WO2020238169A1 - Micro led芯片、制备方法及显示面板 - Google Patents

Micro led芯片、制备方法及显示面板 Download PDF

Info

Publication number
WO2020238169A1
WO2020238169A1 PCT/CN2019/126142 CN2019126142W WO2020238169A1 WO 2020238169 A1 WO2020238169 A1 WO 2020238169A1 CN 2019126142 W CN2019126142 W CN 2019126142W WO 2020238169 A1 WO2020238169 A1 WO 2020238169A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
chip
semiconductor layer
micro
sub
Prior art date
Application number
PCT/CN2019/126142
Other languages
English (en)
French (fr)
Inventor
樊勇
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/626,530 priority Critical patent/US11316069B2/en
Publication of WO2020238169A1 publication Critical patent/WO2020238169A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • This application relates to the display field, and in particular to a micro LED chip, a manufacturing method and a display panel.
  • Micro-LEDs have become the focus of the development of a new generation of display technology due to their higher brightness, better luminous efficiency, and lower power consumption.
  • the driving thin film transistor mainly works in the saturation region during display, the cross-voltage across the source and drain of the TFT is large, while the cross-voltage of the Micro LED is low, which makes the driving TFT consume most of the power consumption, resulting in The power consumption increases and the driving efficiency is low.
  • the existing Micro LED display has a serious problem of driving TFT power consumption, which needs to be solved.
  • the present application provides a Micro-LED chip and a preparation method thereof, so as to alleviate the problem of serious power consumption of driving TFT in the existing Micro LED display.
  • This application provides a Micro-LED chip, including:
  • the insulating layer separates the first semiconductor layer, the active layer, and the second semiconductor layer into at least two sub-chips, and the second semiconductor layer in each sub-chip passes through the
  • the current spreading layer is connected to the first semiconductor layer in the next sub-chip, the first electrode is electrically connected to the first semiconductor layer of the first sub-chip, and the second electrode is electrically connected to the last sub-chip The second semiconductor layer.
  • the current diffusion layer covers the second semiconductor layer of the upper sub-chip, and passes through the vias on the insulating layer and the first semiconductor layer of the next sub-chip. Layer connection.
  • the current diffusion layer is partially in contact with the second semiconductor layer of the previous sub-chip, and is connected to the second semiconductor layer of the next sub-chip through the via on the insulating layer.
  • a semiconductor layer connection
  • the first electrode is electrically connected to the first semiconductor layer of the first sub-chip through the current diffusion layer.
  • the first electrode is directly electrically connected to the first semiconductor layer of the first sub-chip.
  • the second electrode is electrically connected to the second semiconductor layer of the last sub-chip through the current diffusion layer.
  • the second electrode is directly electrically connected to the second semiconductor layer of the last sub-chip.
  • the first semiconductor layer is an N-type gallium nitride layer
  • the active layer is a gallium nitride multiple quantum well layer
  • the second semiconductor layer is a P-type gallium nitride layer.
  • the first electrode is an N-type electrode
  • the second electrode is a P-type electrode.
  • the material of the current diffusion layer is tin oxide or graphene.
  • the buffer layer is an intrinsic layer of gallium nitride.
  • this application provides a method for preparing a Micro-LED chip, including:
  • a base substrate Provide a base substrate, and sequentially prepare a buffer layer, an N-type gallium nitride layer, a gallium nitride multiple quantum well layer, and a P-type gallium nitride layer on the base substrate;
  • this application also provides a Micro-LED display panel, which includes a Micro-LED chip, and the Micro-LED chip includes:
  • the insulating layer separates the first semiconductor layer, the active layer, and the second semiconductor layer into at least two sub-chips, and the second semiconductor layer in each sub-chip passes through the
  • the current diffusion layer is connected to the first semiconductor layer in the next sub-chip, the first electrode is electrically connected to the first semiconductor layer of the first sub-chip, and the second electrode is electrically connected to the last sub-chip The second semiconductor layer.
  • the current spreading layer covers the second semiconductor layer of the upper sub-chip, and passes through the via holes on the insulating layer and the first sub-chip The semiconductor layer is connected.
  • the current diffusion layer is partially in contact with the second semiconductor layer of the previous sub-chip, and is connected to the second semiconductor layer of the next sub-chip through the via on the insulating layer.
  • the first semiconductor layer is connected.
  • the first electrode is electrically connected to the first semiconductor layer of the first sub-chip through the current diffusion layer.
  • the first electrode is directly electrically connected to the first semiconductor layer of the first sub-chip.
  • the second electrode is electrically connected to the second semiconductor layer of the last sub-chip through the current diffusion layer.
  • the second electrode is directly electrically connected to the second semiconductor layer of the last sub-chip.
  • the first semiconductor layer is an N-type gallium nitride layer
  • the active layer is a gallium nitride multiple quantum well layer
  • the second semiconductor layer is a P-type nitrogen In the gallium sulfide layer
  • the first electrode is an N-type electrode
  • the second electrode is a P-type electrode.
  • the material of the current diffusion layer is tin oxide or graphene.
  • the Micro-LED chip includes a stacked buffer layer, a first semiconductor layer, an active layer, a second semiconductor layer, an insulating layer, a current diffusion layer, a protective layer, And a first electrode and a second electrode; wherein the insulating layer separates the first semiconductor layer, the active layer, and the second semiconductor layer into at least two sub-chips, and the second semiconductor layer in each sub-chip passes through the current diffusion layer It is connected to the first semiconductor layer in the next sub-chip, the first electrode is electrically connected to the first semiconductor layer of the first sub-chip, and the second electrode is electrically connected to the second semiconductor layer of the last sub-chip.
  • the sub-chips are separated through the insulating layer, and the sub-chips are connected in series through the current diffusion layer, thereby increasing the Micro
  • the cross voltage of the LED reduces the power consumption on the driving TFT and relieves the existing Micro LED displays have serious problems with driving TFT power consumption.
  • Fig. 1 is a schematic structural diagram of a micro-LED chip provided by an embodiment of the application.
  • FIG. 2 is a flow chart of the preparation of the micro-LED chip provided by the embodiment of the application.
  • FIG. 3 is a schematic diagram of a micro-LED pixel driving circuit provided by an embodiment of the application.
  • this application provides a Micro-LED chip that can alleviate this problem.
  • the Micro-LED chip 10 provided by the present application includes the following layers stacked from top to bottom:
  • the buffer layer 101 in one embodiment, is a thicker gallium nitride intrinsic layer with a thickness greater than 2um. This embodiment is only an exemplary description and is not a limitation.
  • the first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 are an N-type gallium nitride layer, and the active layer 103 is a gallium nitride multiple quantum well layer,
  • the second semiconductor layer 104 is a P-type gallium nitride layer, the P-type gallium nitride layer may be a magnesium (Mg) doped gallium nitride layer, and the N-type gallium nitride layer may be a silicon (Si) doped nitride layer.
  • the gallium layer and the gallium nitride quantum well layer may be an indium gallium nitride/gallium nitride (InGaN/GaN) layer repeatedly arranged in sequence.
  • InGaN/GaN indium gallium nitride/gallium nitride
  • This embodiment is only illustrative and not limited.
  • the first The materials of the semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 can be set according to the actual requirements of the Micro-LED chip.
  • the insulating layer 105 is used to separate the first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 into at least two independent sub-chips; in one embodiment, the insulating layer 105 is made of silicon oxide, nitrogen One or more of silicon oxide, silicon oxynitride, aluminum nitride, coated glass, and polyimide, preferably silicon oxide with good light transmittance.
  • the current diffusion layer 106 is used to connect the second semiconductor layer 104 in each sub-chip with the first semiconductor layer 102 in the next sub-chip to form an ohmic contact, so that the holes and/or generated in the P-type semiconductor layer Or electrons generated in the N-type semiconductor layer can be effectively injected into the active layer, thereby increasing the luminous efficiency of the Micro-LED display panel.
  • the current diffusion layer 106 also plays a role of reflecting light.
  • the material of the current diffusion layer 106 is graphene, indium tin oxide, zinc oxide, nickel, silver, aluminum, gold, platinum, palladium, magnesium, tungsten and other materials with good electrical conductivity and reflective properties.
  • the current diffusion layer 106 may be a single-layer structure or a multilayer structure.
  • the protective layer 107 is used to cover and insulate the current diffusion layer 106, while isolating water and oxygen and heat conduction, and slowing down the performance degradation of each layer in the Micro-LED chip 10, thereby prolonging the service life of the Micro-LED chip.
  • the material of the protective layer 107 is any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, preferably silicon nitride, silicon oxynitride, aluminum nitride, etc. having good thermal conductivity. material.
  • the first electrode 108 and the second electrode 109, the first electrode 108 is electrically connected to the first semiconductor layer 102 of the first sub-chip, and the second electrode 109 is electrically connected to the second semiconductor layer 104 of the last sub-chip.
  • the first electrode 108 is an N-type electrode
  • the second electrode 109 is a P-type electrode.
  • the material is indium, tin, zinc, nickel, silver, aluminum, gold, platinum, palladium, magnesium, tungsten, etc.
  • One or more of the metals or alloys may adopt a single-layer metal structure or a multilayer metal structure.
  • the N-type semiconductor layer 102, the active layer 103, and the P-type semiconductor layer 104 constitute a light-emitting PN junction.
  • the external circuit can be applied to the light-emitting PN junction.
  • the voltage is applied, electrons and holes are generated in the N-type semiconductor layer 102 and the P-type semiconductor layer 104, respectively.
  • the generated electrons and holes are injected into the active layer 103, and recombine and emit photons in the active layer 103 to realize Micro -LED electroluminescence.
  • the N-type semiconductor layer 102 of the first sub-chip is electrically connected to the N-type electrode 108
  • the P-type semiconductor layer 104 of the first sub-chip and the N-type semiconductor layer of the second sub-chip are electrically connected through the current diffusion layer 106
  • the second sub-chip The P-type semiconductor layer 104 of the third sub-chip is electrically connected to the N-type semiconductor layer of the third sub-chip through the current spreading layer 106
  • the P-type semiconductor layer 104 of the last sub-chip is electrically connected to the P-type electrode 109 to realize each sub-chip.
  • each sub-chip When the external circuit is connected through the N-type electrode and the P-type electrode and an external voltage is applied to the Micro-LED chip provided in this embodiment, each sub-chip will obtain a working voltage and simultaneously emit light through the electroluminescence effect. In this way, The entire Micro-LED chip will require a corresponding multiple of the operating voltage of a single sub-chip, thereby increasing the voltage drop of the entire Micro-LED chip.
  • the embodiment of the application provides a Micro-LED chip, which divides the Micro-LED chip into a number of independent sub-chips through an insulating layer, and connects the second semiconductor layer in the upper sub-chip to the lower sub-chip through the current diffusion layer.
  • the first semiconductor layer in a sub-chip is connected to realize the series connection between the sub-chips, thereby increasing the Micro
  • the cross voltage of the LED reduces the power consumption on the driving TFT and relieves the existing Micro LED displays have serious problems with driving TFT power consumption.
  • the embodiment shown in Figure 1 only shows the Micro
  • the film structure of the LED chip does not limit the film structure of the Micro LED chip provided in the present application.
  • the film structure design can be performed according to the requirements of the Micro LED chip.
  • connection between the current spreading layer 106 and the second semiconductor layer 104 of the upper sub-chip is to cover the mesa of the second semiconductor layer 104 of the upper sub-chip, and then pass through the via holes on the insulating layer 105 to connect to the next The first semiconductor layer 102 of the chiplets is connected.
  • connection between the current spreading layer 106 and the second semiconductor layer 104 of the upper sub-chip is to contact with the mesa portion of the second semiconductor layer 104 of the upper sub-chip, and then through insulation
  • the via on the layer 105 is connected to the first semiconductor layer 102 of the next sub-chip.
  • the first electrode 108 is electrically connected to the first semiconductor layer 102 of the first sub-chip through the current diffusion layer 106, that is, the first electrode 108 is still in contact with the first semiconductor layer 102 of the first sub-chip.
  • the current diffusion layer 106 remains.
  • the first electrode 108 is directly electrically connected to the first semiconductor layer 102 of the first sub-chip.
  • the second electrode 109 is electrically connected to the second semiconductor layer 104 of the last sub-chip through the current diffusion layer 106.
  • the second electrode 109 is directly electrically connected to the second semiconductor layer 104 of the last sub-chip, that is, the current diffusion layer 106 is not provided at the position where the second electrode 109 contacts the second semiconductor layer 104 of the last sub-chip.
  • an embodiment of the present application also provides a method for preparing a micro-LED chip, including:
  • S1 Provide a base substrate, and sequentially prepare a buffer layer, an N-type gallium nitride layer, a gallium nitride multiple quantum well layer, and a P-type gallium nitride layer on the base substrate.
  • the base substrate is a sapphire substrate, which has the advantages of mature production technology, good stability, high mechanical strength, easy handling and cleaning, and reusability.
  • the base substrate may also be a silicon carbide (SiC) substrate, a silicon (Si) substrate or other available substrate materials, which is not limited in the embodiment of the present application.
  • a buffer layer, an N-type gallium nitride layer, a gallium nitride multiple quantum well layer, and a P-type gallium nitride layer are sequentially grown on the cleaned substrate by MOCVD epitaxial technology, wherein the buffer layer is The thicker gallium nitride layer is greater than 2um.
  • the chip needs to be pickled first, and then rinsed with aqua regia for 30 minutes to clean and remove metal contaminants on the chip surface; then cleaned with concentrated sulfuric acid at room temperature for 5 minutes to remove organic contamination on the surface; Hydrogen fluoride is used to deoxidize the surface of the wafer, and finally rinsed and dried with deionized water.
  • the preset number of sub-chips of the micro-LED chip and the size of each sub-chip determine the predetermined etching area, use photoresist as a mask, and ICP plasma dry etching to remove the P-type gallium nitride layer and the predetermined area
  • the etched region forms a first via hole, and the N-type gallium nitride layer is exposed through the first via hole.
  • ICP plasma dry etching etch the predetermined area of the N-type gallium nitride layer in the first via hole, remove the N-type gallium nitride layer in the predetermined area, and expose the underlying
  • the second via hole is formed in the etched area, and the N-type gallium nitride layer in the first via hole forms an N-type gallium nitride layer mesa.
  • the mesa area meets the ohmic contact requirements of the N-type gallium nitride layer As small as possible.
  • a layer of insulating film is covered on the chip, the insulating film covers the P-type gallium nitride layer, and the N-type gallium nitride layer and the buffer layer are covered by via holes.
  • the material of the insulating layer 105 is one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, coated glass, and polyimide, preferably silicon oxide with good light transmittance.
  • a current diffusion layer is deposited on the chip to cover the exposed P-type semiconductor layer, N-type semiconductor layer, and insulating layer.
  • the material of the current diffusion layer 106 is graphene, indium tin oxide, zinc oxide, nickel, silver, aluminum, gold, platinum, palladium, magnesium, tungsten and other materials with good conductivity and reflectivity.
  • the current diffusion layer 106 can be Single layer structure can also be multi-layer structure.
  • the current spreading layer on the insulating layer on the first side of the first via is etched away to expose the insulating layer.
  • the first side is the side close to the final chiplet.
  • An etching technique is used to remove the current diffusion layer on the insulating layer on the first side of the first via, so that the P-type semiconductor layer and the N-type semiconductor layer in the same sub-chip form an open circuit.
  • a layer of insulating material on the chip is used as a protective layer.
  • the insulating material layer is made of any one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum nitride, preferably with good thermal conductivity. Materials such as silicon nitride, silicon oxynitride, aluminum nitride, etc.
  • the etching technology is used to remove the protective layer on the current diffusion layer of the last sub-chip, and the protective layer in the first via and the second via on the side of the first sub-chip away from the last sub-chip, so that the N-type semiconductor of the first sub-chip is The layer or the current transport layer connected to the N-type semiconductor layer is exposed, and the P-type semiconductor layer or the current transport layer connected to the P-type semiconductor layer of the last sub-chip is exposed for electrode fabrication.
  • N-type electrodes on the exposed N-type semiconductor layer of the first sub-chip or on the exposed current transport layer connected to the N-type semiconductor layer to form an ohmic contact with the N-type semiconductor layer of the first sub-chip; P-type electrodes are prepared on the P-type semiconductor layer of the last sub-chip or on the current transport layer connected with the P-type semiconductor layer to form an ohmic contact with the P-type semiconductor of the last sub-chip.
  • the materials of the N-type electrode and the P-type electrode are one or more of metals or alloys such as indium, tin, zinc, nickel, silver, aluminum, gold, platinum, palladium, magnesium, tungsten, etc.
  • the peeled base substrate can be reused.
  • the embodiment of the application provides a method for preparing a Micro-LED chip.
  • the Micro-LED chip is divided into several independent sub-chips by etching technology, and the sub-chips are separated by an insulating layer, and then the current is diffused.
  • the layer connects the second semiconductor layer in the previous sub-chip with the first semiconductor layer in the next sub-chip, realizing the series connection between the sub-chips, thereby increasing the Micro
  • the cross voltage of the LED reduces the power consumption on the driving TFT and relieves the existing Micro LED displays have serious problems with driving TFT power consumption.
  • the embodiment of the present application also provides a Micro-LED display panel, which includes the Micro-LED chip as shown in FIG. 1.
  • the Micro-LED chip includes a buffer layer, a first semiconductor layer, and an active layer that are sequentially stacked from top to bottom. And a second semiconductor layer, an insulating layer, a current diffusion layer, a protective layer, and a first electrode and a second electrode;
  • the insulating layer separates the first semiconductor layer, the active layer and the second semiconductor layer into at least two sub-chips, and the second semiconductor layer in each sub-chip passes through the current diffusion layer and the first sub-chip
  • the semiconductor layer is connected, the first electrode is electrically connected to the first semiconductor layer of the first sub-chip, and the second electrode is electrically connected to the second semiconductor layer of the last sub-chip.
  • the embodiment of the application provides a Micro-LED display panel.
  • the Micro-LED display panel includes a Micro-LED chip.
  • the Micro-LED chip is divided into several independent sub-chips by an insulating layer, and the current is passed through.
  • the diffusion layer connects the second semiconductor layer in the previous sub-chip with the first semiconductor layer in the next sub-chip, realizing the series connection between the sub-chips, thereby increasing the Micro
  • the cross voltage of the LED reduces the power consumption on the driving TFT and relieves the existing Micro LED displays have serious problems with driving TFT power consumption.
  • the current spreading layer covers the second semiconductor layer of the upper sub-chip, and is connected to the first semiconductor layer of the next sub-chip through the via on the insulating layer.
  • the current spreading layer is partially in contact with the second semiconductor layer of the previous sub-chip, and is connected to the first semiconductor layer of the next sub-chip through a via on the insulating layer.
  • the first electrode is electrically connected to the first semiconductor layer of the first sub-chip through the current diffusion layer.
  • the first electrode is directly electrically connected to the first semiconductor layer of the first sub-chip.
  • the second electrode is electrically connected to the second semiconductor layer of the last chiplet through the current diffusion layer.
  • the second electrode is directly electrically connected to the second semiconductor layer of the last sub-chip.
  • the first semiconductor layer is an N-type gallium nitride layer
  • the active layer is a gallium nitride multiple quantum well layer
  • the second semiconductor layer is a P-type gallium nitride layer
  • the first electrode is an N-type electrode
  • the second electrode is a P-type electrode.
  • the material of the current diffusion layer is tin oxide or graphene.
  • the Micro-LED pixel drive circuit includes pixel unit drive circuits arranged in an array. As shown in FIG. 3, each pixel unit drive circuit includes red (R) and green (G) , Blue (B) three-color sub-pixel driving circuit, taking the 3T1C circuit as an example, each sub-pixel circuit includes a driving transistor T1, a storage capacitor Cst, a first switching transistor T2, a second switching transistor T3, and a Micro-LED, The Micro-LED includes several sub-Micro-LEDs connected in series.
  • the embodiment of the application provides a Micro-LED pixel drive circuit
  • the Micro-LED pixel drive circuit includes a Micro-LED
  • the Micro-LED chip includes a number of sub-Micro-LEDs connected in series; in this way, when the display emits light , Each sub-Micro-LED will get a working voltage.
  • the voltage drop across the entire Micro-LED is the sum of the working voltages of several sub-Micro-LEDs, which greatly increases the cross-voltage of the Micro-LED and reduces the voltage on the driving TFT.
  • the power consumption alleviates the serious power consumption problem of driving TFT in the existing Micro LED display.
  • the number of sub-Micro-LEDs in the red sub-pixel drive circuit, the number of sub-Micro-LEDs in the green sub-pixel drive circuit, and the number of sub-Micro-LEDs in the blue sub-pixel drive circuit The number of Micro-LEDs is the same; in different pixel units, the number of sub-Micro-LEDs in the pixel drive circuit can be the same or different. The specific number can be set according to the actual needs of the Micro-LED display panel, and there is no restriction here.
  • the Micro-LED chip includes a stacked buffer layer, a first semiconductor layer, an active layer, and a second A semiconductor layer, an insulating layer, a current diffusion layer, a protective layer, and a first electrode and a second electrode; wherein the insulating layer separates the first semiconductor layer, the active layer, and the second semiconductor layer into at least two sub-chips, and each The second semiconductor layer in the sub-chip is connected to the first semiconductor layer in the next sub-chip through the current diffusion layer.
  • the first electrode is electrically connected to the first semiconductor layer of the first sub-chip, and the second electrode is electrically connected to the last sub-chip.
  • the second semiconductor layer The sub-chips are separated through the insulating layer, and the sub-chips are connected in series through the current diffusion layer, thereby increasing the Micro
  • the cross voltage of the LED reduces the power consumption on the driving TFT and relieves the existing Micro LED displays have serious problems with driving TFT power consumption.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种Micro-LED芯片(10)、制备方法及显示面板，所述Micro-LED芯片(10)包括相互串联的若干子芯片，其首位子芯片和末位子芯片分别与第一电极(108)连接和第二电极(109)相连，从而增大了Micro LED芯片(10)的跨压，降低了驱动TFT上的功耗，缓解了现有Micro LED显示器存在驱动TFT功耗严重的问题。

Description

micro LED芯片、制备方法及显示面板
本申请要求于2019年5月31日提交中国专利局、申请号为201910466611.8、发明名称为“micro LED芯片及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，尤其涉及一种micro LED芯片、制备方法及显示面板。
 背景技术
微型发光二极管(Micro-LED)由于具有更高的亮度、更好的发光效、以及更低的功耗，成为新一代显示技术发展的重点。
然而，由于显示时，驱动薄膜晶体管(TFT)主要工作在饱和区，TFT源漏极两端跨压大，而Micro LED的跨压低，这就使得驱动TFT上消耗了大部分功耗，导致了功耗增加，驱动效率低。
因此，现有Micro LED显示器存在驱动TFT功耗严重的问题，需要解决。
 技术问题
本申请提供一种Micro-LED芯片及其制备方法，以缓解现有Micro LED显示器存在驱动TFT功耗严重的问题。
 技术解决方案
为解决以上问题，本申请提供的技术方案如下：
本申请提供一种Micro-LED芯片，包括：
层叠设置的缓冲层、第一半导体层、有源层、第二半导体层、绝缘层、电流扩散层、保护层、以及第一电极和第二电极；
其中，所述绝缘层将所述第一半导体层、所述有源层和所述第二半导体层分隔为至少两个子芯片，且每一所述子芯片内的第二半导体层，通过所述电流扩散层与下一所述子芯片内的第一半导体层连接，所述第一电极电连接第一所述子芯片的第一半导体层，所述第二电极电连接最末所述子芯片的第二半导体层。
在本申请提供的Micro-LED芯片中，所述电流扩散层覆盖上一所述子芯片的第二半导体层，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
在本申请提供的Micro-LED芯片中，所述电流扩散层与上一所述子芯片的第二半导体层部分接触，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
在本申请提供的Micro-LED芯片中，所述第一电极通过所述电流扩散层与所述第一子芯片的第一半导体层电连接。
在本申请提供的Micro-LED芯片中，所述第一电极直接与所述第一子芯片的第一半导体层电连接。
在本申请提供的Micro-LED芯片中，所述第二电极通过所述电流扩散层与所述最末子芯片的第二半导体层电连接。
在本申请提供的Micro-LED芯片中，所述第二电极直接与所述最末子芯片的第二半导体层电连接。
在本申请提供的Micro-LED芯片中，所述第一半导体层为N型氮化镓层，所述有源层为氮化镓多量子阱层，所述第二半导体层为P型氮化镓层，所述第一电极为N型电极，所述第二电极为P型电极。
在本申请提供的Micro-LED芯片中，所述电流扩散层的材料为氧化锡或石墨烯。
在本申请提供的Micro-LED芯片中，所述缓冲层为氮化镓本征层。
同时，本申请提供一种Micro-LED芯片的制备方法，包括：
提供衬底基板，并在所述衬底基板上依次制备缓冲层、N型氮化镓层、氮化镓多量子阱层和P型氮化镓层；
对所述P型氮化镓层和氮化镓多量子阱层的预定区域进行刻蚀，形成第一过孔，并露出N型氮化镓层；
对露出的所述N型氮化镓层的预定区域进行刻蚀，形成第二过孔，并露出缓冲层；
在所述P型氮化镓层、所述N型氮化镓层、以及所述缓冲层上制备绝缘层；
刻蚀掉所述N型氮化镓层和部分所述P型氮化镓层上的绝缘层；
在所述P型半导体层、所述N型半导体层、以及所述绝缘层上制备电流扩散层；
刻蚀掉所述第一过孔第一侧边绝缘层上的电流扩散层，露出绝缘层，所述第一侧边为靠近最末子芯片方向的一侧；
在所述电流扩散层和所述绝缘层上制备保护层；
刻蚀掉所述最末子芯片电流扩散层上的保护层，以及第一子芯片远离所述最末子芯片侧的第一过孔和第二过孔内的保护层，露出电流扩散层；
在所述最末子芯片的电流扩散层上制备P型电极，在所述第一子芯片远离所述最末子芯片侧的第一过孔和第二过孔内制备N型电极；
粘合临时基板；
剥离所述衬底基板。
同时，本申请还提供一种Micro-LED显示面板，其包括Micro-LED芯片，所述Micro-LED芯片包括：
层叠设置的缓冲层、第一半导体层、有源层、第二半导体层、绝缘层、电流扩散层、保护层、以及第一电极和第二电极；
其中，所述绝缘层将所述第一半导体层、所述有源层和所述第二半导体层分隔为至少两个子芯片，且每一所述子芯片内的第二半导体层，通过所述电流扩散层与下一所述子芯片内的第一半导体层连接，所述第一电极电连接第一所述子芯片的第一半导体层，所述第二电极电连接最末所述子芯片的第二半导体层。
在本申请提供的Micro-LED显示面板中，所述电流扩散层覆盖上一所述子芯片的第二半导体层，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
在本申请提供的Micro-LED显示面板中，所述电流扩散层与上一所述子芯片的第二半导体层部分接触，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
在本申请提供的Micro-LED显示面板中，所述第一电极通过所述电流扩散层与所述第一子芯片的第一半导体层电连接。
在本申请提供的Micro-LED显示面板中，所述第一电极直接与所述第一子芯片的第一半导体层电连接。
在本申请提供的Micro-LED显示面板中，所述第二电极通过所述电流扩散层与所述最末子芯片的第二半导体层电连接。
在本申请提供的Micro-LED显示面板中，所述第二电极直接与所述最末子芯片的第二半导体层电连接。
在本申请提供的Micro-LED显示面板中，所述第一半导体层为N型氮化镓层，所述有源层为氮化镓多量子阱层，所述第二半导体层为P型氮化镓层，所述第一电极为N型电极，所述第二电极为P型电极。
在本申请提供的Micro-LED显示面板中，所述电流扩散层的材料为氧化锡或石墨烯。
 有益效果
本申请提供一种Micro-LED芯片及其制备方法，其Micro-LED芯片包括层叠设置的缓冲层、第一半导体层、有源层、第二半导体层、绝缘层、电流扩散层、保护层、以及第一电极和第二电极；其中，绝缘层将第一半导体层、有源层和第二半导体层分隔为至少两个子芯片，且每一子芯片内的第二半导体层，通过电流扩散层与下一子芯片内的第一半导体层连接，第一电极电连接第一子芯片的第一半导体层，第二电极电连接最末子芯片的第二半导体层。通过绝缘层实现了子芯片的分隔，通过电流扩散层实现了子芯片的串联，从而增大了Micro LED的跨压，降低了驱动TFT上的功耗，缓解了现有Micro LED显示器存在驱动TFT功耗严重的问题。
 附图说明
图1为本申请实施例提供的micro-LED芯片的结构示意图。
图2为本申请实施例提供的micro-LED芯片的制备流程图。
图3为本申请实施例提供的micro-LED像素驱动电路示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有Micro LED显示器存在驱动TFT功耗严重的问题，本申请提供一种Micro-LED芯片可以缓解这个问题。
在一种实施例中，如图1所示，本申请提供的Micro-LED芯片10包括由上到下依次层叠设置的：
缓冲层101，在一种实施例中，缓冲层101为较厚的氮化镓本征层，其厚度大于2um，该实施例仅为示例性说明，并非限定。
第一半导体层102、有源层103和第二半导体层104，在一种实施例中，第一半导体层102为N型氮化镓层，有源层103为氮化镓多量子阱层，第二半导体层104为P型氮化镓层，P型氮化镓层可为镁(Mg)掺杂的氮化镓层，N型氮化镓层可为硅(Si)掺杂的氮化镓层，氮化镓量子阱层可为依次重复排列的氮化铟镓/氮化镓(InGaN/GaN)层，该实施例仅为示例性说明，并非限定，在其他实施例中，第一半导体层102、有源层103和第二半导体层104的材料可根据Micro-LED芯片的实际需求设置。
绝缘层105，用于将第一半导体层102、有源层103和第二半导体层104分隔为至少两个独立的子芯片；在一种实施例中，绝缘层105的材料为氧化硅、氮化硅、氮氧化硅、氮化铝、涂布玻璃、聚酰亚胺中的一种或几种，优选透光性能良好的氧化硅。
电流扩散层106，用于将每一子芯片内的第二半导体层104，与下一子芯片内的第一半导体层102连接，形成欧姆接触，使P型半导体层中产生的空穴和/或N型半导体层中产生的电子能有效地注入有源层中，从而增加Micro-LED显示面板的发光效率。同时，电流扩散层106还起到反射光的作用。在一种实施例中，电流扩散层106的材料为石墨烯、氧化铟锡、氧化锌、镍、银、铝、金、铂、钯、镁、钨等导电性和反射性能都较好的材料，电流扩散层106可以是单层结构，也可以是多层结构。
保护层107，用于覆盖和隔绝电流扩散层106，同时隔绝水氧和导热，减缓Micro-LED芯片10中各膜层性能的衰减，从而延长Micro-LED芯片的使用寿命。在一中实施例中，保护层107的材料为氧化硅、氮化硅、氮氧化硅、氮化铝中的任一种，优选导热性良好的氮化硅、氮氧化硅、氮化铝等材料。
第一电极108和第二电极109，第一电极108电连接第一子芯片的第一半导体层102，第二电极109电连接最末子芯片的第二半导体层104。正在一种实施例中，第一电极108为N型电极，第二电极109为P型电极，其材料为铟、锡、锌、镍、银、铝、金、铂、钯、镁、钨等金属或合金中的一种或几种，可以采用单层金属结构，也可以采用多层金属结构。
在每一子芯片内，N型半导体层102、有源层103和P型半导体层104构成发光PN结，当将所述发光PN结连接到外电路中，实现通过外电路给发光PN结施加电压时，N型半导体层102和P型半导体层104内分别产生电子和空穴，产生的电子和空穴均注入到有源层103内，并在有源层103内复合发出光子，实现Micro-LED的电致发光。
第一子芯片的N型半导体层102与N型电极108电连接，第一子芯片的P型半导体层104与第二子芯片的N型半导体层通过电流扩散层106电连接，第二子芯片的P型半导体层104与第三子芯片的N型半导体层通过电流扩散层106电连接，依次向后，最末子芯片的P型半导体层104与P型电极109电连接，实现了各个子芯片的串联。当通过N型电极和P型电极连接外电路并对本实施例提供的Micro-LED芯片施加外电压时，各子芯片将各自获得一份工作电压，并同时通过电致发光效应发光显示，如此，整个Micro-LED芯片将需要单个子芯片相应倍数的工作电压，从而增加了整个Micro-LED芯片的压降。
本申请实施例提供了一种Micro-LED芯片，其通过绝缘层将Micro-LED芯片分隔为若干个相互独立的子芯片，并通过电流扩散层将上一子芯片内的第二半导体层与下一子芯片内的第一半导体层连接，实现了各子芯片之间的串联，从而增大了Micro LED的跨压，降低了驱动TFT上的功耗，缓解了现有Micro LED显示器存在驱动TFT功耗严重的问题。
图1所示的实施例仅展示出了本申请提供的Micro LED芯片的一种膜层结构，并非对本申请提供的Micro LED芯片膜层结构做限定，在其他实施例中，可根据Micro LED芯片的需求进行膜层结构设计。
在一种实施例中，电流扩散层106与上一子芯片第二半导体层104的连接方式为覆盖上一子芯片第二半导体层104的台面，然后通过绝缘层105上的过孔与下一子芯片的第一半导体层102连接。
在另一种实施例中，如图1所示，电流扩散层106与上一子芯片第二半导体层104的连接方式为与上一子芯片第二半导体层104的台面部分接触，然后通过绝缘层105上的过孔与下一子芯片的第一半导体层102连接。
在一种实施例中，第一电极108通过电流扩散层106与第一子芯片的第一半导体层102电连接，即第一电极108与第一子芯片第一半导体层102接触的台面上任然保留有电流扩散层106。
在另一种实施例中，如图1所示，第一电极108直接与第一子芯片的第一半导体层102电连接。
在一种实施例中，如图1所示，第二电极109通过电流扩散层106与最末子芯片的第二半导体层104电连接。
在另一种实施例中，第二电极109直接与最末子芯片的第二半导体层104电连接，即第二电极109与最末子芯片第二半导体层104接触的位置未设置电流扩散层106。
同时，如图2所示，本申请实施例还提供一种micro-LED芯片的制备方法，包括：
S1、提供衬底基板，并在衬底基板上依次制备缓冲层、N型氮化镓层、氮化镓多量子阱层和P型氮化镓层。
在一种实施例中，衬底基板为蓝宝石衬底，蓝宝石衬底基板具有生产技术成熟、稳定性很好、机械强度高、易于处理和清洗、以及可重复利用等优点。衬底基板还可以为碳化硅(SiC)衬底、硅(Si)衬底或者其它可用的衬底材料，本申请实施例对此不做限定。
在一种实施例中，通过MOCVD外延技术在清洗过后的衬底基板上依次生长缓冲层、N型氮化镓层、氮化镓多量子阱层和P型氮化镓层，其中缓冲层为较厚的氮化镓层，厚度大于2um。在P型氮化镓层生长完之后，需对芯片进行先进行酸洗，用王水冲温腐蚀30分钟，清洗去除芯片表面的金属污染物；然后通过浓硫酸常温清洗5分钟，去除表面有机物污染；再用氟化氢进行晶圆表面去氧化层处理，最后用去离子水冲洗甩干。
S2、对P型氮化镓层和氮化镓多量子阱层的预定区域进行刻蚀，形成第一过孔，并露出N型氮化镓层。
根据micro-LED芯片预设子芯片数量以及各子芯片的尺寸，确定预定刻蚀区域，利用光刻胶作为掩膜，ICP等离子体干法蚀刻，去除预定区域内的P型氮化镓层和氮化镓多量子阱层，刻蚀区域形成第一过孔，通过第一过孔露出N型氮化镓层。
在该步骤中，对露出的N型氮化镓层的预定区域的刻蚀还可以采用其他的方法手段，不限于ICP等离子体干法蚀刻。
S3、对露出的N型氮化镓层的预定区域进行刻蚀，形成第二过孔，并露出缓冲层。
以光刻胶作为掩膜，ICP等离子体干法蚀刻，对第一过孔内N型氮化镓层的预定区域进行刻蚀，去除预定区域内的N型氮化镓层，露出位于其下的缓冲层，刻蚀区域形成第二过孔，同时第一过孔内的N型氮化镓层形成N型氮化镓层台面，台面面积在满足N型氮化镓层的欧姆接触要求时尽可能小。
在该步骤中，对露出的N型氮化镓层的预定区域的刻蚀还可以采用其他的方法手段，如湿法腐蚀等，不限于ICP等离子体干法蚀刻。
S4、在P型氮化镓层、N型氮化镓层、以及缓冲层上制备绝缘层。
采用等离子增强型化学气相沉积(PECVD)等技术，在芯片上覆盖一层绝缘薄膜层，绝缘层薄膜覆盖P型氮化镓层，并通过过孔遮盖N型氮化镓层和以及缓冲层。绝缘层105的材料为氧化硅、氮化硅、氮氧化硅、氮化铝、涂布玻璃、聚酰亚胺中的一种或几种，优选透光性能良好的氧化硅。
S5、刻蚀掉N型氮化镓层和部分P型氮化镓层上的绝缘层。
利用刻蚀技术去除N型氮化镓层上的绝缘层，露出N型氮化镓层的台面，去除部分P型氮化镓层上的绝缘层，露出部分P型氮化镓层上的绝缘层。
S6、在P型半导体层、N型半导体层、以及绝缘层上制备电流扩散层。
采用磁控溅射或热蒸发等技术，在芯片上沉积一层电流扩散层，覆盖外露的P型半导体层、N型半导体层、以及绝缘层。电流扩散层106的材料为石墨烯、氧化铟锡、氧化锌、镍、银、铝、金、铂、钯、镁、钨等导电性和反射性能都较好的材料，电流扩散层106可以是单层结构，也可以是多层结构。
S7、刻蚀掉第一过孔第一侧边绝缘层上的电流扩散层，露出绝缘层，所述第一侧边为靠近最末子芯片方向的一侧。
采用刻蚀技术去除第一过孔第一侧边绝缘层上的电流扩散层，使得同一子芯片内的P型半导体层和N型半导体层形成断路。
S8、在电流扩散层和绝缘层上制备保护层。
在芯片上的再覆盖一层的绝缘材料层作为保护层，具体地，绝缘材料层采用氧化硅、氮化硅、氮氧化硅、氮化铝中的任一种制成，优选导热性良好的氮化硅、氮氧化硅、氮化铝等材料。
S9、刻蚀掉最末子芯片电流扩散层上的保护层，以及第一子芯片远离最末子芯片侧的第一过孔和第二过孔内的保护层，露出电流扩散层。
采用刻蚀技术去除最末子芯片电流扩散层上的保护层，以及第一子芯片远离最末子芯片侧的第一过孔和第二过孔内的保护层，使得第一子芯片的N型半导体层或与N型半导体层连接的电流传输层露出来，最末子芯片P型半导体层或者与P型半导体层连接的电流传输层露出来，以备电极制作。
S10、在最末子芯片的电流扩散层上制备P型电极，在第一子芯片远离最末子芯片侧的第一过孔和第二过孔内制备N型电极。
在外露的第一子芯片的N型半导体层上，或外露的与N型半导体层上连接的电流传输层上制备N型电极，与第一子芯片的N型半导体层形成欧姆接触；在最末子芯片的P型半导体层上，或与P型半导体层连接的电流传输层上制备P型电极，与最末子芯片的P型半导体形成欧姆接触。N型电极和P型电极的材料为铟、锡、锌、镍、银、铝、金、铂、钯、镁、钨等金属或合金中的一种或几种，
S11、粘合临时基板。
S12、剥离衬底基板。剥离的衬底基板可重复利用。
本申请实施例提供了一种Micro-LED芯片的制备方法，通过刻蚀技术将Micro-LED芯片分隔为若干个彼此独立的子芯片，并通过绝缘层将子芯片隔离开来，再通过电流扩散层将上一子芯片内的第二半导体层与下一子芯片内的第一半导体层连接，实现了各子芯片之间的串联，从而增大了Micro LED的跨压，降低了驱动TFT上的功耗，缓解了现有Micro LED显示器存在驱动TFT功耗严重的问题。
本申请实施例还提供一种Micro-LED显示面板，其包括如图1所示的Micro-LED芯片，Micro-LED芯片包括上到下依次层叠设置的缓冲层、第一半导体层、有源层和第二半导体层、绝缘层、电流扩散层、保护层、以及第一电极和第二电极；
其中，绝缘层将第一半导体层、有源层和第二半导体层分隔为至少两个子芯片，且每一子芯片内的第二半导体层，通过电流扩散层与下一子芯片内的第一半导体层连接，第一电极电连接第一子芯片的第一半导体层，第二电极电连接最末子芯片的第二半导体层。
本申请实施例提供了一种Micro-LED显示面板，该Micro-LED显示面板包括Micro-LED芯片，所述Micro-LED芯片通过绝缘层将自身分隔为若干个相互独立的子芯片，并通过电流扩散层将上一子芯片内的第二半导体层与下一子芯片内的第一半导体层连接，实现了各子芯片之间的串联，从而增大了Micro LED的跨压，降低了驱动TFT上的功耗，缓解了现有Micro LED显示器存在驱动TFT功耗严重的问题。
在一种实施例中，电流扩散层覆盖上一子芯片的第二半导体层，且通过绝缘层上的过孔与下一子芯片的第一半导体层连接。
在一种实施例中，电流扩散层与上一子芯片的第二半导体层部分接触，且通过绝缘层上的过孔与下一子芯片的第一半导体层连接。
在一种实施例中，第一电极通过电流扩散层与第一子芯片的第一半导体层电连接。
在一种实施例中，第一电极直接与第一子芯片的第一半导体层电连接。
在一种实施例中，第二电极通过电流扩散层与最末子芯片的第二半导体层电连接。
在一种实施例中，第二电极直接与最末子芯片的第二半导体层电连接。
在一种实施例中，第一半导体层为N型氮化镓层，有源层为氮化镓多量子阱层，第二半导体层为P型氮化镓层，第一电极为N型电极，第二电极为P型电极。
在一种实施例中，电流扩散层的材料为氧化锡或石墨烯。
本申请还提供一种Micro-LED像素驱动电路，Micro-LED像素驱动电路包括阵列设置的像素单元驱动电路，如图3所示，每个像素单元驱动电路包括红（R）、绿（G）、蓝（B）三色子像素驱动电路，以3T1C电路为例，每一子像素电路又包括驱动晶体管T1、存储电容Cst、第一开关晶体管T2、第二开关晶体管T3，以及Micro-LED，所述Micro-LED包括若干个相互串联的子Micro-LED。
本申请实施例提供了一种Micro-LED像素驱动电路，该Micro-LED像素驱动电路包括Micro-LED，所述Micro-LED芯片包括若干个相互串联的子Micro-LED；如此，在显示发光时，各子Micro-LED将各自获得一份工作电压，整个Micro-LED上的压降即为若干个子Micro-LED工作电压的总和，从而大大增加了Micro LED的跨压，降低了驱动TFT上的功耗，缓解了现有Micro LED显示器存在驱动TFT功耗严重的问题。
在一种实施例中，在同一像素单元内，红光子像素驱动电路中的子Micro-LED的数量、绿光子像素驱动电路中的子Micro-LED的数量、和蓝光子像素驱动电路中的子Micro-LED的数量均相同；在不同像素单元内，像素驱动电路中的子Micro-LED的数量可以相同，也可以不同。具体的数量可根据Micro-LED显示面板的实际需求进行设置，在此不做限制。
根据上述实施例可知：
本申请提供一种Micro-LED芯片及其制备方法、Micro-LED显示面板、Micro-LED像素驱动电路，其Micro-LED芯片包括层叠设置的缓冲层、第一半导体层、有源层、第二半导体层、绝缘层、电流扩散层、保护层、以及第一电极和第二电极；其中，绝缘层将第一半导体层、有源层和第二半导体层分隔为至少两个子芯片，且每一子芯片内的第二半导体层，通过电流扩散层与下一子芯片内的第一半导体层连接，第一电极电连接第一子芯片的第一半导体层，第二电极电连接最末子芯片的第二半导体层。通过绝缘层实现了子芯片的分隔，通过电流扩散层实现了子芯片的串联，从而增大了Micro LED的跨压，降低了驱动TFT上的功耗，缓解了现有Micro LED显示器存在驱动TFT功耗严重的问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种Micro-LED芯片，其包括：
    层叠设置的缓冲层、第一半导体层、有源层、第二半导体层、绝缘层、电流扩散层、保护层、以及第一电极和第二电极；
    其中，所述绝缘层将所述第一半导体层、所述有源层和所述第二半导体层分隔为至少两个子芯片，且每一所述子芯片内的第二半导体层，通过所述电流扩散层与下一所述子芯片内的第一半导体层连接，所述第一电极电连接第一所述子芯片的第一半导体层，所述第二电极电连接最末所述子芯片的第二半导体层。
  2. 如权利要求1所述的Micro-LED芯片，其中，所述电流扩散层覆盖上一所述子芯片的第二半导体层，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
  3. 如权利要求1所述的Micro-LED芯片，其中，所述电流扩散层与上一所述子芯片的第二半导体层部分接触，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
  4. 如权利要求1所述的Micro-LED芯片，其中，所述第一电极通过所述电流扩散层与所述第一子芯片的第一半导体层电连接。
  5. 如权利要求1所述的Micro-LED芯片，其中，所述第一电极直接与所述第一子芯片的第一半导体层电连接。
  6. 如权利要求1所述的Micro-LED芯片，其中，所述第二电极通过所述电流扩散层与所述最末子芯片的第二半导体层电连接。
  7. 如权利要求1所述的Micro-LED芯片，其中，所述第二电极直接与所述最末子芯片的第二半导体层电连接。
  8. 如权利要求1所述的Micro-LED芯片，其中，所述第一半导体层为N型氮化镓层，所述有源层为氮化镓多量子阱层，所述第二半导体层为P型氮化镓层，所述第一电极为N型电极，所述第二电极为P型电极。
  9. 如权利要求1所述的Micro-LED芯片，其中，所述电流扩散层的材料为氧化锡或石墨烯。
  10. 如权利要求1所述的Micro-LED芯片，其中，所述缓冲层为氮化镓本征层。
  11. 一种Micro-LED芯片的制备方法，其包括：
    提供衬底基板，并在所述衬底基板上依次制备缓冲层、N型氮化镓层、氮化镓多量子阱层和P型氮化镓层；
    对所述P型氮化镓层和氮化镓多量子阱层的预定区域进行刻蚀，形成第一过孔，并露出N型氮化镓层；
    对露出的所述N型氮化镓层的预定区域进行刻蚀，形成第二过孔，并露出缓冲层；
    在所述P型氮化镓层、所述N型氮化镓层、以及所述缓冲层上制备绝缘层；
    刻蚀掉所述N型氮化镓层和部分所述P型氮化镓层上的绝缘层；
    在所述P型半导体层、所述N型半导体层、以及所述绝缘层上制备电流扩散层；
    刻蚀掉所述第一过孔第一侧边绝缘层上的电流扩散层，露出绝缘层，所述第一侧边为靠近最末子芯片方向的一侧；
    在所述电流扩散层和所述绝缘层上制备保护层；
    刻蚀掉所述最末子芯片电流扩散层上的保护层，以及第一子芯片远离所述最末子芯片侧的第一过孔和第二过孔内的保护层，露出电流扩散层；
    在所述最末子芯片的电流扩散层上制备P型电极，在所述第一子芯片远离所述最末子芯片侧的第一过孔和第二过孔内制备N型电极；
    粘合临时基板；
    剥离所述衬底基板。
  12. 一种Micro-LED显示面板，其包括Micro-LED芯片，所述Micro-LED芯片包括：
    层叠设置的缓冲层、第一半导体层、有源层、第二半导体层、绝缘层、电流扩散层、保护层、以及第一电极和第二电极；
    其中，所述绝缘层将所述第一半导体层、所述有源层和所述第二半导体层分隔为至少两个子芯片，且每一所述子芯片内的第二半导体层，通过所述电流扩散层与下一所述子芯片内的第一半导体层连接，所述第一电极电连接第一所述子芯片的第一半导体层，所述第二电极电连接最末所述子芯片的第二半导体层。
  13. 如权利要求12所述的Micro-LED显示面板，其中，所述电流扩散层覆盖上一所述子芯片的第二半导体层，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
  14. 如权利要求12所述的Micro-LED显示面板，其中，所述电流扩散层与上一所述子芯片的第二半导体层部分接触，且通过所述绝缘层上的过孔与下一所述子芯片的第一半导体层连接。
  15. 如权利要求12所述的Micro-LED显示面板，其中，所述第一电极通过所述电流扩散层与所述第一子芯片的第一半导体层电连接。
  16. 如权利要求12所述的Micro-LED显示面板，其中，所述第一电极直接与所述第一子芯片的第一半导体层电连接。
  17. 如权利要求12所述的Micro-LED显示面板，其中，所述第二电极通过所述电流扩散层与所述最末子芯片的第二半导体层电连接。
  18. 如权利要求12所述的Micro-LED显示面板，其中，所述第二电极直接与所述最末子芯片的第二半导体层电连接。
  19. 如权利要求12所述的Micro-LED显示面板，其中，所述第一半导体层为N型氮化镓层，所述有源层为氮化镓多量子阱层，所述第二半导体层为P型氮化镓层，所述第一电极为N型电极，所述第二电极为P型电极。
  20. 如权利要求12所述的Micro-LED显示面板，其中，所述电流扩散层的材料为氧化锡或石墨烯。
PCT/CN2019/126142 2019-05-31 2019-12-18 Micro led芯片、制备方法及显示面板 WO2020238169A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/626,530 US11316069B2 (en) 2019-05-31 2019-12-18 Micro-LED chip and manufacturing method thereof, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910466611.8A CN110224049A (zh) 2019-05-31 2019-05-31 micro LED芯片及其制备方法
CN201910466611.8 2019-05-31

Publications (1)

Publication Number Publication Date
WO2020238169A1 true WO2020238169A1 (zh) 2020-12-03

Family

ID=67818872

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/126142 WO2020238169A1 (zh) 2019-05-31 2019-12-18 Micro led芯片、制备方法及显示面板

Country Status (3)

Country Link
US (1) US11316069B2 (zh)
CN (1) CN110224049A (zh)
WO (1) WO2020238169A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115172565A (zh) * 2022-07-12 2022-10-11 厦门大学 一种倒装深紫外发光二极管芯片

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110224049A (zh) 2019-05-31 2019-09-10 深圳市华星光电半导体显示技术有限公司 micro LED芯片及其制备方法
CN110634839B (zh) * 2019-09-26 2021-11-26 京东方科技集团股份有限公司 微发光二极管显示基板、装置及制备方法
CN114823771A (zh) * 2021-04-20 2022-07-29 友达光电股份有限公司 半导体装置以及显示装置
CN117438512A (zh) * 2023-12-21 2024-01-23 江西兆驰半导体有限公司 一种高压Micro LED芯片及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060169993A1 (en) * 2005-02-03 2006-08-03 Zhaoyang Fan Micro-LED based high voltage AC/DC indicator lamp
CN101026204A (zh) * 2006-02-24 2007-08-29 中国科学院半导体研究所 利用倒装技术制作功率型微结构发光二极管管芯的方法
CN108365061A (zh) * 2018-02-06 2018-08-03 映瑞光电科技(上海)有限公司 一种led芯片及其制造方法
CN109742197A (zh) * 2018-12-22 2019-05-10 复旦大学 一种内窥镜micro-LED光源及其制备方法
CN110224049A (zh) * 2019-05-31 2019-09-10 深圳市华星光电半导体显示技术有限公司 micro LED芯片及其制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070090488A1 (en) * 2005-10-24 2007-04-26 Tyntek Corporation High-efficiency matrix-type LED device
CN101118920B (zh) * 2006-08-02 2010-07-21 海立尔股份有限公司 次粘着基台式及具有阻抗元件的高压发光二极管晶片
CN101072464A (zh) * 2006-10-06 2007-11-14 范朝阳 带有集成保护功能的交直流发光二极管
US7714348B2 (en) 2006-10-06 2010-05-11 Ac-Led Lighting, L.L.C. AC/DC light emitting diodes with integrated protection mechanism
KR100928259B1 (ko) * 2007-10-15 2009-11-24 엘지전자 주식회사 발광 장치 및 그 제조방법
KR101891777B1 (ko) * 2012-06-25 2018-08-24 삼성전자주식회사 유전체 리플렉터를 구비한 발광소자 및 그 제조방법
US10615311B2 (en) * 2016-04-22 2020-04-07 Lg Innotek Co., Ltd. Light emitting device and display comprising same
KR20180052256A (ko) * 2016-11-10 2018-05-18 엘지이노텍 주식회사 반도체 소자
CN107516701B (zh) * 2017-07-14 2019-06-11 华灿光电(苏州）有限公司 一种高压发光二极管芯片及其制作方法
CN111276595A (zh) * 2018-12-04 2020-06-12 展晶科技(深圳)有限公司 发光二极管及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060169993A1 (en) * 2005-02-03 2006-08-03 Zhaoyang Fan Micro-LED based high voltage AC/DC indicator lamp
CN101026204A (zh) * 2006-02-24 2007-08-29 中国科学院半导体研究所 利用倒装技术制作功率型微结构发光二极管管芯的方法
CN108365061A (zh) * 2018-02-06 2018-08-03 映瑞光电科技(上海)有限公司 一种led芯片及其制造方法
CN109742197A (zh) * 2018-12-22 2019-05-10 复旦大学 一种内窥镜micro-LED光源及其制备方法
CN110224049A (zh) * 2019-05-31 2019-09-10 深圳市华星光电半导体显示技术有限公司 micro LED芯片及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115172565A (zh) * 2022-07-12 2022-10-11 厦门大学 一种倒装深紫外发光二极管芯片

Also Published As

Publication number Publication date
CN110224049A (zh) 2019-09-10
US20210336078A1 (en) 2021-10-28
US11316069B2 (en) 2022-04-26

Similar Documents

Publication Publication Date Title
WO2020238169A1 (zh) Micro led芯片、制备方法及显示面板
JP3543170B2 (ja) 電界発光素子及びその製造方法
JP5554792B2 (ja) 発光素子及びその製造方法
CN108878468B (zh) 一种显示基板及其制作方法、显示面板、显示装置
KR20100074352A (ko) 복수개의 발광셀들을 갖는 발광 소자 및 그것을 제조하는 방법
CN102017193A (zh) 具有双面钝化的半导体发光器件
KR102495758B1 (ko) 플립칩 타입의 led 소자, 플립칩 타입의 led 소자의 제조 방법 및 플립칩 타입의 led 소자를 포함하는 디스플레이 장치
WO2023071910A1 (zh) Micro-LED芯片结构及其制作方法
US10490701B2 (en) Light emitting diode chip
WO2015003564A1 (zh) 一种氮化镓基发光二极管及其制作方法
WO2020181859A1 (zh) 无机发光二极管芯片、其制备方法及显示基板
CN106981563A (zh) 一种功率型紫外led器件
CN109037268B (zh) 微型发光二极管显示器、微型发光二极管元件及其制法
CN112968080B (zh) 一种红光led芯片及制备方法
US20220344311A1 (en) High-voltage flip-chip semiconductor light-emitting device
JP2008270616A (ja) 半導体発光装置の製造方法および半導体発光装置
CN113270522A (zh) 一种微发光二极管芯片、其制作方法及显示装置
CN102067340A (zh) 具有在p-型层内钝化的半导体发光器件
WO2020238395A1 (zh) LED芯片及其制备方法、芯片晶圆、Micro-LED显示装置
WO2023134418A1 (zh) 集成式led结构及制备方法
CN113594198B (zh) 微发光二极管显示器件及其制作方法
CN101116191A (zh) 具有多个发光单元的发光装置及其制造方法
TWI667786B (zh) 發光二極體顯示器及其製造方法
WO2015074353A1 (zh) 一种半导体发光二极管芯片
CN114975718A (zh) 一种高稳定性倒装led芯片及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19930322

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19930322

Country of ref document: EP

Kind code of ref document: A1