WO2024109459A1 - 半导体结构、半导体器件、电子设备及晶圆键合方法 - Google Patents

半导体结构、半导体器件、电子设备及晶圆键合方法 Download PDF

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WO2024109459A1
WO2024109459A1 PCT/CN2023/127641 CN2023127641W WO2024109459A1 WO 2024109459 A1 WO2024109459 A1 WO 2024109459A1 CN 2023127641 W CN2023127641 W CN 2023127641W WO 2024109459 A1 WO2024109459 A1 WO 2024109459A1
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bonding layer
layer
metal
bonding
metal bonding
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PCT/CN2023/127641
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English (en)
French (fr)
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王磊
张利
丁肇夷
蒋府龙
刘金强
杨磊
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET

Definitions

  • the embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a semiconductor structure, a semiconductor device, an electronic device, and a wafer bonding method.
  • Wafer bonding technology is a key technology in the semiconductor manufacturing process. It can bond two wafers with different functions together. Based on this stacking concept, semiconductor devices with higher integration, more functions and smaller size can be obtained.
  • the types of traditional wafer bonding technologies generally include metal-metal direct bonding technology (such as Cu-Cu bonding, Au-Sn bonding, etc.), silicon-silicon direct bonding technology, etc. They have high requirements on the type of bonding material and the flatness of the bonding surface. Otherwise, it is easy to cause poor bonding quality or even bonding failure, which limits the application of wafer bonding process in heterogeneous integration. Therefore, it is necessary to provide a wafer bonding method with strong universality, low bonding difficulty and high bonding strength.
  • an embodiment of the present application provides a wafer bonding method, which can achieve convenient and high-strength bonding between two wafers with any metal bonding layers, and also provides a semiconductor structure and a semiconductor device based on this method.
  • a semiconductor structure including:
  • a first substrate and a plurality of first metal bonding layers wherein the plurality of first metal bonding layers are arranged at intervals on one side of the first substrate, and a first insulating bonding layer is arranged between two adjacent first metal bonding layers;
  • a first device functional layer and multiple second metal bonding layers, the second metal bonding layers are arranged on the side of the first device functional layer facing the first substrate, the multiple first metal bonding layers are arranged one by one opposite to the multiple second metal bonding layers, and a second insulating bonding layer is arranged between two adjacent second metal bonding layers; wherein a conductive layer is also arranged between each first metal bonding layer and the second metal bonding layer opposite thereto, an auxiliary bonding layer is arranged between adjacent conductive layers, and the material of the auxiliary bonding layer is an insulating compound; the conductive layer contains the same element as the positively valenced element in the auxiliary bonding layer, and the reducibility of the material of the first metal bonding layer and/or the second metal bonding layer close to the conductive layer is higher than the reducibility of the conductive layer material.
  • the conductive layer is obtained by reducing the same material as the auxiliary bonding layer through the first metal bonding layer and/or the second metal bonding layer.
  • the conductive layer and the insulating bonding layer separating them can establish a bonding bridge between the structures located on the upper and lower sides thereof, realize high-strength bonding between the upper and lower metal bonding layers and between the upper and lower insulating bonding layers, ensure the overall structural stability of the semiconductor structure, and do not affect the longitudinal conductive connection between the correspondingly arranged first and second metal bonding layers, and ensure the lateral electrical insulation between adjacent first metal bonding layers/adjacent second metal bonding layers along the thickness direction perpendicular to the first substrate.
  • the surface of the conductive layer in contact with the first metal bonding layer or the second metal bonding layer is flat and undamaged.
  • the conductive layer with such characteristics can better play the role of firmly electrically connecting the first metal bonding layer and the second metal bonding layer, ensuring the high structural stability of the semiconductor structure.
  • the first metal bonding layer and/or the interface of the first metal bonding layer close to the conductive layer contains the same element as the negative valence element in the auxiliary bonding layer. This may reflect to a certain extent that the conductive layer is obtained by reducing the same material as the auxiliary bonding layer by the first metal bonding layer and/or the second metal bonding layer, and there may be a covalent bond between the conductive layer and the interface of the upper and lower metal bonding layers, resulting in a higher bonding strength.
  • the auxiliary bonding layer includes one or more of metal oxide, metal nitride, silicon oxide containing doping elements, silicon nitride containing doping elements, and silicon oxynitride containing doping elements; the material of the conductive layer includes silicon element containing doping elements, or element corresponding to the metal element in the metal oxide or the metal nitride.
  • auxiliary bonding layer materials have good hydrophilicity and insulation properties, and with their help, the stable bonding between the upper and lower auxiliary bonding layers in the semiconductor structure can be ensured, and the conductive layer, which is a reduction product of the same material as the auxiliary bonding layer material, has good conductivity, which facilitates the realization of good electrical connection between corresponding layers of the semiconductor structure.
  • the metal elements in the metal oxide and the metal nitride include one or more of aluminum, tantalum, hafnium, and zirconium.
  • the conductive layer containing these elements has good conductivity
  • the auxiliary bonding layer is easier to prepare, and can be reduced by a common metal bonding layer at a lower temperature.
  • the conductive layer and the auxiliary bonding layer are each one layer, and the thickness of the conductive layer and the auxiliary bonding layer are respectively in the range of 0.5nm-10nm.
  • the thinner conductive layer and the auxiliary bonding layer can still ensure the stable bonding between the first and second metal bonding layers and the stable bonding between the first and second auxiliary bonding layers.
  • the auxiliary bonding layer with a two-layer structure can better ensure that when preparing the above-mentioned semiconductor structure, the bonding interfaces in different regions are of the same material, which can better achieve high-strength covalent bonding, and ensure that the reduction reaction proceeds at a high degree, the surface state of each conductive layer is good, and there is no gap between adjacent metal bonding layers, etc., to ensure that the structural stability of the semiconductor structure is higher.
  • the first device functional layer includes a plurality of first device functional sub-layers that are spaced apart from each other, and each second metal bonding layer is provided with a second device functional sub-layer on a side facing away from the first substrate.
  • the semiconductor structure further includes: a second device function layer located between the first substrate and the first metal bonding layer, wherein the second device function layer is arranged in a one-to-one correspondence with the second device function layer.
  • a second device function layer located between the first substrate and the first metal bonding layer, wherein the second device function layer is arranged in a one-to-one correspondence with the second device function layer.
  • the second aspect of the embodiment of the present application provides a semiconductor device, comprising the semiconductor structure described in the first aspect of the embodiment of the present application.
  • the semiconductor device has high structural stability and can stably perform its functions.
  • the semiconductor device may include one of an optoelectronic device, a power device, and a radio frequency device.
  • the third aspect of the embodiment of the present application provides an electronic device, comprising the semiconductor device described in the second aspect of the embodiment of the present application.
  • the electronic device with the semiconductor device can operate stably and has outstanding market competitiveness.
  • the present application also provides a wafer bonding method, comprising the following steps:
  • metal bonding layers on the two wafers respectively, wherein the metal bonding layers are arranged on the first side of the substrate;
  • the two processed wafers are bonded together so that the metal bonding layers on the two wafers are arranged relative to each other, and the two bonded wafers are heat-treated so that the original auxiliary bonding layer sandwiched between the corresponding metal bonding layers in the two wafers is reduced to a conductive layer.
  • the above wafer bonding method by introducing an original auxiliary bonding layer on the metal bonding layer of at least one of the two wafers, can achieve initial stable bonding of the two wafers after bonding with the help of the original auxiliary bonding layer, and achieve high-strength covalent bonding between the bonding interfaces with the help of heat treatment, and achieve the reduction of the metal bonding layers of the two wafers to the auxiliary bonding layer sandwiched in the middle, thereby achieving conductive connection between the two wafers.
  • the wafer bonding method has a simple process and strong universality, and can easily achieve high-strength bonding between any two wafers with metal bonding layers.
  • the reducibility of the material on the side of the metal bonding layer in contact with the original auxiliary bonding layer is higher than the reducibility of the single substance corresponding to the positive valence element in the original auxiliary bonding layer. This ensures that the original auxiliary bonding layer in a specific area is smoothly reduced.
  • the original auxiliary bonding layer includes one of metal oxide, metal nitride, silicon oxide containing doped elements, silicon nitride containing doped elements, and silicon oxynitride containing doped elements.
  • These original auxiliary bonding layer materials are relatively easy to prepare, and have good hydrophilicity and insulation properties, which can ensure the close fit of the two wafers after contact, and can be reduced by common metal bonding layers at a relatively low temperature, and their reduction products are all conductive.
  • the thickness of the original auxiliary bonding layer is in the range of 0.5-10 nm. In this case, it will not have an adverse effect on the roughness of the surface to be bonded of the wafer, and it is helpful to reduce the duration of subsequent heat treatment and reduce damage to the wafer function.
  • the temperature of the heat treatment is 100-200° C.
  • the lower heat treatment temperature can ensure that the original auxiliary bonding layer can be restored smoothly, while also reducing the damage to the device functional layer on the wafer, ensuring that the bonded structure can function normally.
  • the metal bonding layer intervals are formed on the first side of the substrate; and before forming the original auxiliary bonding layer, the wafer bonding method also includes: forming an insulating bonding layer between the adjacent metal bonding layers on the two wafers, and the original auxiliary bonding layer also covers the insulating bonding layer; wherein the surface of the insulating bonding layer facing away from the substrate is flush with the surface of the metal bonding layer facing away from the substrate.
  • the initial low-temperature bonding of the two wafers after bonding can be conveniently achieved with the help of the original auxiliary bonding layer, and high-strength covalent bonding between the bonding interfaces can be achieved with the help of heat treatment, and the upper and lower metal bonding layers of the two wafers only reduce the original auxiliary bonding layer sandwiched in the middle in situ, ensuring the longitudinal conductive connection between the corresponding metal bonding layers in the two wafers and the lateral insulation isolation between adjacent metal bonding layers in the same wafer.
  • the surface of the insulating bonding layer facing away from the substrate is flush with the surface of the metal bonding layer facing away from the substrate, which is conducive to the subsequent formation of a flat auxiliary bonding layer to improve the wafer bonding
  • FIG1 is a schematic flow chart of a wafer bonding method provided in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a specific process of a wafer bonding method provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a variation of the wafer bonding method shown in FIG. 2 .
  • FIG. 4 is a schematic diagram of another variant process of the wafer bonding method shown in FIG. 2 .
  • FIG. 5 is a schematic diagram of a specific process of a wafer bonding method provided in another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a variation of the wafer bonding method shown in FIG. 5 .
  • FIG. 7 is another schematic diagram of the process of bonding and heat treating the two wafers in FIG. 5 .
  • FIG. 8 is another schematic diagram of the process of bonding and heat treating the two wafers in FIG. 6 .
  • FIG. 9 is a schematic diagram of another variation of the wafer bonding method shown in FIG. 5 .
  • FIG. 10 is a schematic diagram of a specific process of a wafer bonding method provided in yet another embodiment of the present application.
  • FIG. 11 is a schematic diagram of a variation of the wafer bonding method shown in FIG. 10 .
  • FIG. 12 is a schematic diagram of another variant process of the wafer bonding method shown in FIG. 10 .
  • FIGS 13A to 13H are schematic diagrams of several structures of semiconductor structures provided in embodiments of the present application.
  • An embodiment of the present application provides a wafer bonding method. Please refer to the flow chart of FIG. 1 and the specific process charts of FIG. 2 - FIG. 3 .
  • the wafer bonding method includes the following steps S01 - S04 .
  • each wafer comprising a substrate, and a device function layer is disposed on a first side of at least one of the two substrates.
  • the substrate may be a sapphire substrate, a glass substrate, a silicon substrate, a silicon carbide substrate, a silicon substrate, a germanium substrate, a silicon-on-insulator substrate (SOI substrate), a germanium-on-insulator substrate, or a III-V compound substrate (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, etc.).
  • the crystal orientation of the silicon substrate is not limited, for example, it may be a silicon substrate with a (111) crystal plane index, or a silicon substrate with other crystal plane indexes; in particular, the silicon substrate in the wafer used to make optoelectronic devices may be a silicon substrate with a (111) crystal plane index.
  • Each device functional layer may be a single layer or multiple layers (multilayer means greater than or equal to two layers), and the number of layers or the material of each layer may be selected according to the function of the semiconductor device formed by wafer bonding.
  • the device functional layer includes an epitaxial stack structure formed based on a III-V semiconductor material (such as GaN, GaAs, AlN, AlGaN, InN, etc.), for example, including a buffer layer, an n-type doped layer, an active layer, and a p-type doped layer arranged in layers, and the buffer layer is close to the substrate.
  • the device functional layer including the epitaxial stack structure is particularly suitable for preparing optoelectronic devices.
  • both wafers may include a substrate and a device function disposed on the substrate.
  • each device functional layer fully covers the entire surface area of the first side of the substrate.
  • the two wafers to be bonded can also be one wafer including a substrate, and the other wafer including a substrate and a device functional layer arranged on the substrate (this situation will be introduced in FIG4 below).
  • the metal bonding layer on each substrate can be a single layer of metal or a multi-layer metal stack; each layer of metal can be a metal single substance, or a metal alloy, or a composite layer composed of a metal alloy and a metal single substance.
  • the metal bonding layer is not a copper single substance. In this way, the reduction of the original auxiliary bonding layer below by the metal bonding layer can be ensured more smoothly.
  • the material of the metal bonding layer includes one or more of Ti, Cr, Ni, Ta, Au, In, Sn, Ag, Al, W and alloys of at least two of the above elements, TiN, and TaN.
  • the metal bonding layer can be a Ti layer, a Ta layer, a Cr layer, a Ni layer, a TiCr alloy layer, a NiCrTi alloy layer, a stack of a Ti layer and a Ni layer, etc.
  • the metal bonding layer can be prepared by electroplating, or physical vapor deposition (such as sputtering, electron beam evaporation, thermal evaporation), etc., but is not limited thereto.
  • the thickness of the metal bonding layer can be between a few nanometers and tens of microns, such as in the range of 10nm-10 ⁇ m, and can be specifically 20nm, 30nm, 50nm, 60nm, 80nm, 100nm, 150nm, 200nm, 500nm, 800nm, 1 ⁇ m, 5 ⁇ m or 8 ⁇ m, etc.
  • the first wafer 1a also includes a first metal bonding layer 30a stacked on the side of the second device functional layer 20a away from the first substrate 10a, and the first metal bonding layer 30a is also located on the first side 101a of the first wafer 1a.
  • the second wafer 1b also includes a second metal bonding layer 30b stacked on the side of the first device functional layer 20b away from the second substrate 10b, and the second metal bonding layer 30b is also located on the first side 101b of the second wafer 1b. More specifically, in FIG. 2, the first metal bonding layer 30a fully covers the side surface of the second device functional layer 20a away from the first substrate 10a, and in FIG. 3, the second metal bonding layer 30b fully covers the side surface of the first device functional layer 20b away from the second substrate 10b.
  • the original auxiliary bonding layer can be prepared on both wafers (as shown in FIG. 2), or the original auxiliary bonding layer can be prepared only on one of the wafers (as shown in FIG. 3). Accordingly, after the two wafers are bonded in the following step S04, the total number of original auxiliary bonding layers in the bonded structure can be one or two layers.
  • a first original auxiliary bonding layer 40a is formed on the surface of the side of the first metal bonding layer 30a facing away from the first substrate 10a, which covers the first metal bonding layer 30a.
  • the first original auxiliary bonding layer 40a Since the first metal bonding layer 30a covers the first substrate 10a on the entire surface, the first original auxiliary bonding layer 40a also correspondingly achieves the entire surface coverage of the first substrate 10a; similarly, in the second wafer 1b, a second original auxiliary bonding layer 40b is formed on the side of the second metal bonding layer 30b facing away from the second substrate 10b. In FIG. 3, the original auxiliary bonding layer 40 that can cover the second metal bonding layer 30b is formed only on the second substrate 10b.
  • the thickness of each original auxiliary bonding layer is less than the thickness of the metal bonding layer, for example, the thickness of the original auxiliary bonding layer is 0.1%-10% of the thickness of the metal bonding layer.
  • the thickness of the first original auxiliary bonding layer 40a is less than the thickness of the first metal bonding layer 30a
  • the thickness of the second original auxiliary bonding layer 40b is less than the thickness of the second metal bonding layer 30b.
  • the thickness of the first original auxiliary bonding layer 40a and the second original auxiliary bonding layer 40b can be in the range of 0.5nm-100nm respectively; in some embodiments, the thickness can be in the range of 0.5nm-10nm, for example, 0.6nm, 0.8nm, 1nm, 1.5nm, 2nm, 3nm, 5nm, 8nm, 9.5nm, 10nm, etc.
  • the thinner original auxiliary bonding layer will not have an adverse effect on the roughness of the metal bonding layer on the wafer waiting for bonding, and is conducive to reducing the duration of subsequent heat treatment and reducing damage to the wafer.
  • the thickness of the original auxiliary bonding layer may be greater than or equal to one molecular layer and less than 5 molecular layers, specifically 0.5 nm-3 nm, where "one molecular layer” refers to the thickness of a single layer of molecules of the constituent material of the original auxiliary bonding layer.
  • the material of each original auxiliary bonding layer independently includes one or more of metal oxide, metal nitride, silicon oxide containing doping elements, silicon nitride containing doping elements, and silicon oxynitride containing doping elements. That is, the material of the original auxiliary bonding layer may be the same or different.
  • the metal elements in the metal oxide and the metal nitride include one or more of aluminum Al, tantalum Ta, hafnium Hf, and zirconium Zr.
  • the doping element includes an n-type doping element (such as arsenic As, phosphorus P) and/or a p-type doping element (such as boron B).
  • the doping element can ensure that the product after the silicon oxide, silicon nitride or silicon oxynitride containing the doping element is reduced is conductive, and the reduction product is specifically a silicon element containing the doping element.
  • the original auxiliary bonding layer can be formed by a low-pressure chemical vapor deposition process, a metal organic chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or a laser pulse deposition process.
  • the original auxiliary bonding layer is the above-mentioned insulating material, it generally has good hydrophilicity, and the surface often has hydroxyl dangling bonds, or after being treated with water or an aqueous solution or a hydrophilic organic solvent or plasma bombarded, the surface may have enough hydrophilic hydroxyl groups, which is conducive to achieving sufficient bonding strength between the two wafers at low temperature (including room temperature, which is compared with the temperature of subsequent "heat treatment") with the help of the original auxiliary bonding layer. Hydrogen bonding, which in turn facilitates the conversion of the bonding interface into a higher strength covalent bond in subsequent heat treatment.
  • the above-mentioned original auxiliary bonding layer material can be formed on a variety of metal bonding layers, and the requirements for the type and surface condition of the metal layer to be bonded are not high. Moreover, the material makes the original auxiliary bonding layer have very low requirements for thickness. Usually, a few nm are enough to initially bond the two wafers together. The formation of a thinner original auxiliary bonding layer will not have an adverse effect on the roughness of the bonding surface, and can also ensure that the subsequent heat treatment after the two wafers are bonded is short in duration and low in temperature, reducing damage to the wafer structure.
  • the material of the original auxiliary bonding layer can be selected based on the metal bonding layer, and the principle is that "in the structure obtained after the two wafers are bonded by S04, the reducibility of the material on the side of the metal bonding layer in contact with the original auxiliary bonding layer is higher than the reducibility of the single substance corresponding to the positive-valent element in the original auxiliary bonding layer.” That is, the present application does not mandatory require that the reducibility of the entire metal bonding layer material is higher than the single substance corresponding to the positive-valent element in the original auxiliary bonding layer, but only requires that the part of the metal bonding layer material in contact with the original auxiliary bonding layer meet the requirements.
  • the single substance corresponding to the positive valence element in the original auxiliary bonding layer refers to the single substance corresponding to the metal element in the metal oxide or the metal nitride.
  • the positive valence element specifically refers to the single substance corresponding to the silicon element.
  • the original auxiliary bonding layer is an oxide or nitride of Al.
  • the metal material on the side of the metal bonding layer close to the original auxiliary bonding layer may include at least one of Ti, Cr, and Ni.
  • the original auxiliary bonding layer is an oxide or nitride of tantalum Ta, hafnium Hf, or zirconium Zr.
  • the metal material on the side of the metal bonding layer close to the original auxiliary bonding layer includes at least one of Al, Ti, Cr, and Ni.
  • step S04 bonding the two wafers processed in step S03 so that the metal bonding layers on the two wafers are arranged relative to each other, and heat-treating the two bonded wafers so that the original auxiliary bonding layer sandwiched between the metal bonding layers correspondingly arranged on the two wafers is reduced to a conductive layer.
  • Bonding refers to the contact between the surfaces of the two wafers to be bonded.
  • the bonding refers to the contact between the first original auxiliary bonding layer 40a and the second original auxiliary bonding layer 40b;
  • the bonding refers to the contact between the original auxiliary bonding layer 40 on the second wafer 1b and the first metal bonding layer 30a on the first wafer 1a.
  • the “alignment” here is not limited to “full alignment” (full alignment means that along the thickness direction of the substrate, the side walls of any relatively arranged upper and lower metal bonding layers are flush), and a certain offset is allowed.
  • the offset alignment will be explained below in this application.
  • the “alignment” specifically means that any metal bonding layer on one wafer corresponds one-to-one with a metal bonding layer on the other wafer, and each pair of relatively upper and lower metal bonding layers has a certain overlapping area in their orthographic projections on the original auxiliary bonding layer.
  • hydrophilic treatment of the surfaces to be bonded of the wafers can help the two wafers to form a certain number of hydrogen bonds between the bonding surfaces of the two wafers after bonding, increase the strength of the two wafers after bonding, and be more conducive to the occurrence of reduction reactions during subsequent heat treatment.
  • the hydrophilic treatment of the metal bonding layer is also conducive to the formation of certain hydrophilic groups (such as -OH) on its surface to ensure its close fit with the original auxiliary bonding layer.
  • the hydrophilic treatment can include plasma bombardment (such as oxygen plasma bombardment), or chemical mechanical polishing (CMP), or spraying, soaking, infiltration, etc. with water or hydrophilic reagents, or a combination of the above methods.
  • the hydrophilic agent may be an aqueous solution such as an ammonia solution, a weak acid, or a hydrophilic organic solvent containing a hydroxyl group.
  • water may specifically include spraying or soaking with deionized water, soaking with water vapor, and the like.
  • the two wafers after bonding are heat treated, and the bonding interface of the two wafers can gradually change from hydrogen bonding to covalent bonding, and at the same time, the original auxiliary bonding layer sandwiched between the two relatively arranged metal bonding layers is reduced to a conductive layer, specifically, the metal bonding layer in contact with it is reduced, and the two wafers are electrically connected with the help of the metal bonding layer and the conductive layer between them.
  • the reducibility of the material on the side of the metal bonding layer in contact with the original auxiliary bonding layer is higher than the reducibility of the single substance corresponding to the positive valence element in the original auxiliary bonding layer.
  • the original auxiliary bonding layer is formed on only one wafer as mentioned above, then after bonding, the metal bonding layer on at least one of the two wafers can meet the above-mentioned reducibility requirements.
  • the reducibility of the material on the side of the first metal bonding layer 30a close to the first original auxiliary bonding layer 40a should be higher than the reducibility of the single substance corresponding to the positive-valent element in the first original auxiliary bonding layer 40a
  • the reducibility of the material on the side of the second metal bonding layer 30b close to the second original auxiliary bonding layer 40b should be higher than the reducibility of the single substance corresponding to the positive-valent element in the second original auxiliary bonding layer 40b.
  • the first original auxiliary bonding layer 40a can be reduced to the first conductive layer 402a by the first metal bonding layer 30a
  • the second original auxiliary bonding layer 40b can be reduced to the second conductive layer 402b by the second metal bonding layer 30b.
  • the reducibility of the material on the side of the first metal bonding layer 30a and/or the second metal bonding layer 30b close to the original auxiliary bonding layer 40 should be higher than the reducibility of the single substance corresponding to the positive-valent element in the original auxiliary bonding layer 40. In this way, It can be ensured that after the two wafers in FIG. 3 are bonded, the original auxiliary bonding layer 40 can be reduced by the metal bonding layer on one or both sides in contact with it.
  • the materials of the first original auxiliary bonding layer 40a and the second original auxiliary bonding layer 40b can be the same or different, and the same is preferred.
  • the two are made of the same material, when the two wafers are bonded and heat treated, it can ensure that the covalent bond at the bonding interface is stronger, thereby improving the bonding strength between the first conductive layer 402a and the second conductive layer 402b.
  • the heat treatment can be carried out at a temperature of 100-1000°C, and the time can be 1min-10h.
  • the temperature of the heat treatment is 100-600°C, for example, specifically 100°C, 150°C, 200°C, 220°C, 250°C, 300°C, 350°C, 400°C, 450°C, 500°C, 550°C or 580°C, and the temperature of the heat treatment can further be within the range of 100-200°C.
  • the lower heat treatment temperature can ensure that the reduction of the original auxiliary bonding layer can proceed smoothly, while also reducing the damage to the device functional layer on the wafer, ensuring that the structure after bonding can function normally.
  • the time of the heat treatment can be specifically 5min, 10min, 15min, 20min, 30min, 40min, 1h, 2h, 3h, 5h, 8h, etc.
  • the specific temperature and time of the heat treatment can be regulated according to the material or thickness of the original auxiliary bonding layer.
  • the "bonding" can be performed under pressure, for example, by applying pressure to one or both of the first substrate and the second substrate.
  • the bonding and the heat treatment can be performed simultaneously, for example, in a bonding machine with a heating function, or the "bonding" can be performed in the bonding machine and the “heat treatment” can be performed later in other heating equipment (such as a tube furnace, a rapid annealing furnace, etc.).
  • the embodiment of the present application includes the above-mentioned wafer bonding method of steps S01-S04, by introducing an original auxiliary bonding layer on the metal bonding layer of at least one of the two wafers, and by virtue of the hydrophilicity of the original auxiliary bonding layer, the initial stable bonding of the two wafers after bonding can be achieved, the distance between the wafers can be shortened, and high-strength covalent bonding between the bonding interfaces can be achieved by means of heat treatment, and the metal bonding layers of the two wafers can be reduced in situ to the original auxiliary bonding layer sandwiched in the middle, so as to achieve conductive connection between the two wafers.
  • the above-mentioned wafer bonding method has a simple process, strong universality, and low bonding difficulty, and can achieve convenient and high-strength bonding between any two wafers with metal bonding layers, reducing the excessive dependence on substrate materials, bonding materials, bonding processes, etc. in conventional wafer bonding methods.
  • the original auxiliary bonding layer is introduced on the metal bonding layer of the two wafers, it can be ensured that the bonding surfaces of the two wafers are respectively covered with the same material, reducing the bonding difficulty, and the two wafers can easily achieve preliminary hydrogen bonding after lamination, and better shorten the distance between the wafers, which is more conducive to the reduction reaction during heat treatment, ensuring that the surface state of the resulting conductive layer is good (such as no holes), and there is no gap between the metal bonding layer, etc.
  • the two wafers can still be stably bonded together, and the thinner deposition of the film layer will not have an adverse effect on the roughness of the surface to be bonded of the wafer and affect the bonding process, which can save the flattening treatment of the surface to be bonded, reduce the complexity of the bonding process, and reduce the damage to the wafer structure/function during the heat treatment process.
  • step S05 is further included: removing one of the two substrates to obtain the semiconductor structure 100.
  • the second substrate 10b is removed as an example.
  • the removal of the substrate can be achieved by mechanical grinding, CMP, wet etching, dry etching, etc., and the wafer substrate on one side is retained for subsequent wafer device processing.
  • FIG 4 is a schematic diagram of another variant process of the wafer bonding method shown in Figure 2.
  • the first wafer 1a only includes the first substrate 10a, and there is no second device functional layer 20a on the first side 101a of the first substrate 10a, and the second wafer 1b still includes the second substrate 10b and the first device functional layer 20b arranged on its first side 101b.
  • the first metal bonding layer 30a is directly in contact with the first side surface of the first substrate 10a, and the second metal bonding layer 30b is arranged on the side of the first device functional layer 20b away from the second substrate 10b. After the bonding process and heat treatment, the second substrate 10b on the second wafer 1b is removed.
  • FIG5 is a schematic diagram of a specific process of a wafer bonding method provided by another embodiment of the present application.
  • the main difference between FIG5 and the method shown in FIG2 is that the metal bonding layers are formed on the substrate at intervals, and an insulating bonding layer is introduced between the metal bonding layers.
  • the wafer bonding method shown in FIG5 includes:
  • first wafer 1a and a second wafer 1b
  • first wafer 1a includes a first substrate 10a and a second device functional layer 20a disposed on a first side 101a of the first substrate 10a
  • second wafer 1b includes a second substrate 10b and a first device functional layer 20b disposed on a first side 101b of the second substrate 10b.
  • the second device functional layer 20a fully covers the first side 101a of the first substrate 10a
  • the first device functional layer 20b fully covers the first side 101b of the second substrate 10b.
  • a plurality of first layers are formed on the surface of the second device functional layer 20a facing away from the first substrate 10a.
  • Metal bonding layer 30a two adjacent first metal bonding layers 30a are sandwiched with a first insulating bonding layer 31a, similarly, a plurality of second metal bonding layers 30b are formed on the surface of the first device functional layer 20b facing away from the second substrate 10b, and a second insulating bonding layer 31b is sandwiched between two adjacent second metal bonding layers 30b.
  • the surface of the first insulating bonding layer 31a facing away from the first substrate 10a is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10a
  • the surface of the second insulating bonding layer 31b facing away from the second substrate 10b is flush with the surface of the second metal bonding layer 30b facing away from the second substrate 10b. That is, the first insulating bonding layer 31a has the same thickness as the first metal bonding layer 30a
  • the second insulating bonding layer 31b has the same thickness as the second metal bonding layer 30b.
  • the thickness of the first insulating bonding layer 31a and the second insulating bonding layer 31b can be between a few nanometers and tens of micrometers, for example, in the range of 10nm-10 ⁇ m.
  • the material of each insulating bonding layer can be the same as or different from the original auxiliary bonding layer below, and each insulating bonding layer includes but is not limited to various dielectric materials such as silicon oxide, silicon nitride, titanium oxide, and aluminum oxide.
  • hybrid bonding is generally performed by directly bonding metal bonding layers and directly bonding insulating bonding layers, but since the surface treatment and bonding conditions of different bonding materials have their own strict requirements, this makes hybrid bonding more difficult and increases the failure rate. Therefore, the embodiments of the present application introduce the following original auxiliary bonding layer and related processing.
  • a first original auxiliary bonding layer 40a covering the entire surface of the first metal bonding layer 30a and the first insulating bonding layer 31a is formed on the first side 101a of the first wafer
  • a second original auxiliary bonding layer 40b covering the entire surface of the second metal bonding layer 30b and the second insulating bonding layer 31b is formed on the first side 101b of the second wafer.
  • the thickness, material, function, etc. of each original auxiliary bonding layer can be selected as described in the previous description of this application.
  • the above-mentioned original auxiliary bonding layer is introduced to ensure that the bonding materials in different regions of the wafer formed with the original auxiliary bonding layer are covered by the same material, thereby reducing the bonding difficulty of the two wafers.
  • the original auxiliary bonding layer is introduced on the substrates of both wafers, it can be ensured that the bonding materials in different regions of the two wafers are covered by the same material, and the hybrid bonding of the two wafers becomes the bonding of dielectric materials, which reduces the requirements for the metal bonding layer and the insulating bonding layer materials, surface treatment, etc., and can easily achieve high-quality hybrid bonding under simple bonding conditions.
  • the surface of the original auxiliary bonding layer facing away from the wafer substrate is flat.
  • the surface of the first original auxiliary bonding layer 40a facing away from the first substrate 10a is flat, and the surface of the second original auxiliary bonding layer 40b facing away from the second substrate 10b is flat. This can more conveniently complete the bonding of the two wafers, and the bonding efficiency is higher.
  • each first metal bonding layer 30a has a second metal bonding layer 30b disposed opposite thereto
  • each first insulating bonding layer 31a has a second insulating bonding layer 31b disposed opposite thereto.
  • the bonding interface of the two wafers is converted into a covalent bond with higher bonding strength, and the first original auxiliary bonding layer 40a and the second original auxiliary bonding layer 40b sandwiched between the first metal bonding layer 30a and the second metal bonding layer 30b are reduced.
  • the first original auxiliary bonding layer 40a is reduced to the first conductive layer 402a by the first metal bonding layer 30a in contact with it
  • the second original auxiliary bonding layer 40b is reduced to the second conductive layer 402b by the second metal bonding layer 30b in contact with it
  • the first original auxiliary bonding layer and the second original auxiliary bonding layer sandwiched between the first insulating bonding layer 31a and the second insulating bonding layer 31b remain in their original state, and are respectively referred to by the numbers 401a and 401b for easy distinction.
  • a first auxiliary bonding layer 401a is provided between adjacent first conductive layers 402a, and a second auxiliary bonding layer 401b is provided between adjacent second conductive layers 402b.
  • the surface to be bonded may be subjected to a hydrophilic treatment; the process conditions of the hydrophilic treatment, bonding, heat treatment, etc. may refer to the above description.
  • a step of "removing one of the two substrates" is also included.
  • the wafer bonding method of the embodiment of the present application includes steps S501-S504, by introducing an original auxiliary bonding layer covering the metal bonding layer and the insulating bonding layer on at least one of the two wafers, the initial low-temperature bonding of the two wafers after bonding can be conveniently achieved with the help of the original auxiliary bonding layer, and high-strength covalent bonding between the bonding interfaces can be achieved with the help of heat treatment, and the upper and lower metal bonding layers of the two wafers are only bonded to the original auxiliary bonding layer sandwiched in the middle.
  • the in-situ restoration of the layers ensures the longitudinal conductive connection between the corresponding metal bonding layers in the two wafers. At the same time, the current insulation isolation between adjacent metal bonding layers in the same wafer is guaranteed by the non-conductive auxiliary bonding layer that remains original between the upper and lower insulating bonding layers.
  • Fig. 6 is a schematic diagram of a variant process of the wafer bonding method shown in Fig. 5.
  • the main difference between Fig. 6 and the method shown in Fig. 5 is that in Fig. 6, only the original auxiliary bonding layer 40 is formed on the second wafer 1b.
  • the beneficial effects of the method shown in Fig. 6 are similar to those of Fig. 5 and will not be repeated here.
  • the reducibility of the material of the second metal bonding layer 30b and/or the first metal bonding layer 30a close to the original auxiliary bonding layer 40 should be higher than the reducibility of the single substance corresponding to the positive valence element in the original auxiliary bonding layer 40.
  • the part of the original auxiliary bonding layer 40 sandwiched between the first metal bonding layer 30a and the second metal bonding layer 30b can be reduced to a conductive layer 402, wherein the original auxiliary bonding layer 40 can be specifically reduced by the first metal bonding layer 30a, or reduced by the second metal bonding layer 30b, or reduced by both the first metal bonding layer 30a and the second metal bonding layer 30b, and the specific reduction situation can be determined according to the specific materials of the three.
  • FIG. 5 and FIG. 6 illustrate the situation where the metal bonding layers on the two wafers are completely aligned during bonding, but it is understandable that the alignment of the metal bonding layers on the two wafers may allow a certain offset, as shown in FIG. 7 and FIG. 8 for details.
  • FIG7 is another schematic diagram of the process of bonding and heat treatment of the two wafers in FIG5.
  • the first metal bonding layer 30a and the second metal bonding layer 30b are arranged one by one relative to each other, they are not completely aligned and a certain offset occurs.
  • the first insulating bonding layer 31a and the second insulating bonding layer 31b are also arranged one by one relative to each other but are not completely aligned.
  • the first original auxiliary bonding layer 40a in contact with the first metal bonding layer 30a is reduced to the first conductive layer 402a by the first metal bonding layer 30a
  • the second original auxiliary bonding layer 40b in contact with the second metal bonding layer 30b is reduced to the second conductive layer 402b by the second metal bonding layer 30b
  • the distribution position of the first conductive layer 402a is basically consistent with the first metal bonding layer 30a
  • the distribution position of the second conductive layer 402b is basically consistent with the second metal bonding layer 30b.
  • Fig. 8 is another schematic diagram of the process of bonding and heat treatment of the two wafers in Fig. 6.
  • Fig. 8 is another schematic diagram of the process of bonding and heat treatment of the two wafers in Fig. 6.
  • the reducibility of the materials of the second metal bonding layer 30b and the first metal bonding layer 30a close to the original auxiliary bonding layer 40 is higher than the reducibility of the single substance corresponding to the positive valence element in the original auxiliary bonding layer 40
  • the first metal bonding layer 30a and the second metal bonding layer 30b are arranged one by one but not completely aligned, then the original auxiliary bonding layer 40 sandwiched between the first metal bonding layer 30a and the second metal bonding layer 30b and in contact with the two is reduced to a conductive layer 402 by the two, that is, the resulting conductive layer 402 corresponds to the union of the auxiliary bonding layers in contact with the first metal bonding layer 30a/the second metal bonding layer 30b.
  • FIG9 is a schematic diagram of another variant process of the wafer bonding method shown in FIG5.
  • the difference between FIG9 and FIG5 is that only one of the two wafers used has a device functional layer, and in FIG9 specifically, the second wafer 1b has a device functional layer.
  • the first wafer 1a Before forming the auxiliary bonding layer, the first wafer 1a only includes a first substrate 10a and a plurality of first metal bonding layers 30a formed on its first side 101a at intervals, and two adjacent first metal bonding layers 30a are sandwiched with a first insulating bonding layer 31a. After the two wafers are bonded and heat treated, the second substrate 10b in the second wafer 1b with the device functional layer is removed.
  • FIG10 is a schematic diagram of a specific process of a wafer bonding method provided by another embodiment of the present application.
  • the main difference between FIG10 and the method shown in FIG2 is that the metal bonding layer is formed on the substrate at intervals, and an insulating bonding layer is introduced between the metal bonding layers.
  • the main difference between FIG10 and FIG5 in which the metal bonding layer is formed on the substrate at intervals is that the distribution of the device functional layer on the substrate is different.
  • the wafer bonding method shown in FIG10 may specifically include:
  • step 1 as shown in (A) of FIG10 , two wafers to be bonded are provided - a first wafer 1a and a second wafer 1b, wherein the first wafer 1a includes a first substrate 10a and a plurality of second device functional layers 20a spaced apart on a first side 101a of the first substrate 10a, and the second wafer 1b includes a second substrate 10b and a plurality of first device functional layers 20b spaced apart on a first side 101b of the second substrate 10b.
  • Step 2 forming a plurality of metal bonding layers spaced apart on the two wafers, wherein the metal bonding layer is located on the first side of the substrate, and an insulating bonding layer is formed between two adjacent metal bonding layers.
  • the surface of the insulating bonding layer facing away from the substrate is flush with the surface of the metal bonding layer facing away from the substrate. This facilitates the subsequent formation of an auxiliary bonding layer with a flat surface to improve the bonding efficiency of the wafers.
  • a first metal bonding layer 30a that can cover the third surface 201a is formed on the side surface of each second device functional layer 20a that faces away from the first substrate 10a (which can be referred to as the third surface 201a), and a second metal bonding layer 30b that can cover the third surface 201b is formed on the side surface of each first device functional layer 20b that faces away from the second substrate 10b (which can be referred to as the third surface 201b). Since each device functional layer is distributed at intervals on the substrate where it is located, the metal bonding layers arranged on each device functional layer are also distributed at intervals accordingly.
  • a first insulating bonding layer 31a is provided between the stacked structure formed by the second device functional layer 20a and the first metal bonding layer 30a, and the first insulating bonding layer 31a can contact the first substrate 10a, and its thickness is equal to the sum of the thicknesses of the second device functional layer 20a and the first metal bonding layer 30a, so as to ensure that the surface of the first insulating bonding layer 31a facing away from the first substrate 10a is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10a.
  • a second insulating bonding layer 31b is provided between the stacked structure formed by the first device functional layer 20b and the second metal bonding layer 30b.
  • the second insulating bonding layer 31b can be in contact with the second substrate 10b, and its thickness is equal to the sum of the thicknesses of the first device functional layer 20b and the second metal bonding layer 30b to ensure that the surface of the second insulating bonding layer 31b facing away from the second substrate 10b is flush with the surface of the second metal bonding layer 30b facing away from the second substrate 10b.
  • Step 3 forming an original auxiliary bonding layer covering the metal bonding layer and the insulating bonding layer on at least one of the two wafers with the metal bonding layer and the insulating bonding layer; wherein the original auxiliary bonding layer is an insulating compound.
  • a first original auxiliary bonding layer 40a covering the first metal bonding layer 30a and the first insulating bonding layer 31a is formed on the first side 101a of the first wafer
  • a second original auxiliary bonding layer 40b covering the second metal bonding layer 30b and the second insulating bonding layer 31b is formed on the first side 101b of the second wafer.
  • each auxiliary bonding layer can be selected with reference to the description of the previous text of this application. Similar to FIG. 5 , the surface of the first original auxiliary bonding layer 40a facing away from the first substrate 10a is flat, and the surface of the second original auxiliary bonding layer 40b facing away from the second substrate 10b is flat. In this way, the bonding of the two wafers can be completed more conveniently, and the bonding efficiency is higher.
  • Step 4 as shown in (D) of FIG. 10, the two wafers processed in the above steps 1-3 are bonded together so that the metal bonding layers on the two wafers are arranged and aligned one by one, and the corresponding insulating bonding layers are also arranged and aligned one by one, and the two bonded wafers are heat-treated so that the original auxiliary bonding layer sandwiched between the two corresponding metal bonding layers in the two wafers is reduced to a conductive layer, as shown in (E) of FIG. 10. Specifically, during the heat treatment process, the part of the original auxiliary bonding layer in contact with the metal bonding layer is reduced, while the auxiliary bonding layer in other areas remains in its original state.
  • the above-mentioned wafer bonding method shown in Figure 10 introduces an original auxiliary bonding layer covering the metal bonding layer and the insulating bonding layer on at least one of the two wafers.
  • the original auxiliary bonding layer With the help of the original auxiliary bonding layer, high-quality bonding between the corresponding metal bonding layers and the corresponding insulating bonding layers in the two wafers can be easily achieved.
  • the conductive connection of the upper and lower device functional layers between the two wafers in the longitudinal direction and the current insulation isolation between the discrete device functional layers in the same wafer can be achieved.
  • FIG11 is a schematic diagram of a variant process of the wafer bonding method shown in FIG10.
  • the main difference between FIG11 and the method shown in FIG10 is that in FIG11, only one original auxiliary bonding layer 40 is formed on the second wafer 1b. After the two wafers are bonded and heat treated, the conductive layer 402 sandwiched between the upper and lower metal bonding layers along the thickness direction of the substrate is also a layer.
  • Fig. 12 is a schematic diagram of another variant process of the wafer bonding method shown in Fig. 10.
  • the difference between Fig. 12 and Fig. 10 is that only one of the two wafers used has a device function layer, and in Fig. 12, specifically, the second wafer 1b has a plurality of first device function layers 20b arranged at intervals.
  • the first wafer 1a Before forming the original auxiliary bonding layer, the first wafer 1a only includes the first substrate 10a and a plurality of first metal bonding layers 30a formed on the first side 101a thereof at intervals, and a first insulating bonding layer 31a is sandwiched between two adjacent first metal bonding layers 30a.
  • the thickness of the first insulating bonding layer 31a is the same as that of the first metal bonding layer 30a, so that the surfaces of the two facing away from the first substrate 10a can be flush.
  • the second wafer 1b includes a second substrate 10b and a plurality of first device functional layers 20b spaced apart on a first side 101b of the second substrate 10b, a second metal bonding layer 30b that can cover the first device functional layer 20b is formed on a surface of each first device functional layer 20b facing away from the second substrate 10b, a second insulating bonding layer 31b is provided between the stacked structure formed by the first device functional layer 20b and the second metal bonding layer 30b, the thickness of the second insulating bonding layer 31b is equal to the sum of the thickness of the first device functional layer 20b and the second metal bonding layer 30b, so as to ensure that the surface of the second insulating bonding layer 31b facing away from the second substrate 10b is flush with the surface of the second metal bonding layer 30b facing away from the second substrate 10b.
  • the wafer bonding method described above in the embodiment of the present application can be suitable for wafer bonding in semiconductor manufacturing processes such as power electronic devices, radio frequency electronic devices, LED (light emitting diode), MEMS (Micro Electro Mechanical System), etc.
  • the semiconductor structure provided by the embodiment of the present application is described below.
  • the semiconductor structure can be prepared by the wafer bonding method described in the embodiment of the present application.
  • a semiconductor structure is provided.
  • the semiconductor structure contains both a metal bonding layer and an insulating bonding layer. Therefore, the semiconductor structure in this case may also be referred to as a "hybrid bonded semiconductor structure".
  • FIG. 13A and FIG. 13B are schematic diagrams of the structure of a semiconductor structure provided in some embodiments of the present application. Please refer to FIG. 13A and FIG. 13B together, the semiconductor structure 100 specifically includes:
  • a first substrate 10a and a plurality of first metal bonding layers 30a wherein the plurality of first metal bonding layers 30a are arranged at intervals on a first side 101a of the first substrate 10a, and a first insulating bonding layer 31a is provided between two adjacent first metal bonding layers 30a;
  • the first device function layer 20b and a plurality of second metal bonding layers 30b wherein the second metal bonding layers 30b are arranged on the first device function layer 20b toward the On one side of the first substrate 10a, a plurality of first metal bonding layers 30a and a plurality of second metal bonding layers 30b are arranged opposite to each other one by one, and along the thickness direction perpendicular to the first substrate 10a, a second insulating bonding layer 31b is arranged between two adjacent second metal bonding layers 30b (correspondingly, each second insulating bonding layer 31b is also arranged opposite to the first insulating bonding layer 31a one by one).
  • a conductive layer 402 is also arranged between each first metal bonding layer 30a and the second metal bonding layer 30b opposite thereto, and an auxiliary bonding layer 401 is arranged between adjacent conductive layers 402 along the thickness direction perpendicular to the first substrate 10a (z direction in the figure), and the material of the auxiliary bonding layer 401 is an insulating compound.
  • the conductive layer 402 contains the same element as the positively valenced element in the auxiliary bonding layer 401, and along the thickness direction of the first substrate 10a, the reducibility of the material on the side of the first metal bonding layer 30a and/or the second metal bonding layer 30b close to the conductive layer 402 is higher than the reducibility of the material of the conductive layer 402. This shows that the conductive layer 402 is obtained by reducing the same material as the auxiliary bonding layer 401 through the first metal bonding layer 30a and/or the second metal bonding layer 30b.
  • the conductive layer 402 and the auxiliary bonding layer 401 arranged in the same plane as the conductive layer 402 will establish a bonding bridge between the structures located on their upper and lower sides, ensuring that the overall structure of the semiconductor structure 100 is relatively stable, and realizing high-strength bonding between the upper and lower metal bonding layers and between the upper and lower insulating bonding layers without affecting the longitudinal conductive connection between the upper and lower metal bonding layers, and the lateral electrical insulation between adjacent metal bonding layers in the thickness direction perpendicular to the first substrate.
  • the interface of the first metal bonding layer 30a and/or the second metal bonding layer 30b near the conductive layer 402 contains the same element as the negative valence element in the auxiliary bonding layer 401.
  • This can reflect that the first metal bonding layer 30a and/or the second metal bonding layer 30b has captured the negative valence element in the material of the same material as the auxiliary bonding layer 401.
  • the conductive layer 402 is the same material as the auxiliary bonding layer 401 and is chemically reduced by the first metal bonding layer 30a and/or the second metal bonding layer 30b.
  • this can also explain that there may be a covalent bond between the conductive layer and the interface of the upper and lower metal bonding layers, and the bonding strength is higher.
  • the surface of the conductive layer 402 in contact with the first metal bonding layer 30a or the second metal bonding layer 30b is flat and undamaged.
  • the formation of the conductive layer 402 is the result of an in-situ chemical reaction, and the surface state of the film layer is not significantly damaged compared to the surface state of the unreduced auxiliary bonding layer 401, which is conducive to ensuring a good conductive connection between the conductive layer 402 and the first metal bonding layer 30a and the second metal bonding layer 30b, and ensuring that the structure of the semiconductor structure 100 is relatively stable.
  • an auxiliary bonding layer 401 is sandwiched between adjacent conductive layers 402”, that is, along the thickness direction of the first substrate 10a, an auxiliary bonding layer 401 is sandwiched between each first insulating bonding layer 31a and a second insulating bonding layer 31b.
  • the conductive layer 402 and the auxiliary bonding layer 401 have the same thickness and are arranged in the same plane.
  • the semiconductor structure 100 shown in FIG13A can be prepared by a method similar to that shown in FIG9 (the difference is that the dielectric auxiliary layer is formed only on one wafer).
  • the first device functional layer 20b is a complete film layer, and a plurality of second metal bonding layers 30b are arranged at intervals on the side of the first device functional layer 20b facing the first substrate 10a.
  • the first device functional layer 20b covers the side surface of the plurality of second metal bonding layers 30b facing away from the first substrate 10a and the side surface of the plurality of second insulating bonding layers 31b facing away from the first substrate 10a.
  • each second metal bonding layer 30b is provided with (specifically covered with) a first device functional layer 20b on the side facing away from the first substrate 10a. That is, there are multiple first device functional layers 20b, and their number is consistent with the number of second metal bonding layers 30b; the orthographic projections of the multiple first device functional layers 20b on the first substrate 10a are distributed at intervals.
  • the first device functional layer in FIG13B can be regarded as a non-continuous film layer, which can be regarded as including multiple first device functional sublayers arranged at intervals, and each second metal bonding layer 30b is provided with a first device functional sublayer on the side facing away from the first substrate 10a, which is no longer individually numbered here.
  • the surface of the first insulating bonding layer 31a facing away from the first substrate 10a is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10a; the surface of the second insulating bonding layer 31b facing the first substrate 10a is flush with the surface of the second metal bonding layer 30b facing the first substrate 10a.
  • the surfaces of the conductive layer 402 and the auxiliary bonding layer 401 facing away from or toward the first substrate 10a are flat, which is conducive to ensuring the smooth preparation and maintaining good stability of the above-mentioned semiconductor structure.
  • the thickness of the first insulating bonding layer 31a is the same as that of the first metal bonding layer 30a, and the thickness of the second insulating bonding layer 31b is the same as that of the second metal bonding layer 30b; in FIG. 13B , the thickness of the first insulating bonding layer 31a is the same as that of the first metal bonding layer 30a, but the thickness of the second insulating bonding layer 31b is equal to the sum of the thickness of the second metal bonding layer 30b and the first device functional layer 20b.
  • the auxiliary bonding layer 401 can be one layer (as shown in FIG. 13A and FIG. 13B) or two layers; the number of layers of the conductive layer 402 is the same as the number of layers of the auxiliary bonding layer 401.
  • the auxiliary bonding layer 401 and the conductive layer 402 are one layer, and the thickness of the auxiliary bonding layer 401 and the conductive layer 402 can be in the range of 0.5nm-100nm, for example, preferably in the range of 0.5nm-10nm, and the details can be referred to the relevant description of the single-layer initial auxiliary bonding layer in the previous text.
  • the material, thickness, etc. of the first metal bonding layer 30a and the second metal bonding layer 30b can also refer to the previous description.
  • the material of the auxiliary bonding layer 401 includes one or more of metal oxide, metal nitride, silicon oxide containing doped elements, silicon nitride containing doped elements, and silicon oxynitride containing doped elements.
  • the metal element includes one or more of aluminum Al, tantalum Ta, hafnium Hf, and zirconium Zr.
  • the material of the conductive layer 402 includes silicon or other metal materials containing doped elements, wherein the reducibility of the material on the side of the first metal bonding layer 30a and/or the second metal bonding layer 30b close to the conductive layer 402 is higher than the reducibility of the other metal materials.
  • the other metal material is a single substance corresponding to the metal element in the metal oxide or metal nitride.
  • the other metal material includes one or more of aluminum Al, tantalum Ta, hafnium Hf, and zirconium Zr.
  • the conductive layer 402 contains the same element as the positively valenced element in the auxiliary bonding layer 401
  • the conductive layer 402 is the other metal material.
  • the conductive layer 402 is a silicon single substance containing doped elements.
  • the auxiliary bonding layer 401 is an oxide or nitride of aluminum, and the material of the first metal bonding layer 30a and/or the second metal bonding layer 30b on the side close to the conductive layer 402 includes at least one of Ti, Cr, and Ni.
  • the auxiliary bonding layer 401 is an oxide or nitride of tantalum, hafnium, or zirconium, and the material of the first metal bonding layer 30a and/or the second metal bonding layer 30b on the side close to the conductive layer 402 includes at least one of Al, Ti, Cr, and Ni.
  • FIG13C is a schematic diagram of another semiconductor structure when the auxiliary bonding layer 401 in FIG13A is two layers
  • FIG13D is a schematic diagram of another semiconductor structure when the auxiliary bonding layer 401 in FIG13B is two layers.
  • the semiconductor structure shown in FIG13C can be prepared by the method shown in FIG9 above
  • the semiconductor structure shown in FIG13D can be prepared by the method shown in FIG12 above.
  • the auxiliary bonding layer 401 is two layers, specifically including a first auxiliary bonding layer 401a and a second auxiliary bonding layer 401b which are stacked, and the first auxiliary bonding layer 401a is close to the first insulating bonding layer 31a;
  • the conductive layer 402 includes a first conductive layer 402a and a second conductive layer 402b which are stacked, and the first conductive layer 402a is close to the first metal bonding layer 30a.
  • the first conductive layer 402a is obtained by reducing the first metal bonding layer 30a with the same material as the first auxiliary bonding layer 401a
  • the second conductive layer 402b is obtained by reducing the second metal bonding layer 30b with the same material as the second auxiliary bonding layer 401b.
  • the first conductive layer 402a contains the same element as the positively valent element in the first auxiliary bonding layer 401a, and the reducing property of the material on the side of the first metal bonding layer 30a close to the first conductive layer 402a is higher than the reducing property of the material of the first conductive layer 402a;
  • the second conductive layer 402b contains the same element as the positively valent element in the second auxiliary bonding layer 401b, and the reducing property of the material on the side of the second metal bonding layer 30b close to the second conductive layer 402b is higher than the reducing property of the material of the second conductive layer 402b.
  • the bonding interface is the same material, which can better achieve covalent bonding, improve the bonding strength, and the structural stability of the semiconductor structure 100 is higher. It can be understood that if the auxiliary bonding layer 401 is two layers, the thickness of the auxiliary bonding layer 401 or the conductive layer 402 can be in the range of 1nm-200nm, preferably in the range of 1nm-20nm.
  • the semiconductor structure 100 further includes a second device functional layer 20a, which is located between the first substrate 10a and the first metal bonding layer 30a, and is arranged corresponding to the first device functional layer 20b. Accordingly, the second device functional layer 20a is located on the side of the first substrate 10a facing the first device functional layer 20b (i.e., located on the first side 101a of the first substrate 10a), the plurality of first metal bonding layers 30a are arranged at intervals, and the first metal bonding layer 30a is arranged on the side of the second device functional layer 20a away from the first substrate 10a.
  • the semiconductor structure shown in FIG13E can be prepared by the method shown in FIG5 (the second substrate 10b is removed on the basis of FIG5), and the semiconductor structure shown in FIG13F can be prepared by the method shown in FIG6 (the second substrate 10b is removed on the basis of FIG6).
  • the difference between FIG13F and FIG13E is that the number of layers of the auxiliary bonding layer 401 and the conductive layer 402 is different.
  • the second device functional layer 20a is a complete film layer, which completely covers the first side 101a of the first substrate 10a, and a plurality of first metal bonding layers 30a are arranged at intervals on the surface of the second device functional layer 20a facing away from the first substrate 10a. Since a first insulating bonding layer 31a is arranged between two adjacent first metal bonding layers 30a, the plurality of first insulating bonding layers 31a are also arranged at intervals on the side of the second device functional layer 20a facing away from the first substrate 10a.
  • the first device functional layer 20b is arranged opposite to the second device functional layer 20a, and similarly, a plurality of second metal bonding layers 30b are also arranged at intervals on the surface of the first device functional layer 20b facing the first substrate 10a, and a second insulating bonding layer 31b is sandwiched between two adjacent second metal bonding layers 30b.
  • a first auxiliary bonding layer 401a, the second auxiliary bonding layer 401b, the first conductive layer 402a, the second conductive layer 402b, etc. please refer to the description of Figures 13C and 13D above in this application.
  • the semiconductor structure shown in FIG13G can be prepared by the method shown in FIG10 (the second substrate 10b is removed on the basis of FIG10), and the semiconductor structure shown in FIG13H can be prepared by the method shown in FIG11 (the second substrate 10b is removed on the basis of FIG11).
  • the difference between FIG13G and FIG13H is that the number of layers of the auxiliary bonding layer 401 and the conductive layer 402 is different.
  • a plurality of second device functional layers 20a are spaced apart on the first side 101a of the first substrate 10a, and a first metal bonding layer 30a is covered on the surface of each second device functional layer 20a facing away from the first substrate 10a. In this way, the plurality of first metal bonding layers 30a are spaced apart on the first side 101a of the first substrate 10a.
  • the second device functional layer 20a and the first metal bonding layer 30a form a stacked structure, and a first insulating bonding layer 31a is provided between two adjacent stacked structures, and the thickness of the first insulating bonding layer 31a is equal to the sum of the thickness of the second device functional layer 20a and the first metal bonding layer 30a, so as to ensure that the surface of the first insulating bonding layer 31a facing away from the first substrate 10a It is flush with the surface of the first metal bonding layer 30a facing away from the first substrate 10a, thereby facilitating the smooth preparation of the above-mentioned semiconductor structure and maintaining good stability.
  • a plurality of second metal bonding layers 30b are arranged opposite to a plurality of first metal bonding layers 30a, and a plurality of second insulating bonding layers 31b are arranged opposite to a plurality of first insulating bonding layers 31a.
  • each second metal bonding layer 30b is covered with a first device functional layer 20b on one side away from the first substrate 10a, and the first device functional layer 20b and the second metal bonding layer 30b form another stacked structure, and a second insulating bonding layer 31b is sandwiched between two adjacent stacked structures, and the thickness of the second insulating bonding layer 31b is equal to the sum of the thickness of the first device functional layer 20b and the second metal bonding layer 30b, so as to ensure that the surface of the second insulating bonding layer 31b facing the first substrate 10a is flush with the surface of the second metal bonding layer 30b facing the first substrate 10a, so as to facilitate the smooth preparation of the above-mentioned semiconductor structure and maintain good stability.
  • the semiconductor structure shown in FIG. 13E to FIG. 13H contains two device functional layers at the same time, which can realize the stable integration of device functional layers with different functions in one semiconductor structure.
  • each device functional layer in the semiconductor structure 100 of Figures 13A to 13H above may be one or more layers.
  • each device functional layer may be an epitaxial stacked structure formed based on a III-V semiconductor material (such as GaN, GaAs, AlN, AlGaN, InN, etc.).
  • the second device functional layer 20a may include a first buffer layer, a first n-type doped layer, a first active layer, and a first p-type doped layer arranged in a stacked manner, and the first buffer layer is close to the first substrate 10a;
  • the first device functional layer 20b includes a second buffer layer, a second n-type doped layer, a second active layer, and a second p-type doped layer arranged in a stacked manner, and the second buffer layer is far away from the first substrate.
  • a semiconductor structure is particularly suitable for preparing optoelectronic devices, such as inorganic electroluminescent devices, or photoelectric detection devices, etc.
  • each first metal bonding layer 30a and the second metal bonding layer 30b may also be incompletely aligned, for example, a certain alignment offset may occur, but the good structural stability of the semiconductor structure can still be guaranteed.
  • the present application also provides a semiconductor device, including the semiconductor structure provided in the present application, or including a semiconductor structure obtained by the wafer bonding method in the present application.
  • the semiconductor device has high structural stability, can stably perform its functions, and has strong market competitiveness.
  • the semiconductor structure of the embodiment of the present application can be directly used as a part of the semiconductor device, or it can be peeled off and applied to the semiconductor device.
  • the semiconductor device includes but is not limited to optoelectronic devices, or power devices (i.e., power electronic devices) or radio frequency devices, etc.
  • the optoelectronic device can be an electroluminescent device, such as a light emitting diode (Light Emitting Diode, LED) or a laser diode (Laser diode, LD), specifically a nitride-based light emitting diode, a nitride-based quantum well laser diode.
  • the optoelectronic device can also be a photoelectric detection device, such as an infrared detector, an ultraviolet detector, etc.
  • the power device and the radio frequency device can be a transistor, specifically a field effect transistor.
  • An embodiment of the present application further provides an electronic device, which includes the above-mentioned semiconductor device of the embodiment of the present application.
  • the electronic device can be various consumer electronic products, such as mobile phones, tablet computers, laptops, mobile power supplies, portable devices, and can also be other wearable or portable electronic devices, televisions, DVD players, video recorders, camcorders, radios, radio recorders, combination audio systems, record players, laser record players, home office equipment, home electronic health care equipment, and can also be transportation vehicles such as cars, or energy storage devices, etc.
  • At least one means one or more
  • plural means two or more.
  • At least one of the following” or similar expressions refers to any combination of these items, including any combination of single or plural items.
  • at least one of a, b, or c or “at least one of a, b, and c” can all mean: a, b, c, a-b (i.e. a and b), a-c, b-c, or a-b-c, where a, b, c can be single or multiple, respectively.
  • the size of the serial numbers of the above-mentioned processes does not mean the order of execution, some or all of the steps can be executed in parallel or sequentially, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

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Abstract

本申请实施例提供了一种半导体结构、半导体器件、电子设备及晶圆键合方法，晶圆键合方法包括：提供待键合的两个晶圆，每个晶圆包括衬底，两个衬底中至少一者的第一侧设有器件功能层；在两个晶圆上分别形成金属键合层，金属键合层设置在衬底的第一侧；在带金属键合层的两个晶圆中的至少一者上形成覆盖金属键合层的原始辅助键合层，得到处理后的两个晶圆；其中，原始辅助键合层为绝缘化合物；将处理后的两个晶圆进行贴合以使两晶圆上的金属键合层相对设置，并进行热处理，以使夹在两晶圆中对应设置的金属键合层之间的原始辅助键合层被还原为导电层。该晶圆键合方法的工艺简单、普适性强，能便捷实现具有任意金属键合层的两晶圆之间的高强度键合。

Description

半导体结构、半导体器件、电子设备及晶圆键合方法
本申请要求于2022年11月23日提交至中国专利局、申请号为202211474673.1、申请名称为“半导体结构、半导体器件、电子设备及晶圆键合方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体制造技术领域，具体涉及一种半导体结构、半导体器件、电子设备及晶圆键合方法。
背景技术
晶圆键合技术是半导体制造工艺中的一种关键技术，它可以将两片不同功能的晶圆接合在一起，基于该堆叠思路，可获得具有更高集成度、更多功能、更小尺寸的半导体器件。传统晶圆键合技术的类型一般包括金属-金属直接键合技术(如Cu-Cu键合、Au-Sn键合等)，硅-硅直接键合技术等，它们对键合材料的种类、键合表面的平整度等的要求较高，否则容易导致键合质量较差甚至键合失败，这限制了晶圆键合工艺在异质集成中的应用。因此，有必要提供一种普适性强、键合难度低且键合强度高的晶圆键合方法。
发明内容
鉴于此，本申请实施例提供一种晶圆键合方法，其能实现具有任意金属键合层的两片晶圆之间的便捷化、高强度键合，并基于该方法还提供了一种半导体结构及半导体器件。
具体地，本申请实施例第一方面提供了一种半导体结构，包括：
第一衬底及多个第一金属键合层，所述多个第一金属键合层间隔设置在所述第一衬底的一侧，相邻的两个所述第一金属键合层之间设有第一绝缘键合层；
第一器件功能层和多个第二金属键合层，所述第二金属键合层设置在所述第一器件功能层朝向所述第一衬底的一侧，所述多个第一金属键合层与所述多个第二金属键合层一一相对设置，相邻的两个所述第二金属键合层之间设有第二绝缘键合层；其中，每个所述第一金属键合层和与之相对的所述第二金属键合层之间还设有导电层，相邻的所述导电层之间设有辅助键合层，所述辅助键合层的材质为绝缘化合物；所述导电层含有与所述辅助键合层中的正价态元素相同的元素，所述第一金属键合层和/或所述第二金属键合层靠近所述导电层一侧的材料的还原性高于所述导电层材料的还原性。
本申请实施例提供的半导体结构中，导电层是与辅助键合层相同的材料经第一金属键合层和/或所述第二金属键合层还原得到。导电层及将其隔开的绝缘键合层可将位于它们上下侧的结构之间建立键合桥梁，实现上下金属键合层之间、上下绝缘键合层之间的高强度接合，保证该半导体结构的整体结构稳定性，且不影响对应设置的第一与第二金属键合层之间的纵向导电连接，及保证沿垂直第一衬底的厚度方向上相邻的第一金属键合层之间/相邻的第二金属键合层之间的横向电绝缘。
本申请实施方式中，所述导电层与所述第一金属键合层或与所述第二金属键合层接触的表面平整且无破损。具体这样特征的导电层能更好地发挥稳固电连接第一金属键合层与第二金属键合层的作用，保证该半导体结构的高结构稳定性。
本申请实施方式中，所述第一金属键合层和/或所述第一金属键合层靠近所述导电层的界面含有与所述辅助键合层中的负价态元素相同的元素。这可在一定程度上反映上述导电层是与辅助键合层相同的材料被第一金属键合层和/或第二金属键合层还原得到，导电层与上下金属键合层的界面之间可存在共价键作用，结合强度更高。
本申请实施方式中，所述辅助键合层包括金属氧化物、金属氮化物、含掺杂元素的氧化硅、含掺杂元素的氮化硅、含掺杂元素的氮氧硅中的一种或多种；所述导电层的材质包括含掺杂元素的硅单质、或者与所述金属氧化物或所述金属氮化物中的金属元素相对应的单质。这些辅助键合层材料的亲水性和绝缘性较好，借助它们可保证所述半导体结构中的上下辅助键合层之间的稳定接合，且与该辅助键合层材料材质相同的材料的还原产物-导电层的导电性良好，便于实现半导体结构对应层之间的良好电连接。
本申请实施方式中，所述金属氧化物及所述金属氮化物中的金属元素包括铝、钽、铪、锆中的一种或多种。此时，含这些元素的导电层的导电性良好、辅助键合层较易制备，并能在较低温度下被常见的金属键合层还原。
本申请实施方式中，所述辅助键合层是一层或两层；所述导电层的层数与所述辅助键合层相同。
本申请一些实施方式中，所述导电层和所述辅助键合层分别为一层，所述导电层和所述辅助键合层的厚度分别在0.5nm-10nm的范围内。较薄的导电层、辅助键合层在较薄的情况下仍可保证第一、第二金属键合层之间的稳固接合、第一、第二辅助键合层之间的稳固接合。
本申请另外一些实施方式中，所述辅助键合层包括层叠设置的第一辅助键合层和第二辅助键合层，且所述第一辅助键合层靠近所述第一绝缘键合层；所述导电层包括层叠设置的第一导电层和第二导电层，且所述第一导电层靠近所述第一金属键合层；其中，所述第一导电层为与所述第一辅助键合层材质相同的材料经所述第一金属键合层还原得到，所述第二导电层为与所述第二辅助键合层材质相同的材料经所述第二金属键合层还原得到。两层结构的辅助键合层更能保证在制备上述半导体结构时，不同区域的键合界面是同类材料，能更好地实现高强度的共价键合，并保证还原反应的进行程度较高、使各导电层的表面状态良好、与相邻的金属键合层之间无空隙等，保证该半导体结构的结构稳定性更高。
本申请实施方式中，所述第一绝缘键合层背离所述第一衬底的表面与所述第一金属键合层背离所述第一衬底的表面齐平；所述第二绝缘键合层朝向所述第一衬底的表面与所述第二金属键合层朝向所述第一衬底的表面齐平。这样可保证所述导电层或辅助键合层背离或朝向第一衬底的表面均是平整的，利于保证该半导体结构的顺利制备及维持良好稳定性。
本申请一些实施方式中，所述第一器件功能层包括间隔设置的多个第一器件功能子层，每个所述第二金属键合层背离所述第一衬底的一侧设有一个所述第二器件功能子层。
本申请一些实施方式中，上述半导体结构还包括：位于所述第一衬底与所述第一金属键合层之间的第二器件功能层，其中，所述第二器件功能层与所述第二器件功能层一一对应设置。这样所述半导体结构中，就可集成两种不同功能的器件功能层，具有较高集成度和较多功能。
本申请实施例第二方面提供了一种半导体器件，包括本申请实施例第一方面所述的半导体结构。该半导体器件的结构稳定性高，可稳定地发挥其功能。
本申请实施方式中，所述半导体器件可以包括光电器件、功率器件、射频器件中的一种。
本申请实施例第三方面提供了一种电子设备，包括本申请实施例第二方面所述的半导体器件。带有上述半导体器件的电子设备可以稳定地运行，市场竞争力突出。
本申请实施例还提供了一种晶圆键合方法，包括以下步骤：
提供待键合的两个晶圆，每个所述晶圆包括衬底，两个所述衬底中至少一者的第一侧上设置有器件功能层；
在所述两个晶圆上分别形成金属键合层，其中，所述金属键合层设置在所述衬底的第一侧；
在带有所述金属键合层的两个晶圆中的至少一者上形成覆盖所述金属键合层的原始辅助键合层，得到处理后的两个晶圆；其中，所述原始辅助键合层为绝缘化合物；
将所述处理后的两个晶圆进行贴合以使两个晶圆上的所述金属键合层相对设置，并对所述贴合后的两个晶圆进行热处理，以使夹在两晶圆中对应设置的所述金属键合层之间的所述原始辅助键合层被还原为导电层。
上述晶圆键合方法，通过在两晶圆中至少一者的金属键合层上引入原始辅助键合层，借助原始辅助键合层可实现两晶圆贴合后的初步稳固接合，并借助热处理实现贴合界面之间的高强度共价键合，以及实现两晶圆的金属键合层对夹在中间的辅助键合层的还原，从而实现两晶圆的导电连接。该晶圆键合方法的工艺简单、普适性强，可便捷地实现具有金属键合层的任意两晶圆之间的高强度键合。
本申请实施方式中，在所述贴合后，所述金属键合层与所述原始辅助键合层相接触的一侧的材料的还原性高于所述原始辅助键合层中的正价态元素所对应单质的还原性。这样能保证特定区域的原始辅助键合层被顺利还原。
本申请实施方式中，所述原始辅助键合层包括金属氧化物、金属氮化物、含掺杂元素的氧化硅、含掺杂元素的氮化硅、含掺杂元素的氮氧硅中的一种。这些原始辅助键合层材料较易制备，且亲水性和绝缘性较好，可保证两晶圆接触后的紧密贴合，并能在较低温度下被常见的金属键合层还原，且它们的还原产物均是可导电的。
本申请实施方式中，所述原始辅助键合层的厚度在0.5-10nm的范围内。原始辅助键合层在较薄的情况 下，不会对晶圆的待键合表面的粗糙度产生不利影响，且利于降低后续热处理的进行时长、减少对晶圆功能的损坏。
本申请实施方式中，所述热处理的温度为100-200℃。较低的热处理温度可在保证原始辅助键合层的还原可顺利进行的同时，还减小了对晶圆上器件功能层的损坏，保证键合后结构能正常发挥作用。
本申请一些实施方式中，所述金属键合层间隔形成在所述衬底的第一侧；且在形成所述原始辅助键合层之前，所述晶圆键合方法还包括：在两晶圆上相邻的所述金属键合层之间还形成绝缘键合层，且所述原始辅助键合层还覆盖所述绝缘键合层；其中，所述绝缘键合层背离所在衬底的表面与所述金属键合层背离所在衬底的表面齐平。
对同时带有金属键合层及绝缘键合层的两晶圆进行混合键合时，通过在两晶圆中的至少一者上引入可覆盖金属键合层及绝缘键合层的原始辅助键合层，可以借助该原始辅助键合层便捷地实现两晶圆贴合后的初步低温键合，并借助热处理实现贴合界面之间的高强度共价键合，以及两晶圆的上下金属键合层仅对夹在中间的原始辅助键合层的原位还原，保证了两晶圆中对应金属键合层之间的纵向导电连接，及同一晶圆中相邻金属键合层之间的横向绝缘隔断。此外，所述绝缘键合层背离所在衬底的一侧表面与所述金属键合层背离所在衬底的一侧表面齐平，这利于后续形成表面平整的辅助键合层，以提升晶圆键合成功率。
附图说明
图1为本申请实施例提供的晶圆键合方法的流程示意图。
图2为本申请一实施例提供的晶圆键合方法的具体过程示意图。
图3为图2所示晶圆键合方法的一种变型过程示意图。
图4为图2所示晶圆键合方法的另一种变型过程示意图。
图5为本申请另一实施例提供的晶圆键合方法的一种具体过程示意图。
图6为图5所示晶圆键合方法的一种变型过程示意图。
图7为图5中两晶圆在贴合、热处理时的另一种过程示意图。
图8为图6中两晶圆在贴合、热处理时的另一种过程示意图。
图9为图5所示晶圆键合方法的另一种变型过程示意图。
图10为本申请又一实施例提供的晶圆键合方法的一种具体过程示意图。
图11为图10所示晶圆键合方法的一种变型过程示意图。
图12为图10所示晶圆键合方法的另一种变型过程示意图。
图13A至图13H为本申请实施例提供的半导体结构的几种结构示意图。
主要附图标记说明：100-半导体结构，1a-第一晶圆，1b-第二晶圆，10a-第一衬底，10b-第二衬底，20a-第二器件功能层，20b-第一器件功能层，30a-第一金属键合层，30b-第二金属键合层，31a-第一绝缘键合层，31b-第一绝缘键合层，40a-第一原始辅助键合层，40b-第二原始辅助键合层，402a-第一导电层，402b-第二导电层，401a-第一辅助键合层；401b-第二辅助键合层，401-辅助键合层，402-导电层。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行说明。
本申请实施例提供了一种晶圆键合方法，请一并参见图1的流程示意图，图2-图3的具体过程示意图，该晶圆键合方法包括以下步骤S01-S04。
S01，提供待键合的两个晶圆，每个晶圆包括衬底，两个衬底中至少一者的第一侧上设置有器件功能层。
其中，衬底可以是蓝宝石衬底、玻璃衬底、硅衬底、碳化硅衬底、硅衬底、锗衬底、绝缘体上硅衬底(SOI衬底)、绝缘体上锗衬底、或III-V族化合物衬底(如氮化镓(GaN)衬底、砷化镓(GaAs)衬底等)。其中，硅衬底的晶体取向不限，例如可以是(111)晶面指数的硅衬底，还可以是其他晶面指数的硅衬底；特别地，用于制作光电器件的晶圆中的硅衬底可以是(111)晶面指数的硅衬底。各器件功能层可以是单层或多层(多层是指大于或等于两层)，层数或各层材质可根据通过晶圆键合形成的半导体器件的功能来选择。在一些实施方式中，所述器件功能层包括基于三五族半导体材料(如GaN、GaAs、AlN、AlGaN、InN等)形成的外延堆叠结构，例如包括层叠设置的缓冲层、n型掺杂层、有源层和p型掺杂层，且缓冲层靠近衬底。包含该外延堆叠结构的器件功能层特别适合制备光电器件。
关于待键合的两个晶圆，在一些实施方式中，可以是两个晶圆都包括衬底及设置在衬底上的器件功能 层，如图2-图3所示，可以将两个晶圆分别称为第一晶圆1a、第二晶圆1b，第一晶圆1a包括第一衬底10a及设置在第一衬底10a的第一侧101a上的第二器件功能层20a，第二晶圆1b包括第二衬底10b及设置在第二衬底10b的第一侧101b上的第一器件功能层20b。图2-图3中，带有器件功能层的两个晶圆中，各器件功能层均是全覆盖所在衬底的第一侧的全部表面区域。在另一些实施方式中，待键合的两个晶圆也可以是一个晶圆包括衬底，另一个晶圆包括衬底及设置在衬底上的器件功能层(下文的图4会对这种情况进行介绍)。
S02，在两个晶圆上分别形成金属键合层，其中，金属键合层设置在所述衬底的第一侧。
其中，各衬底上的所述金属键合层可以是单层金属、或多层金属叠层；每层金属可以是金属单质、或者金属合金，或者是金属合金与金属单质构成的复合层。本申请实施方式中，所述金属键合层不为铜单质。这样可较顺利地保证金属键合层对下文原始辅助键合层的还原。其中，所述金属键合层的材料包括Ti、Cr、Ni、Ta、Au、In、Sn、Ag、Al、W及前述至少两种元素的合金、TiN、TaN中的一种或多种。例如，金属键合层可以是Ti层、Ta层、Cr层、Ni层、TiCr合金层、NiCrTi合金层、Ti层与Ni层的叠层等。其中，金属键合层可以通过电镀、或物理气相沉积(如溅射、电子束蒸镀、热蒸发)等方式制备，但不限于此。本申请中，金属键合层的厚度可以介于几纳米至数十微米之间，如在10nm-10μm的范围内，具体可以是20nm、30nm、50nm、60nm、80nm、100nm、150nm、200nm、500nm、800nm、1μm、5μm或8μm等。
如图2-图3所示，经上述步骤S02的处理后，第一晶圆1a还包括层叠在第二器件功能层20a背离第一衬底10a一侧上的第一金属键合层30a，第一金属键合层30a也位于第一晶圆1a的第一侧101a。类似地，第二晶圆1b还包括层叠在第一器件功能层20b背离第二衬底10b一侧上的第二金属键合层30b，第二金属键合层30b也位于第二晶圆1b的第一侧101b。更具体地，图2中，第一金属键合层30a是全覆盖第二器件功能层20a背离第一衬底10a的一侧表面，图3中，第二金属键合层30b是全覆盖第一器件功能层20b背离第二衬底10b的一侧表面。
S03，在带有所述金属键合层的两个晶圆中的至少一者上形成覆盖所述金属键合层的原始辅助键合层，得到处理后的两个晶圆；其中，所述原始辅助键合层为绝缘化合物。
在进行步骤S03时，可以在两个晶圆上都制备原始辅助键合层(如图2所示)，也可以仅在其中一个晶圆上制备原始辅助键合层(如图3所示)。相应地，在下述步骤S04中将两晶圆贴合后，贴合后的结构中原始辅助键合层的总层数可以是一层或两层。其中，图2中，第一晶圆1a中，第一金属键合层30a背离第一衬底10a的一侧表面上形成有第一原始辅助键合层40a，其覆盖了第一金属键合层30a，由于第一金属键合层30a是整面覆盖第一衬底10a，该第一原始辅助键合层40a也相应实现了对第一衬底10a的整面覆盖；类似地，第二晶圆1b中，第二金属键合层30b背离第二衬底10b的一侧形成有第二原始辅助键合层40b。而图3中，仅第二衬底10b上形成了可覆盖第二金属键合层30b的原始辅助键合层40。
本申请实施方式中，各原始辅助键合层的厚度小于金属键合层的厚度，例如原始辅助键合层的厚度是金属键合层的厚度的0.1％-10％。以图2来例，具体是第一原始辅助键合层40a的厚度小于第一金属键合层30a的厚度、第二原始辅助键合层40b的厚度小于第二金属键合层30b的厚度。本申请实施方式中，第一原始辅助键合层40a、第二原始辅助键合层40b的厚度可分别在0.5nm-100nm的范围内；在一些实施方式中，该厚度可以在0.5nm-10nm的范围内，例如为0.6nm、0.8nm、1nm、1.5nm、2nm、3nm、5nm、8nm、9.5nm、10nm等。较薄的原始辅助键合层不会对晶圆上的金属键合层等待键合表面的粗糙度产生不利影响，且利于降低后续热处理的进行时长、减少对晶圆的破坏。在一些实施方式中，原始辅助键合层的厚度可以大于或等于一个分子层且小于5个分子层，具体可以是0.5nm-3nm。其中“一个分子层”是指原始辅助键合层的构成材料的单层分子的厚度。
本申请实施方式中，各原始辅助键合层的材质独立地包括金属氧化物、金属氮化物、含掺杂元素的氧化硅、含掺杂元素的氮化硅、含掺杂元素的氮氧硅中的一种或多种。即，原始辅助键合层的材质可以相同或不同。其中，所述金属氧化物及所述金属氮化物中的金属元素包括铝Al、钽Ta、铪Hf、锆Zr中的一种或多种。所述掺杂元素包括n型掺杂元素(如砷As、磷P)和/或p型掺杂元素(如硼B)。掺杂元素可保证含掺杂元素的氧化硅、氮化硅或氮氧硅被还原后的产物是可导电的，该还原产物具体的是含掺杂元素的硅单质。其中，原始辅助键合层可以通过低压化学气相沉积工艺、金属有机化学气相沉积工艺、等离子体增强化学气相沉积工艺、原子层沉积、物理气相沉积工艺或激光脉冲沉积工艺等形成。
原始辅助键合层为上述绝缘材料时一般具有较好的亲水性，表面常具有羟基悬挂键，或者其经水或含水溶液或亲水性有机溶剂处理或等离子体轰击后，表面可具有足够多的亲水性羟基，这利于借助该原始辅助键合层在低温下(可包含常温，这是相较于后续“热处理”的温度而言)实现两晶圆间的足够键合强度的 氢键键合，进而在后续热处理利于键合界面转变为更高强度的共价键键合。此外，上述原始辅助键合层材料可在多种金属键合层上形成，对待键合金属层的种类、表面状况等的要求不高，且该材料使得原始辅助键合层对厚度要求很低，通常几nm就足以将两晶圆初步键合在一起，且形成较薄的原始辅助键合层不会对键合表面的粗糙度产生不利影响，还可保证后续两晶圆贴合后的热处理的进行时长较短、温度较低，降低对晶圆结构的损害。
其中，所述原始辅助键合层的材质可基于金属键合层来选择，并以“两个晶圆在经S04贴合后得到的结构中，金属键合层与原始辅助键合层相接触一侧的材料的还原性高于原始辅助键合层中的正价态元素所对应单质的还原性”为原则。也即，本申请不强制要求整体金属键合层材料的还原性都高于原始辅助键合层中正价态元素所对应的单质，仅要求与原始辅助键合层相接触的那部分金属键合层材料满足即可，这就拓宽了本申请晶圆键合方法的适用范围，特别是在金属键合层为多层金属叠层时，使得原始辅助键合层可在具有任意金属键合层的晶圆上设置，以实现两晶圆的便捷键合。
其中，当原始辅助键合层为金属氧化物或金属氮化物时，原始辅助键合层中的正价态元素所对应的单质是指金属氧化物或金属氮化物中金属元素所对应的单质。当该原始辅助键合层为含掺杂元素的氧化硅、氮化硅或氮氧硅，所述正价态元素具体是指硅元素所对应的单质。在一些实施例中，所述原始辅助键合层为Al的氧化物或者氮化物，此时，金属键合层靠近原始辅助键合层的一侧的金属材料可以包括Ti、Cr、Ni中的至少一种。在另一些实施例中，所述原始辅助键合层为钽Ta、铪Hf、锆Zr的氧化物或氮化物，此时，金属键合层靠近原始辅助键合层的一侧的金属材料包括Al、Ti、Cr、Ni中的至少一种。
S04，将步骤S03处理后的两个晶圆进行贴合以使两个晶圆上的所述金属键合层相对设置，并对所述贴合后的两个晶圆进行热处理，以使夹在两晶圆对应设置的金属键合层之间的所述原始辅助键合层被还原为导电层。
“贴合”是指两晶圆的待贴合表面相接触。其中，对于两晶圆上都有原始辅助键合层的图2来说，该贴合是指第一原始辅助键合层40a与第二原始辅助键合层40b相接触；对于两晶圆中仅一者带有原始辅助键合层的图3来说，该贴合是指第二晶圆1b上的原始辅助键合层40与第一晶圆1a上的第一金属键合层30a接触。贴合后，两晶圆上的上下两金属键合层是相对设置并对准的。需要说明的是，这里的“对准”并不局限于“完全对准”(完全对准是指沿衬底的厚度方向，任意相对设置的上下两金属键合层的侧壁是齐平的)，可允许有一定偏移，本申请下文会对偏移对准的情况进行说明。其中，当两晶圆上分别有若干个金属键合层时，该“对准”具体是指一个晶圆上的任一个金属键合层都与另一晶圆上的一个金属键合层一一对应，且每一对相对设置的上下两金属键合层在原始辅助键合层上的正投影都有一定的重叠区域。
本申请一些实施方式中，在将上述处理后的两个晶圆进行所述贴合之前，还包括：对两个晶圆的待贴合表面进行亲水性处理。对晶圆的待贴合表面进行亲水性处理，可利于两晶圆在贴合后，两晶圆的贴合表面之间可形成一定数目的氢键，增加两晶圆贴合后的强度，并更利于后续热处理时还原反应的发生。如本申请前文所述，对原始辅助键合层进行亲水性处理后，可增加其表面的羟基悬挂数量；而对金属键合层的亲水性处理也利于其表面形成一定的亲水性基团(如-OH)，以保证其与原始辅助键合层之间的紧密贴合。其中，该亲水性处理可以包括等离子体轰击(如氧等离子轰击)，或者化学机械抛光(Chemical Mechanical Polishing，CMP)，或者使用水或亲水性试剂进行喷淋、浸泡、浸润等，或者采用前述方式的多种组合等。其中，亲水性试剂可以是氨溶液、弱酸等含水溶液，或者含羟基的亲水性有机溶剂。在使用水进行亲水性处理时，可具体包括使用去离子水进行喷淋或浸泡、用水蒸气进行浸润等。
本申请中，对贴合后的两个晶圆进行热处理，两晶圆的贴合界面可逐渐从氢键键合转变为共价键键合，同时夹设在相对设置的两个所述金属键合层之间的原始辅助键合层被还原为导电层，具体是被与其接触的金属键合层被还原，两晶圆之间借助金属键合层及之间的导电层实现了导电连接。可以理解地，两个晶圆在贴合后得到的结构中，所述金属键合层与原始辅助键合层相接触一侧的材料的还原性高于原始辅助键合层中的正价态元素所对应单质的还原性。其中，若前述仅在一个晶圆上形成了所述原始辅助键合层，则在贴合后，可以是两晶圆中至少一者上的金属键合层满足上述还原性的要求。
其中，图2中，第一金属键合层30a靠近第一原始辅助键合层40a一侧的材料的还原性应高于第一原始辅助键合层40a中的正价态元素所对应单质的还原性，第二金属键合层30b靠近第二原始辅助键合层40b一侧的材料的还原性应高于第二原始辅助键合层40b中的正价态元素所对应单质的还原性，这样可使第一原始辅助键合层40a被第一金属键合层30a还原成第一导电层402a、第二原始辅助键合层40b被第二金属键合层30b还原成第二导电层402b。图3中，第一金属键合层30a和/或第二金属键合层30b靠近原始辅助键合层40一侧的材料的还原性应高于原始辅助键合层40中的正价态元素所对应单质的还原性。这样也 可保证图3中的两个晶圆在贴合后，原始辅助键合层40可被与其接触的一侧或两侧的金属键合层还原。此外，当如图2中那样在两晶圆上都制备原始辅助键合层时，第一原始辅助键合层40a与第二原始辅助键合层40b的材料可以相同或不同，并以相同为优。当二者是相同材料时，在两晶圆贴合、热处理时，能保证贴合界面处的共价键结合力更强，提高第一导电层402a、第二导电层402b之间的键合强度。
本申请实施方式中，所述热处理可以在温度为100-1000℃下进行，进行时间可以为1min-10h。在一些实施方式中，热处理的进行温度为100-600℃下进行，例如具体为100℃、150℃、200℃、220℃、250℃、300℃、350℃、400℃、450℃、500℃、550℃或580℃等，热处理的进行温度进一步可以在100-200℃的范围内。较低的热处理温度可在保证原始辅助键合层的还原可顺利进行的同时，还减小了对晶圆上器件功能层的损坏，保证键合后结构能正常发挥作用。热处理的进行时间可以具体是5min、10min、15min、20min、30min、40min、1h、2h、3h、5h、8h等。热处理的具体进行温度及时间可根据原始辅助键合层的材质或厚度等进行调控。
需要说明的是，步骤S04中，所述“贴合”可以加压条件下进行，例如对第一衬底、第二衬底中的一者或两者施加压力。此外，所述贴合及所述热处理可以同时进行，例如在具有加热功能的键合机中进行，也可以是“贴合”在键合机中进行，“热处理”在其他加热设备(如管式炉、快速退火炉等)中后进行。
基于现有技术将直接带有金属键合层的两晶圆之间进行键合，会对金属键合层的类别、键合表面的平整度、致密度等均有严苛复杂的要求，而本申请实施例包括步骤S01-S04的上述晶圆键合方法，通过在两晶圆中至少一者的金属键合层上引入原始辅助键合层，借助原始辅助键合层的亲水性，可实现两晶圆贴合后的初步稳固接合，拉近晶圆之间的距离，并借助热处理可实现贴合界面之间的高强度共价键合，及两晶圆的金属键合层对夹在中间的原始辅助键合层的原位还原，实现两晶圆的导电连接。因此，上述晶圆键合方法的工艺简单、普适性强、键合难度低，可以实现具有金属键合层的任意两晶圆之间的便捷化、高强度键合，降低了常规晶圆键合方法中对衬底材料、键合材料、键合工艺等的过度依赖。
其中，当在两晶圆的金属键合层上都引入原始辅助键合层时，可保证两晶圆的键合表面均分别被同种材料覆盖，降低键合难度，且两晶圆在贴合后可便捷地实现初步氢键键合，并更好地拉近晶圆之间的距离，更利于热处理时还原反应的进行，保证所得导电层的表面状态良好(如无孔洞)、与金属键合层之间无空隙等。此外，在原始辅助键合层的厚度较低时，仍可将两晶圆稳定地键合在一起，且沉积较薄的该膜层不会对晶圆的待键合表面的粗糙度产生不利影响而影响键合进行，可省去对待键合表面的平坦化处理，降低了键合工艺的复杂度，还可降低热处理过程中对晶圆结构/功能的损伤。
本申请一些实施方式中，在上述步骤S04之后，还包括步骤S05：去除两个衬底中的一个，得到半导体结构100。如图2或图3中均以去除第二衬底10b进行示例。其中，衬底的去除可以通过机械研磨、CMP、湿法腐蚀、干法刻蚀等方法来实现，并保留其中一侧的晶圆衬底，以便进行后续的晶圆器件加工流程。
需要说明的是，若步骤S01中所用两个晶圆中只有一者的衬底的第一侧上带有器件功能层，则在进行去除一个衬底的操作时，一般去除的是带器件功能层的那个晶圆的衬底，后续一般会在露出的器件功能层上进行后续工序制程。具体地，可参见图4，图4为图2所示晶圆键合方法的另一种变型过程示意图。图4与图2的区别在于：在形成金属键合层之前，第一晶圆1a仅包括第一衬底10a，而第一衬底10a的第一侧101a上无第二器件功能层20a，第二晶圆1b还是包括第二衬底10b及设置其第一侧101b上的第一器件功能层20b。相应地，第一金属键合层30a是直接与第一衬底10a的第一侧表面接触，第二金属键合层30b设置在第一器件功能层20b背离第二衬底10b一侧。在经过贴合处理及热处理之后，去除的是第二晶圆1b上的第二衬底10b。
图5为本申请另一实施例提供的晶圆键合方法的一种具体过程示意图。图5与图2示出方法的主要不同之处在于：金属键合层是间隔形成在衬底上，并在金属键合层之间引入了绝缘键合层。具体地，图5所示的晶圆键合方法包括：
S501，如图5中(A)所示，提供待键合的两个晶圆-第一晶圆1a及第二晶圆1b，第一晶圆1a包括第一衬底10a及设置在第一衬底10a的第一侧101a上的第二器件功能层20a，第二晶圆1b包括第二衬底10b及设置在第二衬底10b的第一侧101b上的第一器件功能层20b。其中，第二器件功能层20a全覆盖第一衬底10a的第一侧101a，第一器件功能层20b全覆盖第二衬底10b的第一侧101b。
S502，在两个晶圆上分别形成间隔设置的多个金属键合层，所述金属键合层位于衬底的第一侧，相邻的两个金属键合层之间还形成绝缘键合层，其中，所述绝缘键合层背离所在衬底的表面与所述金属键合层背离所在衬底的表面齐平。
如图5中(B)所示，第二器件功能层20a背离第一衬底10a的一侧表面形成有间隔设置的多个第一 金属键合层30a，相邻的两个第一金属键合层30a夹设有第一绝缘键合层31a，类似地，第一器件功能层20b背离第二衬底10b的一侧表面形成有间隔设置的多个第二金属键合层30b，相邻的两个第二金属键合层30b夹设有第二绝缘键合层31b。其中，第一绝缘键合层31a背离第一衬底10a的表面与第一金属键合层30a背离第一衬底10a的表面齐平，第二绝缘键合层31b背离第二衬底10b的表面与第二金属键合层30b背离第二衬底10b的表面齐平。也即，第一绝缘键合层31a与第一金属键合层30a的厚度相同，第二绝缘键合层31b与第二金属键合层30b的厚度相同。参见本申请前文对金属键合层的厚度描述，可以理解的是，第一绝缘键合层31a、第二绝缘键合层31b的厚度可分别介于几纳米至数十微米之间，例如在10nm-10μm的范围内。此外，各绝缘键合层的材质可以与下文的原始辅助键合层可以相同或者不同，各绝缘键合层包括但不限于氧化硅、氮化硅、氧化钛、氧化铝等各种介质材料。
由于同一晶圆的不同区域同时存在金属键合层及绝缘键合层，也即不同键合区域存在两种不同的键合材料，对这样的两晶圆的键合可称为“混合键合”。现有技术进行混合键合时一般是将金属键合层之间直接键合、将绝缘键合层之间直接键合，但因不同键合材料的表面处理、键合条件都各自有严格的要求，这使得混合键合的进行难度增大、失败率增加。因此本申请实施例引入了下述原始辅助键合层及相关处理。
S503，在带有所述金属键合层及绝缘键合层的两个晶圆中的至少一者上形成覆盖所述金属键合层及所述绝缘键合层的原始辅助键合层；其中，所述原始辅助键合层为绝缘化合物。
如图5中(C)所示，在第一晶圆的第一侧101a形成了覆盖第一金属键合层30a及第一绝缘键合层31a的一整面的第一原始辅助键合层40a，在第二晶圆的第一侧101b形成了覆盖第二金属键合层30b及第二绝缘键合层31b的一整面的第二原始辅助键合层40b。其中，各原始辅助键合层的厚度、材质、作用等选择可参见本申请前文的描述。
在进行两晶圆的混合键合时，引入上述原始辅助键合层，保证了形成有原始辅助键合层的晶圆中不同区域的键合材料被同一材料覆盖，降低了两晶圆的键合难度。其中，在两晶圆的衬底上都引入原始辅助键合层时，可保证两晶圆中不同区域的键合材料均被同种材料覆盖，两晶圆的混合键合变成介质材料的键合，这就降低了对金属键合层和绝缘键合层材料、表面处理等的要求，可以在简单的键合条件下便捷地实现高质量的混合键合。
本申请实施方式中，所述原始辅助键合层背离所在晶圆衬底的表面是平整的。对图5中(C)来说，第一原始辅助键合层40a背离第一衬底10a的表面是平整的、第二原始辅助键合层40b背离第二衬底10b的表面是平整的。这样能更便捷地完成两晶圆的键合、键合成功率更高。
S504，将经过上述处理后的两个晶圆进行贴合，以使两个晶圆上的各金属键合层一一相对设置、相应地各绝缘键合层也一一相对设置，并对贴合后的两个晶圆进行热处理，以使夹设在两晶圆中对应设置的两个金属键合层(即，沿衬底厚度方向相对设置的两金属键合层)之间的原始辅助键合层被还原为导电层，具体是被与金属键合层接触的那部分原始辅助键合层被还原，而其他区域的原始辅助键合层仍保持原状。
如图5中(D)所示，两晶圆在贴合后，第一原始辅助键合层40a与第二原始辅助键合层40b相接触，其中，借助原始辅助键合层材料表面的羟基悬挂键，两晶圆可实现羟基键合。且，每一个第一金属键合层30a都有一个第二金属键合层30b与其相对设置，第一绝缘键合层31a都与一个第二绝缘键合层31b与其相对设置。贴合后的两晶圆在经过热处理后，如图5中(E)所示，两晶圆的键合界面转为更高结合强度的共价键合，且夹在第一金属键合层30a与第二金属键合层30b之间的第一原始辅助键合层40a及第二原始辅助键合层40b被还原，具体是第一原始辅助键合层40a被与其接触的第一金属键合层30a还原成第一导电层402a、第二原始辅助键合层40b被与其接触的第二金属键合层30b还原成第二导电层402b；而夹在第一绝缘键合层31a与第二绝缘键合层31b之间的那部分第一原始辅助键合层及第二原始辅助键合层仍保持原状，为便于区分，分别以标号401a、401b指代。可以理解的是，沿垂直第一衬底10a的厚度方向，相邻的第一导电层402a之间设有第一辅助键合层401a，相邻的第二导电层402b之间设有第二辅助键合层401b。
此外，如本申请前文所述，在对晶圆进行所述贴合之前，还可以对待贴合表面进行亲水性处理；所述亲水性处理、贴合、热处理等的工艺条件可参见前文的描述。在步骤S504的热处理之后，还包括“去除两个衬底中一个衬底”的步骤。
对于同时带有导电的金属键合层及不导电的绝缘键合层的两晶圆之间的混合键合，包括步骤S501-S504的本申请实施例上述晶圆键合方法，通过在两晶圆中的至少一者上引入覆盖金属键合层及绝缘键合层的原始辅助键合层，可以借助该原始辅助键合层便捷地实现两晶圆贴合后的初步低温键合，并借助热处理实现贴合界面之间的高强度共价键合，以及两晶圆的上下金属键合层仅对夹在中间的原始辅助键合 层的原位还原，保证了两晶圆中对应金属键合层之间的纵向导电连接，同时借助上下绝缘键合层之间保持原状的不导电辅助键合层保障了同一晶圆中相邻金属键合层之间的电流绝缘隔断。
图6为图5所示晶圆键合方法的一种变型过程示意图。图6与图5示出方法的主要不同之处在于：图6中仅在第二晶圆1b上形成原始辅助键合层40。图6所示方法的有益效果与图5类似，这里不再赘述。
图6中，在两晶圆贴合后，第二金属键合层30b和/或第一金属键合层30a靠近原始辅助键合层40一侧的材料的还原性应高于原始辅助键合层40中的正价态元素所对应单质的还原性。这样在热处理时，夹在第一金属键合层30a与第二金属键合层30b之间的那部分原始辅助键合层40可被还原成导电层402，其中该原始辅助键合层40可以具体是被第一金属键合层30a还原，或者是被第二金属键合层30b还原，或者被第一金属键合层30a及第二金属键合层30b共同还原，具体还原情况可根据这三者的具体材料来定。
需要说明的是，图5、图6中是以贴合时两晶圆上的金属键合层是完全对准的情况进行了示意，但可以理解的是，两晶圆上金属键合层的对准还可以允许有一定偏移，具体可参见图7及图8。
图7为图5中两晶圆在贴合、热处理时的另一种过程示意图。图7中，在两晶圆贴合后，第一金属键合层30a与第二金属键合层30b虽是一一相对设置，但二者并未完全对准，发生了一定偏移，相应地，第一绝缘键合层31a与第二绝缘键合层31b也是一一相对设置、但未完全对准的。在热处理时，与第一金属键合层30a接触的第一原始辅助键合层40a被第一金属键合层30a还原成第一导电层402a、与第二金属键合层30b接触的第二原始辅助键合层40b被第二金属键合层30b还原成第二导电层402b，即，第一导电层402a的分布位置基本与第一金属键合层30a一致、第二导电层402b的分布位置基本与第二金属键合层30b一致。
图8为图6中两晶圆在贴合、热处理时的另一种过程示意图。图8中，在两晶圆贴合后，若第二金属键合层30b及第一金属键合层30a靠近原始辅助键合层40一侧的材料的还原性均高于原始辅助键合层40中的正价态元素所对应单质的还原性，此时若第一金属键合层30a与第二金属键合层30b是一一相对设置、但未完全对准的，则夹在第一金属键合层30a与第二金属键合层30b之间的、与二者相接触的原始辅助键合层40被二者共同还原成导电层402，也即，所得导电层402对应与第一金属键合层30a/第二金属键合层30b接触的那部分辅助键合层的并集。
可见，即使两晶圆在贴合时未能将两晶圆上的各金属键合层完全对准，采用本申请实施例提供的引入原始辅助键合层的晶圆键合方法时，仍能保证未完全对准的上下两金属键合层之间的纵向导电连接，及横向上金属键合层之间的绝缘隔断。
图9为图5所示晶圆键合方法的另一种变型过程示意图。图9与图5的区别在于：所用的两晶圆中仅一个带有器件功能层，图9中具体是第二晶圆1b带有器件功能层。在形成辅助键合层之前，第一晶圆1a仅包括第一衬底10a及间隔形成在其第一侧101a上的多个第一金属键合层30a，相邻的两个第一金属键合层30a夹设有第一绝缘键合层31a。在两晶圆贴合及热处理之后，将带器件功能层的第二晶圆1b中的第二衬底10b去除。
图10为本申请又一实施例提供的晶圆键合方法的一种具体过程示意图。图10与图2示出方法的主要不同之处也是在于：金属键合层是间隔形成在衬底上，并在金属键合层之间引入了绝缘键合层。其中，图10与衬底上间隔形成有金属键合层的图5的主要不同之处在于：器件功能层在衬底上的分布情况不同。图10所示的晶圆键合方法可具体包括：
步骤1，如图10中(A)所示，提供待键合的两个晶圆-第一晶圆1a及第二晶圆1b，第一晶圆1a包括第一衬底10a及间隔设置在第一衬底10a的第一侧101a上的多个第二器件功能层20a，第二晶圆1b包括第二衬底10b及间隔设置在第二衬底10b的第一侧101b上的多个第一器件功能层20b。
步骤2，在两个晶圆上分别形成间隔设置的多个金属键合层，其中，金属键合层位于所在衬底的第一侧，相邻的两个所述金属键合层之间还形成绝缘键合层。其中，绝缘键合层背离所在衬底的表面与金属键合层背离所在衬底的表面齐平。这样利于后续形成表面平整的辅助键合层，以提升晶圆键合成功率。
结合图10中(B)来说，具体是在各个第二器件功能层20a背离第一衬底10a的一侧表面(可称为第三表面201a)形成可覆盖该第三表面201a的第一金属键合层30a，在各第一器件功能层20b背离第二衬底10b的一侧表面(可称为第三表面201b)形成可覆盖该第三表面201b的第二金属键合层30b。由于各器件功能层是在所在衬底上间隔分布，设置在各器件功能层上的金属键合层相应也是间隔分布的。其中，第二器件功能层20a与第一金属键合层30a构成的层叠结构之间设有第一绝缘键合层31a，第一绝缘键合层31a可与第一衬底10a接触，其厚度等于第二器件功能层20a与第一金属键合层30a的厚度之和，以保证第一绝缘键合层31a背离第一衬底10a的表面与第一金属键合层30a背离第一衬底10a的表面齐平。类似地， 第一器件功能层20b与第二金属键合层30b构成的层叠结构之间设有第二绝缘键合层31b，第二绝缘键合层31b可与第二衬底10b接触，其厚度等于第一器件功能层20b与第二金属键合层30b的厚度之和，以保证第二绝缘键合层31b背离第二衬底10b的表面与第二金属键合层30b背离第二衬底10b的表面齐平。
步骤3，在带有所述金属键合层及所述绝缘键合层的两个晶圆中的至少一者上形成覆盖所述金属键合层及所述绝缘键合层的原始辅助键合层；其中，所述原始辅助键合层为绝缘化合物。如图10中(C)所示，第一晶圆的第一侧101a形成有覆盖第一金属键合层30a及第一绝缘键合层31a的第一原始辅助键合层40a，第二晶圆的第一侧101b形成有覆盖第二金属键合层30b及第二绝缘键合层31b的第二原始辅助键合层40b。其中，各辅助键合层的厚度、材质、作用等选择可参见本申请前文的描述。与图5相同的是，第一原始辅助键合层40a背离第一衬底10a的表面是平整的、第二原始辅助键合层40b背离第二衬底10b的表面是平整的。这样能更便捷地完成两晶圆的键合、键合成功率更高。
步骤4，如图10中(D)所示，将经过上述步骤1-3处理后的两个晶圆进行贴合，以使两个晶圆上的各金属键合层一一相对设置并对准、相应地各绝缘键合层也一一相对设置并对准，并对贴合后的两个晶圆进行热处理，以使夹设在两晶圆中对应设置的两个金属键合层之间的原始辅助键合层被还原为导电层，如图10中(E)所示。具体地，在热处理过程中是与金属键合层接触的那部分原始辅助键合层被还原，而其他区域的辅助键合层仍保持原状。
针对同时带有导电的金属键合层及不导电的绝缘键合层的两晶圆之间的混合键合，图10示出的上述晶圆键合方法，通过在两晶圆中至少一者上引入覆盖金属键合层及绝缘键合层的原始辅助键合层，借助该原始辅助键合层可便捷地实现两晶圆中对应金属键合层之间、对应绝缘键合层之间的高质量键合，并借助两晶圆的上下金属键合层仅对夹在中间的那部分原始辅助键合层的原位还原，可以实现两晶圆之间上下器件功能层在纵向上的导电连接，及同一晶圆中各分立器件功能层之间的电流绝缘隔断。
图11为图10所示晶圆键合方法的一种变型过程示意图。图11与图10示出方法的主要不同之处在于：图11中仅在第二晶圆1b上形成一层原始辅助键合层40。在两晶圆贴合、热处理后，沿衬底的厚度方向，夹设在上下两金属键合层之间的导电层402也是一层。
关于图11中第一金属键合层30a与第二金属键合层30b的材料还原性与原始辅助键合层40材料的关系，可参见上文对图6的描述。图11所示方法的有益效果与图10类似，这里不再赘述。
图12为图10所示晶圆键合方法的另一种变型过程示意图。图12与图10的区别在于：所用两晶圆中仅一个晶圆带有器件功能层，图12中具体是第二晶圆1b带有间隔设置的多个第一器件功能层20b。
其中，在形成原始辅助键合层之前，第一晶圆1a仅包括第一衬底10a及间隔形成在其第一侧101a上的多个第一金属键合层30a，相邻的两个第一金属键合层30a夹设有第一绝缘键合层31a。第一绝缘键合层31a的厚度与第一金属键合层30a相同，这样二者背离第一衬底10a的表面可齐平。而第二晶圆1b包括第二衬底10b及间隔设置在第二衬底10b的第一侧101b上的多个第一器件功能层20b，各第一器件功能层20b背离第二衬底10b的一侧表面形成可覆盖该第一器件功能层20b的第二金属键合层30b，第一器件功能层20b与第二金属键合层30b构成的层叠结构之间设有第二绝缘键合层31b，第二绝缘键合层31b的厚度等于第一器件功能层20b与第二金属键合层30b的厚度之和，以保证第二绝缘键合层31b背离第二衬底10b的表面与第二金属键合层30b背离第二衬底10b的表面齐平。
图12中，在两晶圆贴合及热处理之后，在去除衬底时，具体是将带器件功能层的第二晶圆1b中的第二衬底10b去除。图12所示方法的有益效果与图10类似，这里不再赘述。
本申请实施例上述的晶圆键合方法可以适合面向功率电子器件、射频电子器件、LED(light emitting diode，发光二极管)、MEMS(Micro Electro Mechanical System，微机电系统)、等半导体制造工艺中的晶圆键合。
下面介绍本申请实施例提供的半导体结构。该半导体结构可以通过本申请实施例上述的晶圆键合方法制备得到。
本申请一些实施方式中提供了一种半导体结构，该半导体结构同时含有金属键合层及绝缘键合层，故也可将此种情况下的半导体结构称为“混合键合半导体结构”。
图13A、图13B为本申请一些实施例提供的半导体结构的结构示意图。请一并参阅图13A、图13B，该半导体结构100具体包括：
第一衬底10a及多个第一金属键合层30a，多个第一金属键合层30a间隔设置在第一衬底10a的第一侧101a，相邻的两个第一金属键合层30a之间设有第一绝缘键合层31a；
第一器件功能层20b和多个第二金属键合层30b，第二金属键合层30b设置在第一器件功能层20b朝 向第一衬底10a的一侧，多个第一金属键合层30a与多个第二金属键合层30b一一相对设置，沿垂直于第一衬底10a的厚度方向，相邻的两个第二金属键合层30b之间设有第二绝缘键合层31b(相应地，各第二绝缘键合层31b也与第一绝缘键合层31a一一相对设置)。其中，每个第一金属键合层30a和与其相对的第二金属键合层30b之间还设有导电层402，沿垂直于第一衬底10a的厚度方向(图中的z方向)，相邻的导电层402之间设有辅助键合层401，辅助键合层401的材质为绝缘化合物。
其中，导电层402含有与辅助键合层401中的正价态元素相同的元素，沿第一衬底10a的厚度方向，第一金属键合层30a和/或第二金属键合层30b靠近导电层402的一侧的材料的还原性高于导电层402的材料的还原性。由此可反映，导电层402是与辅助键合层401相同的材料经第一金属键合层30a和/或第二金属键合层30b还原得到。
在上述半导体结构100中，导电层402及与其同平面设置的辅助键合层401将位于它们上下侧的结构之间建立键合桥梁，保证半导体结构100的整体结构较稳定，实现上下金属键合层之间、上下绝缘键合层之间的高强度接合，且不影响上下金属键合层之间的纵向导电连接，及垂直第一衬底的厚度方向上的相邻金属键合层之间的横向电绝缘。
本申请实施方式中，第一金属键合层30a和/或第二金属键合层30b靠近导电层402的界面含有与辅助键合层401中的负价态元素相同的元素。这可反映第一金属键合层30a和/或第二金属键合层30b夺取了与辅助键合层401材质相同的材料中的负价态元素。也可在一定程度上反映导电层402是与辅助键合层401相同的材料被第一金属键合层30a和/或第二金属键合层30b化学还原得到。此外，这也可说明导电层与上下金属键合层的界面之间可存在共价键作用，结合强度更高。
本申请实施方式中，导电层402与第一金属键合层30a或与第二金属键合层30b接触的表面平整且无破损。该导电层402的形成是原位化学反应的结果，该膜层的表面状态相较于未被还原的辅助键合层401的表面状态未发生明显破坏，这利于保证导电层402与第一金属键合层30a、第二金属键合层30b之间的良好导电连接，保证半导体结构100的结构较稳定。
对于上述“沿垂直第一衬底10a的厚度方向，相邻的导电层402之间夹设有辅助键合层401”，也即，沿第一衬底10a的厚度方向，每一第一绝缘键合层31a与一个第二绝缘键合层31b之间夹设有辅助键合层401。其中，导电层402与辅助键合层401的厚度相同，二者共平面设置。
图13A所示的半导体结构100可以采用与上述图9所示的类似方法(不同之处是仅在一个晶圆上形成介质辅助层)制备得到。图13A中，第一器件功能层20b为一完整膜层，多个第二金属键合层30b间隔设置在第一器件功能层20b朝向第一衬底10a的一侧。第一器件功能层20b覆盖多个第二金属键合层30b背离第一衬底10a的一侧表面及多个第二绝缘键合层31b背离第一衬底10a的一侧表面。
图13B所示的半导体结构100可以采用与上述图12所示的类似方法(不同之处是仅在一个晶圆上形成介质辅助层)制备得到。图13B中，每一第二金属键合层30b背离第一衬底10a的一侧均设有(具体是覆盖有)一个第一器件功能层20b。即，第一器件功能层20b有多个，其数目与第二金属键合层30b的数目一致；多个第一器件功能层20b在第一衬底10a上的正投影是间隔分布的。从另一角度来说，可将图13B中的第一器件功能层是一个非连续膜层，可看成包括间隔设置的多个第一器件功能子层，每一第二金属键合层30b背离第一衬底10a的一侧均设有一个第一器件功能子层，这里不再单独标号。
本申请实施方式中，如图13A及图13B所示，第一绝缘键合层31a背离第一衬底10a的表面与第一金属键合层30a背离第一衬底10a的表面齐平；第二绝缘键合层31b朝向第一衬底10a的表面与第二金属键合层30b朝向第一衬底10a的表面齐平。这样可保证导电层402及辅助键合层401背离或朝向第一衬底10a的表面均是平整的，利于保证上述半导体结构的顺利制备及维持良好稳定性。其中，图13A中，第一绝缘键合层31a与第一金属键合层30a的厚度相同，第二绝缘键合层31b与第二金属键合层30b的厚度相同；图13B中，第一绝缘键合层31a与第一金属键合层30a的厚度相同，但第二绝缘键合层31b的厚度等于第二金属键合层30b与第一器件功能层20b的厚度之和。
本申请实施方式中，辅助键合层401可以是一层(如图13A、图13B所示)或者两层；导电层402的层数与辅助键合层401的层数相同。在一些实施方式中，辅助键合层401、导电层402为一层，此时辅助键合层401、导电层402的厚度可分别在0.5nm-100nm的范围内，例如优选在0.5nm-10nm的范围内，具体可参见前文对单层初始辅助键合层的相关描述。此外，第一金属键合层30a及第二金属键合层30b的材质、厚度等也可参见前文的描述。
本申请实施方式中，辅助键合层401的材质包括金属氧化物、金属氮化物、含掺杂元素的氧化硅、含掺杂元素的氮化硅、含掺杂元素的氮氧硅中的一种或多种。其中，所述金属氧化物及所述金属氮化物中的 金属元素包括铝Al、钽Ta、铪Hf、锆Zr中的一种或多种。相应地，导电层402的材质包括含掺杂元素的硅单质或其他金属材料，其中，第一金属键合层30a和/或第二金属键合层30b靠近导电层402的一侧的材料的还原性高于所述其他金属材料的还原性。其中，所述其他金属材料是与所述金属氧化物或金属氮化物中的金属元素相对应的单质。所述其他金属材料包括铝Al、钽Ta、铪Hf、锆Zr中的一种或多种。
基于“导电层402含有与辅助键合层401中的正价态元素相同的元素”，可以理解的是，当辅助键合层401为金属氧化物或金属氮化物时，导电层402为所述其他金属材料。当辅助键合层401为含掺杂元素的氧化硅、含掺杂元素的氮化硅、含掺杂元素的氮氧硅时，导电层402为含掺杂元素的硅单质。
本申请一些实施方式中，辅助键合层401为铝的氧化物或者氮化物，此时第一金属键合层30a和/或第二金属键合层30b靠近导电层402的一侧的材料包括Ti、Cr、Ni中的至少一种。在另外一些实施方式中，辅助键合层401为钽、铪、锆的氧化物或氮化物，此时第一金属键合层30a和/或第二金属键合层30b靠近导电层402的一侧的材料包括Al、Ti、Cr、Ni中的至少一种。
图13C是图13A中辅助键合层401为两层时的另一种半导体结构的结构示意图，图13D是13B中辅助键合层401为两层时的另一种半导体结构的结构示意。其中，图13C所示的半导体结构可以采用上述图9所示的方法制备得到，图13D所示的半导体结构可以采用上述图12所示的方法制备得到。
如图13C、图13D所示，辅助键合层401为两层，具体包括层叠设置的第一辅助键合层401a和第二辅助键合层401b，且第一辅助键合层401a靠近第一绝缘键合层31a；导电层402包括层叠设置的第一导电层402a和第二导电层402b，且第一导电层402a靠近第一金属键合层30a。其中，第一导电层402a为与第一辅助键合层401a材质相同的材料经第一金属键合层30a还原得到，第二导电层402b为与第二辅助键合层401b材质相同的材料经第二金属键合层30b还原得到。相应地，第一导电层402a含有与第一辅助键合层401a中的正价态元素相同的元素，第一金属键合层30a靠近第一导电层402a的一侧的材料的还原性高于第一导电层402a材料的还原性；第二导电层402b含有与第二辅助键合层401b中的正价态元素相同的元素，第二金属键合层30b靠近第二导电层402b的一侧的材料的还原性高于第二导电层402b材料的还原性。
其中，当辅助键合层401为两层时，在制备该半导体结构100时，键合界面是同种材料，能更好地实现共价键合，提升键合强度，该半导体结构100的结构稳定性也就更高。可以理解地，若辅助键合层401为两层，辅助键合层401或导电层402的厚度可分别在1nm-200nm的范围内，优选在1nm-20nm的范围内。
本申请一些实施方式中，参见图13E、图13F、图13G、图13H，半导体结构100还包括第二器件功能层20a，其位于第一衬底10a与第一金属键合层30a之间，并与第一器件功能层20b对应设置。相应地，第二器件功能层20a位于第一衬底10a朝向第一器件功能层20b的一侧(即位于第一衬底10a的第一侧101a上)，多个第一金属键合层30a是间隔设置的，第一金属键合层30a设置在第二器件功能层20a背离第一衬底10a的一侧。
其中，图13E所示的半导体结构可以采用上述图5所示的方法制备得到(在图5的基础上去除第二衬底10b)，图13F所示的半导体结构可以采用上述图6所示的方法制备得到(在图6的基础上去除第二衬底10b)。图13F与图13E的区别仅在于：辅助键合层401、导电层402的层数不同。
在图13E及图13F中，第二器件功能层20a为一完整膜层，其全覆盖第一衬底10a的第一侧101a，第二器件功能层20a背离第一衬底10a的一侧表面间隔设置有多个第一金属键合层30a。由于相邻的两个第一金属键合层30a之间设有一个第一绝缘键合层31a，多个第一绝缘键合层31a也是间隔设置在第二器件功能层20a背离第一衬底10a的一侧。第一器件功能层20b与第二器件功能层20a对应地相对设置，类似地，第一器件功能层20b朝向第一衬底10a的一侧表面也间隔设置有多个第二金属键合层30b，相邻的两个第二金属键合层30b之间夹设有第二绝缘键合层31b。关于第一辅助键合层401a、第二辅助键合层401b、第一导电层402a、第二导电层402b等的分布位置可参见本申请上文对图13C、图13D的描述。
图13G所示的半导体结构可以采用上述图10所示的方法制备得到(在图10的基础上去除第二衬底10b)，图13H所示的半导体结构可以采用上述图11所示的方法制备得到(在图11的基础上去除第二衬底10b)。图13G与图13H的区别仅在于：辅助键合层401、导电层402的层数不同。
在图13G及图13H中，第一衬底10a的第一侧101a上间隔设置有多个第二器件功能层20a，每一第二器件功能层20a背离第一衬底10a的一侧表面都覆盖有一个第一金属键合层30a。这样多个第一金属键合层30a是在第一衬底10a的第一侧101a是间隔分布的。第二器件功能层20a与第一金属键合层30a构成一层叠结构，相邻的两个该层叠结构之间设有第一绝缘键合层31a，第一绝缘键合层31a的厚度等于第二器件功能层20a与第一金属键合层30a的厚度之和，以保证第一绝缘键合层31a背离第一衬底10a的表面 与第一金属键合层30a背离第一衬底10a的表面齐平，进而利于上述半导体结构的顺利制备及保持良好的稳定性。
图13G及图13H中，多个第二金属键合层30b与多个第一金属键合层30a一一相对设置、多个第二绝缘键合层31b与多个第一绝缘键合层31a一一相对设置。相应地，每一第二金属键合层30b背离第一衬底10a的一侧均覆盖有一个第一器件功能层20b，第一器件功能层20b与第二金属键合层30b构成另一层叠结构，相邻的两个该层叠结构之间夹设有第二绝缘键合层31b，第二绝缘键合层31b的厚度等于第一器件功能层20b与第二金属键合层30b的厚度之和，以保证第二绝缘键合层31b朝向第一衬底10a的表面与第二金属键合层30b朝向第一衬底10a的表面齐平，以利于上述半导体结构的顺利制备及保持良好的稳定性。
由上述描述可以获知，图13E至图13H所示的半导体结构同时含有两种器件功能层，可实现不同功能的器件功能层在一个半导体结构中的稳定集成。
此外，关于上述图13A至图13H的半导体结构100中各器件功能层，具体可以是一层或多层。在一些实施方式中，各器件功能层可以是包括基于三五族半导体材料(如GaN、GaAs、AlN、AlGaN、InN等)形成的外延堆叠结构。例如第二器件功能层20a可以包括层叠设置的第一缓冲层、第一n型掺杂层、第一有源层和第一p型掺杂层，且第一缓冲层靠近第一衬底10a；第一器件功能层20b包括层叠设置的第二缓冲层、第二n型掺杂层、第二有源层和第二p型掺杂层，且第二缓冲层远离第一衬底。这样的半导体结构特别适合制备光电器件，如无机电致发光器件、或光电探测器件等。
此外，上述图13A至图13H的半导体结构中均是以第一金属键合层30a与第二金属键合层30b完全对准时进行了示例，但从本申请前文关于图7、图8的描述可知，所述半导体结构中，各第一金属键合层30a与第二金属键合层30b也可以是不完全对准，例如发生一定对准偏移，但仍能保证该半导体结构的良好结构稳定性。
本申请实施例还提供了一种半导体器件，包括本申请实施例上述提供的半导体结构，或包括通过本申请实施例的上述晶圆键合方法得到的半导体结构。该半导体器件的结构稳定性高，可稳定地发挥其功能，市场竞争力强。
其中，本申请实施例的半导体结构可以直接作为半导体器件的一部分，也可以是将剥离下来应用于半导体器件中。该半导体器件包括但不限于光电器件、或功率器件(即电力电子器件)或射频器件等。在一些实施方式中，光电器件可以是电致发光器件，例如为发光二极管(Light Emitting Diode，LED)或激光二极管(Laser diode，LD)，具体可为氮化物基发光二极管，氮化物基量子阱激光二极管。在另一些实施方式中，光电器件还可以是光电探测器件，例如红外探测器、紫外探测器等。其中，功率器件、射频器件可以是晶体管，具体可以是场效应晶体管。
本申请实施例还提供了一种电子设备，该电子设备包括本申请实施例的上述半导体器件。
该电子设备可以是各种消费类电子产品，例如手机、平板电脑、笔记本电脑、移动电源、便携机，还可以是其它可穿戴或可移动的电子设备、电视机、影碟机、录像机、摄录机、收音机、收录机、组合音响、电唱机、激光唱机、家庭办公设备、家用电子保健设备，还可以是汽车等交通工具，或储能设备等。
应理解，本文中涉及的第一、第二以及各种数字编号仅为描述方便进行的区分，并不能用来限制本申请的范围。
本申请中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，“a,b,或c中的至少一项(个)”，或，“a,b,和c中的至少一项(个)”，均可以表示：a,b,c,a-b(即a和b),a-c,b-c,或a-b-c，其中a,b,c分别可以是单个，也可以是多个。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，部分或全部步骤可以并行执行或先后执行，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。

Claims (19)

  1. 一种半导体结构，其特征在于，包括：
    第一衬底及多个第一金属键合层，所述多个第一金属键合层间隔设置在所述第一衬底的一侧，相邻的两个所述第一金属键合层之间设有第一绝缘键合层；
    第一器件功能层和多个第二金属键合层，所述第二金属键合层设置在所述第一器件功能层朝向所述第一衬底的一侧，所述多个第一金属键合层与所述多个第二金属键合层一一相对设置，相邻的两个所述第二金属键合层之间设有第二绝缘键合层；其中，每个所述第一金属键合层和与之相对的所述第二金属键合层之间还设有导电层，相邻的所述导电层之间设有辅助键合层，所述辅助键合层的材质为绝缘化合物；所述导电层含有与所述辅助键合层中的正价态元素相同的元素，所述第一金属键合层和/或所述第二金属键合层靠近所述导电层一侧的材料的还原性高于所述导电层材料的还原性。
  2. 如权利要求1所述的半导体结构，其特征在于，所述导电层与所述第一金属键合层或与所述第二金属键合层接触的表面平整且无破损。
  3. 如权利要求1或2所述的半导体结构，其特征在于，所述第一金属键合层和/或所述第二金属键合层靠近所述导电层的界面含有与所述辅助键合层中的负价态元素相同的元素。
  4. 如权利要求1-3任一项所述的半导体结构，其特征在于，所述辅助键合层包括金属氧化物、金属氮化物、含掺杂元素的氧化硅、含掺杂元素的氮化硅、含掺杂元素的氮氧硅中的一种或多种；
    所述导电层的材质包括含掺杂元素的硅单质、或者与所述金属氧化物或所述金属氮化物中的金属元素相对应的单质。
  5. 如权利要求4所述的半导体结构，其特征在于，所述金属氧化物及所述金属氮化物中的金属元素包括铝、钽、铪、锆中的一种或多种。
  6. 如权利要求1-5任一项所述的半导体结构，其特征在于，所述第一金属键合层或所述第二金属键合层的材料包括Ti、Cr、Ni、Ta、Au、In、Sn、Ag、Al、W及其合金、TiN、TaN中的一种或多种。
  7. 如权利要求4-6任一项所述的半导体结构，其特征在于，所述辅助键合层为铝的氧化物或者氮化物，所述第一金属键合层或所述第二金属键合层靠近所述导电层的一侧的材料包括Ti、Cr、Ni中的至少一种。
  8. 如权利要求4-6任一项所述的半导体结构，其特征在于，所述辅助键合层为钽、铪、锆的氧化物或氮化物，所述第一金属键合层或所述第二金属键合层靠近所述导电层的一侧的材料包括Al、Ti、Cr、Ni中的至少一种。
  9. 如权利要求1-8任一项所述的半导体结构，其特征在于，所述导电层和所述辅助键合层分别为一层，所述导电层和所述辅助键合层的厚度分别在0.5nm-10nm的范围内。
  10. 如权利要求1-8任一项所述的半导体结构，其特征在于，所述辅助键合层包括层叠设置的第一辅助键合层和第二辅助键合层，且所述第一辅助键合层靠近所述第一绝缘键合层；所述导电层包括层叠设置的第一导电层和第二导电层，且所述第一导电层靠近所述第一金属键合层；其中，所述第一导电层为与所述第一辅助键合层材质相同的材料经所述第一金属键合层还原得到，所述第二导电层为与所述第二辅助键合层材质相同的材料经所述第二金属键合层还原得到。
  11. 一种半导体器件，其特征在于，包括如权利要求1-10任一项所述的半导体结构。
  12. 如权利要求11所述的半导体器件，其特征在于，所述半导体器件包括光电器件、功率器件、射频器件中的一种。
  13. 一种电子设备，其特征在于，所述电子设备包括如权利要求11或12所述的半导体器件。
  14. 一种晶圆键合方法，其特征在于，包括以下步骤：
    提供待键合的两个晶圆，每个所述晶圆包括衬底，两个所述衬底中至少一者的第一侧上设置有器件功能层；
    在所述两个晶圆上分别形成金属键合层，其中，所述金属键合层设置在所述衬底的第一侧；
    在带有所述金属键合层的两个晶圆中的至少一者上形成覆盖所述金属键合层的原始辅助键合层，得到处理后的两个晶圆；其中，所述原始辅助键合层为绝缘化合物；
    将所述处理后的两个晶圆进行贴合以使两个晶圆上的所述金属键合层相对设置，并对所述贴合后的两个晶圆进行热处理，以使夹在两晶圆中对应设置的所述金属键合层之间的所述原始辅助键合层被还原为导电层。
  15. 如权利要求14所述的晶圆键合方法，其特征在于，在所述贴合后，所述金属键合层与所述原始辅助键合层相接触的一侧的材料的还原性高于所述原始辅助键合层中的正价态元素所对应单质的还原性。
  16. 如权利要求14或15所述的晶圆键合方法，其特征在于，所述原始辅助键合层包括金属氧化物、金属氮化物、含掺杂元素的氧化硅、含掺杂元素的氮化硅、含掺杂元素的氮氧硅中的一种。
  17. 如权利要求14-16任一项所述的晶圆键合方法，其特征在于，所述原始辅助键合层的厚度在0.5nm-10nm的范围内。
  18. 如权利要求14-17任一项所述的晶圆键合方法，其特征在于，所述热处理的温度为100-200℃。
  19. 如权利要求14-18任一项所述的晶圆键合方法，其特征在于，所述金属键合层间隔形成在所述衬底的第一侧；
    在形成所述原始辅助键合层之前，所述晶圆键合方法还包括：
    在两个晶圆上相邻的所述金属键合层之间还分别形成绝缘键合层；其中，所述绝缘键合层背离所在衬底的一侧表面与所述金属键合层背离所在衬底的一侧表面齐平，且所述原始辅助键合层还覆盖所述绝缘键合层。
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CN110676216A (zh) * 2019-12-03 2020-01-10 长江存储科技有限责任公司 一种互连结构及其形成方法

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