CN109786315A - 形成半导体器件的方法以及封装件 - Google Patents

形成半导体器件的方法以及封装件 Download PDF

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Publication number
CN109786315A
CN109786315A CN201811132795.6A CN201811132795A CN109786315A CN 109786315 A CN109786315 A CN 109786315A CN 201811132795 A CN201811132795 A CN 201811132795A CN 109786315 A CN109786315 A CN 109786315A
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pipe core
component pipe
passive device
hole
component
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CN109786315B (zh
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胡致嘉
陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例涉及一种形成半导体器件的方法，包括将第一器件管芯与第二器件管芯接合。第二器件管芯位于第一器件管芯上方。在包括第一器件管芯和第二器件管芯的组合结构中形成无源器件。无源器件包括第一端和第二端。在第一器件管芯上方形成间隙填充材料，间隙填充材料包括位于第二器件管芯的相对侧上的部分。该方法还包括实施平坦化以露出第二器件管芯，其中，间隙填充材料的剩余部分形成隔离区，形成穿过隔离区的第一贯通孔和第二贯通孔，以电连接至第一器件管芯，并且形成电连接至无源器件的第一端和第二端的第一电连接件和第二电连接件。本发明的实施例还提供了另一种形成半导体器件的方法以及一种封装件。

Description

形成半导体器件的方法以及封装件
技术领域
本发明涉及半导体领域，并且更具体地，涉及形成半导体器件的方法以及封装件。
背景技术
集成电路的封装正在变得越来越复杂，其中，将多个器件管芯封装在同一封装件中以实现更多的功能。例如，已经将封装件结构开发成在同一封装件中包括诸如处理器和存储器立方体的多个器件管芯。封装件结构可以包括使用不同技术形成的器件管芯并且具有接合至同一器件管芯的不同功能，从而形成系统。这可以节省制造成本并优化器件性能。
发明内容
根据本发明的实施例，提供了一种形成半导体器件的方法，包括：将第一器件管芯与第二器件管芯接合，其中，第二器件管芯位于第一器件管芯上方，并且其中，第一无源器件形成在包括第一器件管芯和第二器件管芯的组合结构中，并且第一无源器件包括第一端和第二端；在第一器件管芯上方填充间隙填充材料，其中，间隙填充材料包括位于第二器件管芯的相对侧上的部分；实施平坦化以露出第二器件管芯，其中，间隙填充材料的剩余部分形成隔离区；形成穿过隔离区的第一贯通孔和第二贯通孔，以电连接至第一器件管芯；以及形成第一电连接件和第二电连接件，以电连接至第一无源器件的第一端和第二端。
根据本发明的实施例，提供了一种形成半导体器件的方法，包括：将第一器件管芯与第二器件管芯接合，其中，第一器件管芯中的第一金属焊盘接合至第二器件管芯中的第二金属焊盘；将第二器件管芯密封在隔离区中；在第二器件管芯和隔离区上方形成介电层；在介电层中形成第一无源器件；以及在介电层上方形成第一焊料区和第二焊料区，其中，第一焊料区和第二焊料区电连接至第一无源器件的相对端子。
根据本发明的实施例，提供了一种封装件，包括：第一器件管芯；第二器件管芯，位于第一器件管芯上方并且接合至第一器件管芯；隔离区，包围第二器件管芯；第一贯通孔和第二贯通孔，穿过隔离区以分别连接至第一器件管芯中的第一接合焊盘和第二接合焊盘；以及第一无源器件，包括分别连接至第一贯通孔和第二贯通孔的第一端子和第二端子。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图10是根据一些实施例的制造封装件的中间阶段的截面图。
图11至图13示出根据一些实施例的具有通过面至面接合而接合的器件管芯的封装件的截面图。
图14示出根据一些实施例的具有通过面至背接合而接合的器件管芯的封装件的截面图。
图15和图16示出根据一些实施例的示例性无源器件。
图17和图18示出根据一些实施例的形成在屏蔽结构中的示例性无源器件。
图19和图20示出根据一些实施例的封装件嵌入封装件的截面图。
图21示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上方”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例，提供了一种封装件及其形成方法。根据一些实施例示出形成封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图10示出根据本发明的一些实施例的形成封装件的中间阶段的截面图。图1至图10所示的步骤还在图21所示的工艺流程200中示意性地示出。
图1示出形成的封装组件2的截面图。根据本发明的一些实施例，封装组件2是包括诸如晶体管和/或二极管的有源器件22以及诸如电容器、电感器、电阻器等的可能无源器件的器件晶圆。封装组件2可以包括位于其中的多个芯片4，其中，示出一个芯片4。芯片4在下文中可选地称为(器件)管芯。根据本发明的一些实施例，器件管芯4是逻辑管芯，该管芯可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯、应用处理器(AP)管芯等。器件管芯4也可以是诸如动态随机存取存储器(DRAM)管芯或静态随机存取存储器(SRAM)管芯等的存储器管芯，或可以是其他类型的管芯。在后续的讨论中，将器件晶圆作为示例性封装组件2进行讨论。本发明的实施例还可以应用于诸如内插器晶圆的其他类型的封装组件。
根据本发明的一些实施例，示例性晶圆2包括半导体衬底20和在半导体衬底20的顶面处形成的部件。半导体衬底20可以由晶体硅、晶体锗、晶体硅锗和/或诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等的Ⅲ-Ⅴ族化合物半导体形成。半导体衬底20可以还是块状硅衬底或绝缘体上硅(SOI)衬底。浅沟槽隔离(STI)区(未示出)可以形成在半导体衬底20中以隔离半导体衬底20中的有源区。尽管未示出，但贯通孔可以形成为延伸到半导体衬底20中，并且贯通孔可以用于电互连位于晶圆2的相对侧上的部件。
根据本发明的一些实施例，晶圆2包括形成在半导体衬底20的顶面上的集成电路器件22。示例性集成电路器件22可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。在此未示出集成电路器件22的细节。根据可选实施例，晶圆2用于形成内插器，其中，衬底20可以是半导体衬底或介电衬底。
层间电介质(ILD)24形成在半导体衬底20上方并且填充位于集成电路器件22中的晶体管(未示出)的栅极堆叠件之间的间隔。根据一些示例性实施例，ILD 24由磷硅酸玻璃(PSG)、硼硅酸玻璃(BSG)、硼掺杂的磷硅酸玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等形成。可使用旋涂、可流动化学汽相沉积(FCVD)、化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)等来形成ILD 24。
接触插塞28形成在ILD 24中，并且用于将集成电路器件22电连接至上面的金属线34和通孔36。根据本发明的一些实施例，接触插塞28由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金和/或它们的多层的导电材料形成。接触插塞28的形成可以包括在ILD 24中形成接触开口，将导电材料填充到接触开口中，并且实施平坦化(诸如化学机械抛光(CMP)工艺)以使接触插塞28的顶面与ILD 24的顶面齐平。
位于ILD 24和接触插塞28上方的是互连结构30。互连结构30包括介电层32以及形成在介电层32中的金属线34和通孔36。在下文中，介电层32可选地称为金属间介电(IMD)层32。根据本发明的一些实施例，至少介电层32中的下部介电层由具有低于约3.0或低于约2.5的介电常数(k值)的低k介电材料形成。介电层32可以由Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的可选实施例，介电层32中的一些或全部由诸如氧化硅、碳化硅(SiC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)等非低k介电材料形成。根据本发明的一些实施例，介电层32的形成包括沉积含致孔剂的介电材料，以及然后实施固化工艺以驱除致孔剂，并且因此剩余的介电层32变成多孔的。在IMD层32之间形成可由碳化硅、氮化硅等形成的蚀刻停止层(未示出)，并且为了简明，未示出。
在介电层32中形成金属线(还包括金属焊盘)34和通孔36。下文中将处于相同层级的金属线34统称为金属层。根据本发明的一些实施例，互连结构30包括可为互连贯通孔36的多个金属层。金属线34和通孔36可以由铜或铜合金形成，并且它们也可以由其他金属形成。形成工艺可以包括单镶嵌和双镶嵌工艺。在示例性单镶嵌工艺中，首先在一个介电层32中形成沟槽，接着用导电材料填充沟槽。然后实施诸如CMP工艺的平坦化工艺以去除导电材料的比IMD层的顶面更高的多余部分，从而在沟槽中留下金属线。在双镶嵌工艺中，在IMD层中形成沟槽和通孔开口两者，其中，通孔开口位于沟槽下方并连接至沟槽。然后将导电材料分别填充到沟槽和通孔开口中以形成金属线和通孔。导电材料可以包括扩散阻挡件和位于扩散阻挡件上方的含铜金属材料。扩散阻挡件可以包括钛、氮化钛、钽、氮化钽等。
金属线34包括金属线34A，其有时称为顶部金属线。顶部金属线34A也统称为顶部金属层。各个介电层32A可以由诸如未掺杂的硅酸盐玻璃(USG)、氧化硅、氮化硅等的非低k介电材料形成。介电层32A也可以由低k介电材料形成，其可以从下面的IMD层32的类似材料中选择。
根据本发明的一些实施例，在顶部金属层上方形成介电层38、40和42。介电层38和42可以由氧化硅、氮氧化硅、碳氧化硅等形成。介电层40由与介电层42的介电材料不同的介电材料形成。例如，介电层42可以由氮化硅、碳化硅等形成。
在介电层38、40和42中形成通孔44和金属焊盘46A、46B和46C。相应工艺在图21所示的工艺流程中示出为步骤202。金属焊盘46A、46B和46C可以在下文中统称和单独地称为金属焊盘46。可以使用双镶嵌工艺形成通孔44和金属焊盘46，其中，双镶嵌工艺包括在介电层38和40中形成通孔开口，在介电层42中形成沟槽，以及用导电材料填充通孔开口和沟槽。实施诸如CMP工艺或机械研磨工艺的平坦化工艺以使介电层42和金属焊盘46的顶面齐平。填充导电材料可以包括沉积诸如氮化钛层、氮化钽层、钛层、钽层等的扩散阻挡件，并且在扩散阻挡件上方沉积含铜材料。
根据一些实施例，器件管芯4还可以包括形成在介电层38中的诸如铝或铝铜焊盘的金属焊盘。为了简明，未示出铝(铜)焊盘。
根据本发明的一些实施例，在晶圆2中没有诸如聚合物层的有机介电材料。有机介电层通常具有可以为10ppm/℃或更高的高的热膨胀系数(CTE)。这显著大于硅衬底(诸如衬底20)的CTE(其约为3ppm/℃)。因此，有机介电层倾向于引起晶圆2的翘曲。晶圆2中不包括有机材料有利地减小了晶圆2中的层之间的CTE失配，并且导致翘曲的减少。而且，在晶圆2中不包括有机材料使得可以形成细节距金属线(诸如图10中的66和70)和可能的高密度接合焊盘，并且导致布线能力的改善。
图1还示出形成无源器件48A，其中，在形成顶部金属层和金属焊盘46的同时形成无源器件48A。在整个说明书中，无源器件可以标识为48A、48B、48C、48D、48E、48F、48G(在图10至图14中示出)等，其可以统称为和单独地称为无源器件48。根据本发明的一些实施例，无源器件48A(以及任何其他无源器件48)可以是电容器、电感器、变压器、电阻器等。图15示出示例性无源器件48，其是电容器。电容器48包括电容器板160和164和电容器绝缘体162。电容器板160和164也分别称为电容器48的两个端子TB和TA。当电容器48A(图1)是具有图15所示结构的电容器时，顶部电容器板164与金属焊盘46(图1)同时形成，底部电容器板160与顶部金属层34A(图1)同时形成，并且电容器绝缘体是介电层38和40的部分。
图16示出示例性无源器件48，其是电感器。电感器可以包括底板166、顶板170和通孔168。通孔168将底板166和顶板170互连以形成电感器。当电容器48A(图1)是具有图16所示结构的电感器时，顶板170与金属焊盘46同时形成，底板166与顶部金属层34A同时形成，并且通孔168(图16)与通孔44(图1)同时形成。图16中的无源器件48还具有两个端子TA和TB。在整个说明书中，可以形成多个无源器件，并且可以通过参考图15和图16作为实例找到示例性结构和相应的层。应当理解，无源器件可以具有许多与图15和图16中所示的不同的结构。
图2示出器件管芯112与器件管芯4的接合。相应工艺在图21所示的工艺流程中示出为步骤204。根据本发明的一些实施例，器件管芯112是逻辑管芯，其可以是CPU管芯、MCU管芯、IO管芯、基带管芯或AP管芯等。器件管芯112还可以是存储器管芯。器件管芯112包括半导体衬底114，其可以是硅衬底。硅贯通孔(TSV)116(有时称为半导体贯通孔或贯通孔)形成为穿过半导体衬底114。TSV 116用于将形成在半导体衬底114的前侧(图示的底侧)上的器件和金属线连接至背侧。而且，器件管芯112包括用于连接至器件管芯112中的有源器件和无源器件的互连结构130。互连结构130包括金属线和通孔(未示出)。
器件管芯112可以包括介电层138和142以及位于介电层138和142之间的蚀刻停止层140。在层138、140和142中形成接合焊盘146和通孔144。根据本发明的一些实施例，管芯112不含诸如聚合物的有机介电材料。介电层138和142、接合焊盘146和通孔144的材料和形成方法可以类似于器件管芯4中的它们的对应部分，并且因此在此不重复细节。
可以通过混合接合来实现器件管芯112与管芯4的接合。例如，接合焊盘146通过金属-金属直接接合来接合至接合焊盘46A和46C。根据本发明的一些实施例，金属-金属直接接合是铜-铜直接接合。接合焊盘146的尺寸可以大于、等于或小于相应接合焊盘46A和46C的尺寸。尽管示出一个器件管芯112，但是可以存在接合至晶圆2的多个器件管芯112，并且间隙53留在相邻的器件管芯112之间。此外，介电层142通过电介质-电介质的接合而接合至表面介电层42，电介质至电介质接合可以是例如生成Si-O-Si接合的熔融接合。为了实现混合接合，首先通过将器件管芯112轻压在管芯4上而将器件管芯112预先接合至介电层42和接合焊盘46A。然后实施退火以引起接合焊盘46A/46C和相应的上面的接合焊盘146中的金属的相互扩散。
返回参考图2，根据一些实施例，在接合工艺之后，可以实施背侧研磨以将器件管芯112削薄至例如，厚度在约15μm和约30μm之间。图2示意性地示出虚线112-BS1，其中，虚线112-BS1是背侧研磨之前的器件管芯112的背面。背面112-BS2是在背侧研磨之后的器件管芯112的背面。通过削薄器件管芯112，减小间隙53的高宽比以实施间隙填充。否则，由于间隙53的高的高宽比，间隙填充可能存在困难。在背侧研磨之后，可以露出TSV 116。可选地，此时不露出TSV 116，并且当存在覆盖TSV 116的衬底114的薄层时停止背侧研磨。根据这些实施例，可以在图4所示的步骤中示出TSV 116。根据其中用于间隔填充的间隙53的高宽比不太高的其他实施例，跳过背侧研磨。
根据本发明的一些实施例，器件管芯112包括无源器件48B的部分。在器件管芯112和器件管芯4的接合之后，器件管芯4的金属焊盘接合至器件管芯112中的无源器件48B的部分，以形成整个无源器件48B。例如，当无源器件48B是电容器时，顶部电容器板可以是顶部金属层134A的部分。底部电容器板包括上部和底部，它们分别是器件管芯112和4的金属焊盘。当无源器件48B是电感器时，例如，如图16所示，顶板170(图16)将位于器件管芯112中的顶部金属层134A(图2)中，通孔168(图16)将位于器件管芯112中的介电层138和140(图2)中，并且每个底板166(图16)还包括上部和底部，它们分别是器件管芯112和4的金属焊盘。
在将器件管芯112接合至器件管芯4之后，形成电连接沟道52，每个包括堆叠的金属焊盘/线和通孔，从而使得形成在器件管芯112和4中的无源器件48可以连接至将在后续步骤中形成的上面的电连接件(例如焊接区)。形成屏蔽环50，每个屏蔽环包围电沟道52中的一个。当从图2所示结构的顶部观察时，屏蔽环50具有环的形状。屏蔽环50由金属线和通孔形成，其中，屏蔽环50可以是一些金属层和一些通孔层中的实心环(没有断口)。为了电连接至无源器件，屏蔽环50具有一些断口，从而允许金属线穿过断口以将无源器件48连接至电沟道52。连接至无源器件48的金属线通过介电材料与屏蔽环电绝缘。例如，图10示出从平面获得的截面图，其中，在该平面中，金属线穿过屏蔽环50中的断口以互连无源器件48B和电连接沟道52。图10中的虚线(示出屏蔽环50的部分)表示在所示平面的前面和后面的屏蔽环的部分。屏蔽环50电接地，从而使得无源器件(诸如48B)不会干扰器件管芯112和4中的其他器件，并且不受其干扰。
图3示出形成间隙填充层，其中，间隙填充层包括介电层56和下面的蚀刻停止层54。相应工艺在图21所示的工艺流程中示出为步骤206。可以使用诸如原子层沉积(ALD)或化学汽相沉积(CVD)的共形沉积方法来沉积介电层54。蚀刻停止层54由介电材料形成，该介电材料对器件管芯112的侧壁，介电层42的顶面和接合焊盘46B具有良好的粘附性。根据本发明的一些实施例，蚀刻停止层54由诸如氮化硅的含氮化物材料形成。例如，蚀刻停止层54可以是共形层，其中，水平部分的厚度T1A和垂直部分的厚度T1B彼此大致相等，例如，差值(T1A-T1B)的绝对值小于两个厚度T1A和T1B的约20％或约10％。
介电层56由与蚀刻停止层54的材料不同的材料形成。根据本发明的一些实施例，介电层56由氧化硅形成，由TEOS形成，并且还可以使用诸如碳化硅、氮氧化硅、碳氮氧化硅、PSG、BSG、BPSG等的其他介电材料。可以使用CVD、高密度等离子体化学汽相沉积(HDPCVD)、可流动CVD、旋涂等形成介电层56。介电层56完全填充剩余的间隙53(图2)。
参考图4，实施诸如CMP工艺或机械研磨工艺的平坦化工艺以去除间隙填充层54和56的多余部分，从而暴露器件管芯112。相应工艺还在图21所示的工艺流程中示出为步骤206。而且，暴露贯通孔116。层54和56的剩余部分统称为(间隙填充)隔离区58。
根据本发明的一些实施例，如图5所示，轻微蚀刻衬底114，从而使得贯通孔116具有从衬底114的顶面突出的顶部。形成介电层60，并轻微抛光以去除介电层60的覆盖贯通孔116的部分。介电层60可由氧化硅、氮化硅、氮氧化硅等形成。根据本发明的一些实施例，跳过贯通孔116的蚀刻和介电层60的形成。
图6示出蚀刻介电层60、56和54以形成开口61。相应工艺在图21所示的工艺流程中示出为步骤208。根据本发明的一些实施例，形成并图案化光刻胶(未示出)，并且使用图案化的光刻胶作为蚀刻掩模来蚀刻介电层60和56。因此形成开口61，并且开口61向下延伸至蚀刻停止层54，其中，蚀刻停止层54充当蚀刻停止层。根据本发明的一些实施例，层60和56包括氧化物，并且可以通过干蚀刻来实施蚀刻。蚀刻气体可以包括NF3和NH3的混合物或HF和NH3的混合物。接下来，对蚀刻停止层54进行蚀刻，从而使得开口61向下延伸至接合焊盘46B。根据本发明的一些实施例，蚀刻停止层54由氮化硅形成，并且使用干蚀刻来实施蚀刻。蚀刻气体可以包括CF4、O2和N2的混合物、NF3和O2的混合物、SF6、或SF6和O2的混合物等。
图7示出形成贯通孔64(包括64-1和64-2)和贯电介质通孔(TDV)65，从而填充开口61(图6)。相应工艺在图21所示的工艺流程中示出为步骤210。贯通孔64和TDV 65连接至接合焊盘46B。TDV 65电接地以形成屏蔽结构，从而使得无源器件(诸如图10中的48C)不会干扰器件管芯112和4中的其他器件，并且不会受到其干扰。根据本发明的一些实施例，贯通孔64和TDV 65的形成包括实施诸如电化学镀工艺或化学镀工艺的镀工艺。贯通孔64和TDV 65可以包括诸如钨、铝、铜等的金属材料。也可以在金属材料下面形成导电阻挡层(诸如钛、氮化钛、钽、氮化钽等)。实施诸如CMP的平坦化以去除镀的金属材料的多余部分，并且金属材料的剩余部分形成贯通孔64和TDV 65。贯通孔64和TDV 65可以具有大致直的和垂直的侧壁。而且，贯通孔64和TDV 65可以具有锥形轮廓，其顶部宽度略大于相应的底部宽度。
根据可选实施例，不在器件管芯112中预先形成TSV 116。相反，它们在形成隔离区58之后形成。例如，在形成开口61(图6)之前或之后，蚀刻器件管芯112以形成额外的开口(由所示的TSV 116占用)。可以同时填充器件管芯112中的额外的开口和开口61以形成TSV116和贯通孔64。所得到的贯通孔116可以具有比相应的下部更宽的上部，与图10中所示的相对。
参考图8，形成介电层62和63、再分布线(RDL)66和70以及通孔68。相应工艺在图21所示的工艺流程中示出为步骤212。根据本发明的一些实施例，介电层62和63由诸如氧化硅的氧化物、诸如氮化硅的氮化物等形成。尽管示出两个RDL层，但是可以存在多于两层的RDL。可以使用单和/或双镶嵌工艺来形成RDL 70，其包括蚀刻介电层以形成通孔开口和沟槽，将导电阻挡层沉积到开口中，镀诸如铜或铜合金的金属材料，并实施平坦化以去除金属材料的多余部分。在介电层60、62和63之间可以存在蚀刻停止层，其中，未示出蚀刻停止层。
图8示出无源器件48C，其也可以是电容器、电感器等，如图15和图16中的一些示例性实施例所示。在形成其他再分布线的同时形成无源器件48C。
图9示出形成钝化层、金属焊盘和上面的介电层。相应工艺在图21所示的工艺流程中示出为步骤214。在介电层63上方形成钝化层72。金属焊盘74形成在钝化层72上方，并且电连接至RDL 70。金属焊盘74可以是铝焊盘或铝铜焊盘，并且可以使用其他金属材料。根据本发明的一些实施例，不形成金属焊盘74，并且形成后钝化互连件(PPI)。钝化层72可以是单层或复合层，并且可以由无孔材料形成。根据本发明的一些实施例，钝化层72是包括氧化硅层(未单独示出)和位于氧化硅层上方的氮化硅层(未单独示出)的复合层。钝化层72也可以由诸如未掺杂的硅酸盐玻璃(USG)、氮氧化硅等的其他无孔的介电材料形成。接下来，形成聚合物层76，并且然后进行图案化以暴露金属焊盘74。聚合物层76可以由聚酰亚胺、聚苯并恶唑(PBO)等形成。
根据本发明的一些实施例，位于金属焊盘74下方的结构不含有机材料(诸如聚合物层)，从而使得用于形成位于金属焊盘74下方的结构的工艺可以采用用于形成器件管芯的工艺，并且制备具有细节距和线宽的细节距RDL(诸如66和70)是可能的。
参考图10，形成凸块下金属(UBM)77，并且UBM 77延伸到聚合物层76中以连接至金属焊盘74和PPI。相应工艺在图21所示的工艺流程中示出为步骤214。根据本发明的一些实施例，UBM 77中的每个包括阻挡层(未示出)和位于阻挡层上方的晶种层(未示出)。阻挡层可以是钛层、氮化钛层、钽层、氮化钽层或由钛合金或钽合金形成的层。晶种层的材料可以包括铜或铜合金。诸如银、金、铝、钯、镍、镍合金、钨合金、铬、铬合金及它们的组合的其他金属也可以包括在UBM 77中。
还如图10所示，形成电连接件78(包括78-1至78-5)。相应工艺还在图21所示的工艺流程中示出为步骤214。用于形成UBM 77和电连接件78的示例性形成工艺包括沉积毯式UBM层，形成并图案化掩模(其可以是光刻胶，未示出)，其中，通过掩模中的开口暴露毯式UBM层的部分。在形成UBM 77之后，将所示的封装件放置到镀溶液(未示出)中，并且实施镀步骤以在UBM 77上形成电连接件78。根据本发明的一些示例性实施例，电连接件78包括在后续回流工艺中不熔化的非焊料部分(未示出)。非焊料部分可以由铜形成，并且因此在下文中称为铜凸块，尽管它们可以由其他非焊料材料形成。电连接件78的每个还可以包括从镍层、镍合金、钯层、金层、银层或它们的多层中选择的覆盖层(未示出)。在铜凸块上方形成覆盖层。电连接件78还可包括焊帽。在前面的步骤中形成的结构称为复合晶圆80。对复合晶圆80实施管芯切锯(分割)步骤以将复合晶圆80分离成多个封装件82。相应工艺在图21所示的工艺流程中示出为步骤216。
如图10所示，每个无源器件48(诸如48A、48B、48C和图11至图13所示的无源器件48D至48G)包括两个端子(图15和图16中的TA和TB)，每个均电连接至电连接件78中的一个和TSV 116中的一个。例如，
图10示出示例性电连接件78-1、78-2、78-3、78-4和78-5，它们分别连接至TSV116-1、116-2、116-3、64-1和64-2。根据本发明的一些实施例，无源器件48A和48C中的每个电连接至贯通孔64-1和64-2，其中，贯通孔64-1和64-2进一步连接至电连接件78-4和78-5。应当理解，可以根据一些实施例形成无源器件48A和48C中的一个或两个。而且，当形成无源器件48A和48C时，无源器件48A和48C可以是不同类型的无源器件，以形成诸如LC电路、RC电路、RL电路的电路。无源器件48A和48C也可以是诸如电容器的相同类型的无源器件。这可能导致电容增加而不增加占用的芯片面积。类似地，诸如无源器件48B的其他无源器件也连接两个焊料区(诸如78-2和78-3)。
根据本发明的一些实施例，如图10所示，无源器件48形成在封装件82中，并且可以与或可以不与封装件82内的集成电路电连接并且被封装件82内的集成电路使用。每个无源器件48的两个端子连接在封装件82的外部。因此，无源器件48也具有与表面安装器件(SMD)相同的功能，也称为集成无源器件(IPD)。当封装件82与其他封装组件封装以形成更大的封装件时，其他封装组件可以直接通过焊料区和TSV访问和使用无源器件。
再次参考图10，TDV 65穿过隔离区58，并围绕无源器件48。图17示出TDV 65、贯通孔64-1和64-2以及无源器件48的示例性布局的顶视图。根据一些实施例，形成多个TDV 65以包围贯通孔64-1和64-2以及位于无源器件48正下方的区域(如图10所示)。例如，TDV 65彼此靠近，其中，距离D1小于约10μm。TDV 65电接地，并且因此形成屏蔽结构，从而用于防止无源器件48与位于由TDV 65包围的区域外部的集成电路器件之间的干扰。图18示出TDV 65的顶视图，其形成包围贯通孔64和位于无源器件48正下方的区域的完整环。
根据本发明的一些实施例，位于无源器件48正上方和正下方的区域没有诸如晶体管和二极管的有源器件，以便减少无源器件48和集成电路之间的干扰。因此，在器件管芯4和112中设计了一些排除区，并且在该排除区中没有设计有源器件。在器件管芯4的不与器件管芯112重叠的部分中堆叠无源器件和设计无源器件可以使所需的排除区最小化。
图11至图13示出用于形成无源器件48的一些可能位置。例如，图11示出无源器件48D位于金属层(其可以包括或可以不包括介电层32A中的顶部金属层)中，并且形成在隔离区58正下方。无源器件48D连接至贯通孔64-1和64-2和电连接件78-4和78-5。
图12示出无源器件48E和48F。无源器件48E包括器件管芯4和112的接合焊盘，接合该接合焊盘以形成无源器件48E的顶板。在器件管芯4中形成底板和通孔(如果有的话)。无源器件48F位于器件管芯4中的金属层(其可以包括或可以不包括介电层32A中的顶部金属层)中并且位于器件管芯112正下方，并且电连接至TSV 116-2和116-3。无源器件48D连接至贯通孔64-1和64-2以及电连接件78-4和78-5。无源器件48E包括器件管芯4和112的接合焊盘，接合该接合焊盘以形成无源器件48E的顶板。在器件管芯4中形成底板和通孔(如果有的话)。也在隔离区58正下方形成无源器件48D。
图13示出无源器件48G位于与器件管芯112重叠的RDL层中，并且电连接至TSV116-2和116-3。无源器件48G可以与无源器件48B重叠，并且可以与无源器件48B并联连接。应当理解，如图10至图13所示的无源器件48可以任何组合形成在同一芯片中。
图1至图13所示的封装件具有面至面的结构，其中，器件管芯112的正面面对器件管芯4的正面。图14示出面至背结构，其中，器件管芯112的正面面向器件管芯4的背面。器件管芯4包括延伸穿过衬底20和介电层17的TSV 16。示出无源器件48作为实例。应当理解，如图10至图13所示的无源器件48可以在适用时形成在图14中的封装件中，并且无源器件48的细节可以与图10至图13中的大致相同，并且在此不再重复。
图19和图20示出封装件82与其他封装组件的接合。相应工艺在图21所示的工艺流程中示出为步骤218。图19示出封装件84，其中嵌入了封装件82(图10至图14)。该封装件包括存储器立方体86，其中，存储器立方体86包括多个堆叠的存储器管芯(未单独示出)。将封装件82和存储器立方体86密封在密封材料88中，其中，密封材料88可以是模塑料。介电层和RDL(统称为89)位于封装件82和存储器立方体86下方并连接至封装件82和存储器立方体86。可以通过存储器立方体86或接合至封装件84的封装组件访问封装件82中的无源器件48。
图20示出叠层封装(PoP)结构90，其中，叠层封装(PoP)结构90具有与顶部封装件93接合的集成扇出(InFO)封装件92。InFO封装件90还包括嵌入其中的封装件82。将封装件82和贯通孔94密封在密封材料96中，其中，密封材料96可以是模塑料。封装件82接合至介电层和RDL，其统称为互连结构95。可以通过顶部封装件93或接合至封装件90的封装组件访问封装件82中的无源器件48(在图20中未示出，参见图10至图14)。
本发明的实施例具有一些优势特征。通过在封装件中集成无源器件，从而不需要SMD，并且节省了制造成本。在封装件中设计无源器件非常灵活。
根据本发明的一些实施例，一种方法包括将第一器件管芯与第二器件管芯接合，其中，第二器件管芯位于第一器件管芯上方，并且其中，在包括第一器件管芯和第二器件管芯的组合结构形成第一无源器件，并且第一无源器件包括第一端子和第二端子；在第一器件管芯上方填充间隙填充材料，其中，间隙填充材料包括位于第二器件管芯的相对侧上的部分；实施平坦化以露出第二器件管芯，其中，间隙填充材料的剩余部分形成隔离区；形成穿过隔离区的第一贯通孔和第二贯通孔，以电连接至第一器件管芯；以及形成第一电连接件和第二电连接件，以电连接至第一无源器件的第一端子和第二端子。在实施例中，第一电连接件和第二电连接件包括焊料区。在实施例中，第一无源器件的第一端子和第二端子分别连接至第一贯通孔和第二贯通孔。在实施例中，第一无源器件包括电容器。在实施例中，第一无源器件包括电感器。在实施例中，第一器件管芯包括第一金属焊盘，并且第二器件管芯包括接合至第一金属焊盘的第二金属焊盘，并且该接合还导致将形成第二无源器件，并且第一金属焊盘和第二金属焊盘组合形成第二无源器件的板。在实施例中，第一器件管芯包括屏蔽环的第一部分，并且第二器件管芯包括屏蔽环的第二部分，并且第一部分接合至屏蔽环的第二部分，并且其中，屏蔽环包围第二无源器件。在实施例中，第一器件管芯包括第三无源器件，其中，第三无源器件包括导电板，并且间隙填充材料与第三无源器件的导电板接触。在实施例中，该方法还包括在隔离区中形成多个额外的贯通孔，其中，多个额外的通孔电接地，并且多个额外的通孔组合环绕位于第一无源器件正下方的区域。
根据本发明的一些实施例，一种方法包括将第一器件管芯与第二器件管芯接合，其中，第一器件管芯中的第一金属焊盘接合至第二器件管芯中的第二金属焊盘；将第二器件管芯密封在隔离区中；在第二器件管芯和隔离区上方形成介电层；在介电层中形成第一无源器件；并且在介电层上方形成第一焊料区和第二焊料区，其中，第一焊料区和第二焊料区电连接至第一无源器件的相对端子。在实施例中，该方法还包括蚀刻隔离区以形成第一开口和第二开口；在第一开口和第二开口中分别形成第一贯通孔和第二贯通孔，其中，第一贯通孔和第二贯通孔电连接至第一无源器件的相对端子。在实施例中，第一无源器件与隔离区重叠，并且与第二器件管芯垂直未对准。在实施例中，第一无源器件与第二器件管芯重叠。在实施例中，通过混合接合将第一器件管芯接合至第二器件管芯，并且第一器件管芯的第一表面介电层接合至第二器件管芯的第二表面介电层。
根据本发明的一些实施例，一种封装件包括第一器件管芯；第二器件管芯，位于第一器件管芯上方并接合至第一器件管芯；隔离区，包围第二器件管芯；第一贯通孔和第二贯通孔，穿过隔离区以分别连接至位于第一器件管芯中的第一接合焊盘和第二接合焊盘；以及第一无源器件，包括分别连接至第一贯通孔和第二贯通孔的第一端子和第二端子。在实施例中，封装件还包括分别电连接至第一无源器件的第一端子和第二端子的第一焊料区和第二焊料区。在实施例中，封装件还包括位于第一器件管芯中的第二无源器件，其中，第二无源器件的端子连接至第一贯通孔和第二贯通孔。在实施例中，第二无源器件的顶板接触隔离区的底面，并且顶板的顶面与第一器件管芯和第二器件管芯之间的界面共面。在实施例中，通过混合接合将第一器件管芯和第二器件管芯接合，其中，第一器件管芯的接合焊盘接合至第二器件管芯的接合焊盘，并且第一器件管芯的第一表面介电层接合至第二器件管芯的第二表面介电层，并且第二无源器件包括位于第一表面介电层下面的板。在实施例中，封装件还包括位于隔离区中的屏蔽结构，其中，屏蔽结构包围第一贯通孔和第二贯通孔。
根据本发明的实施例，提供了一种形成半导体器件的方法，包括：将第一器件管芯与第二器件管芯接合，其中，所述第二器件管芯位于所述第一器件管芯上方，并且其中，第一无源器件形成在包括所述第一器件管芯和所述第二器件管芯的组合结构中，并且所述第一无源器件包括第一端和第二端；在所述第一器件管芯上方填充间隙填充材料，其中，所述间隙填充材料包括位于所述第二器件管芯的相对侧上的部分；实施平坦化以露出所述第二器件管芯，其中，所述间隙填充材料的剩余部分形成隔离区；形成穿过所述隔离区的第一贯通孔和第二贯通孔，以电连接至所述第一器件管芯；以及形成第一电连接件和第二电连接件，以电连接至所述第一无源器件的第一端和第二端。
根据本发明的实施例，所述第一电连接件和所述第二电连接件包括焊料区。
根据本发明的实施例，所述第一无源器件的第一端和第二端分别连接至所述第一贯通孔和所述第二贯通孔。
根据本发明的实施例，所述第一无源器件包括电容器。
根据本发明的实施例，所述第一无源器件包括电感器。
根据本发明的实施例，所述第一器件管芯包括第一金属焊盘，并且所述第二器件管芯包括接合至所述第一金属焊盘的第二金属焊盘，并且所述接合还导致将形成第二无源器件，并且所述第一金属焊盘和所述第二金属焊盘组合形成所述第二无源器件的板。
根据本发明的实施例，所述第一器件管芯包括屏蔽环的第一部分，并且所述第二器件管芯包括所述屏蔽环的第二部分，并且所述第一部分接合至所述屏蔽环的第二部分，并且其中，所述屏蔽环包围所述第二无源器件。
根据本发明的实施例，所述第一器件管芯包括第三无源器件，其中，所述第三无源器件包括导电板，并且所述间隙填充材料与所述第三无源器件的导电板接触。
根据本发明的实施例，还包括在所述隔离区中形成多个额外的贯通孔，其中，所述多个额外的贯通孔电接地，并且所述多个额外的贯通孔组合以包围位于所述第一无源器件正下方的区域。
根据本发明的实施例，提供了一种形成半导体器件的方法，包括：将第一器件管芯与第二器件管芯接合，其中，所述第一器件管芯中的第一金属焊盘接合至所述第二器件管芯中的第二金属焊盘；将所述第二器件管芯密封在隔离区中；在所述第二器件管芯和所述隔离区上方形成介电层；在所述介电层中形成第一无源器件；以及在所述介电层上方形成第一焊料区和第二焊料区，其中，所述第一焊料区和所述第二焊料区电连接至所述第一无源器件的相对端子。
根据本发明的实施例，还包括：蚀刻所述隔离区以形成第一开口和第二开口；以及在所述第一开口和所述第二开口中分别形成第一贯通孔和第二贯通孔，其中，所述第一贯通孔和所述第二贯通孔电连接至所述第一无源器件的相对端子。
根据本发明的实施例，所述第一无源器件与所述隔离区重叠，并且与所述第二器件管芯垂直未对准。
根据本发明的实施例，所述第一无源器件与所述第二器件管芯重叠。
根据本发明的实施例，通过混合接合将所述第一器件管芯接合至所述第二器件管芯，并且所述第一器件管芯的第一表面介电层接合至所述第二器件管芯的第二表面介电层。
根据本发明的实施例，提供了一种封装件，包括：第一器件管芯；第二器件管芯，位于所述第一器件管芯上方并且接合至所述第一器件管芯；隔离区，包围所述第二器件管芯；第一贯通孔和第二贯通孔，穿过所述隔离区以分别连接至所述第一器件管芯中的第一接合焊盘和第二接合焊盘；以及第一无源器件，包括分别连接至所述第一贯通孔和所述第二贯通孔的第一端子和第二端子。
根据本发明的实施例，还包括：第一焊料区和第二焊料区，分别电连接至所述第一无源器件的第一端子和第二端子。
根据本发明的实施例，还包括：第二无源器件，位于所述第一器件管芯中，其中，所述第二无源器件的端子连接至所述第一贯通孔和所述第二贯通孔。
根据本发明的实施例，所述第二无源器件的顶板接触所述隔离区的底面，并且所述顶板的顶面与位于所述第一器件管芯和所述第二器件管芯之间的界面共面。
根据本发明的实施例，通过混合接合将所述第一器件管芯接合至所述第二器件管芯，其中，所述第一器件管芯的接合焊盘接合至所述第二器件管芯的接合焊盘，并且所述第一器件管芯的第一表面介电层接合至所述第二器件管芯的第二表面介电层，并且所述第二无源器件包括位于所述第一表面介电层下方的板。
根据本发明的实施例，还包括位于所述隔离区中的屏蔽结构，其中，所述屏蔽结构包围所述第一贯通孔和所述第二贯通孔。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
将第一器件管芯与第二器件管芯接合，其中，所述第二器件管芯位于所述第一器件管芯上方，并且其中，第一无源器件形成在包括所述第一器件管芯和所述第二器件管芯的组合结构中，并且所述第一无源器件包括第一端和第二端；
在所述第一器件管芯上方填充间隙填充材料，其中，所述间隙填充材料包括位于所述第二器件管芯的相对侧上的部分；
实施平坦化以露出所述第二器件管芯，其中，所述间隙填充材料的剩余部分形成隔离区；
形成穿过所述隔离区的第一贯通孔和第二贯通孔，以电连接至所述第一器件管芯；以及
形成第一电连接件和第二电连接件，以电连接至所述第一无源器件的第一端和第二端。
2.根据权利要求1所述的方法，其中，所述第一电连接件和所述第二电连接件包括焊料区。
3.根据权利要求1所述的方法，其中，所述第一无源器件的第一端和第二端分别连接至所述第一贯通孔和所述第二贯通孔。
4.根据权利要求1所述的方法，其中，所述第一无源器件包括电容器。
5.根据权利要求1所述的方法，其中，所述第一无源器件包括电感器。
6.根据权利要求1所述的方法，其中，所述第一器件管芯包括第一金属焊盘，并且所述第二器件管芯包括接合至所述第一金属焊盘的第二金属焊盘，并且所述接合还导致将形成第二无源器件，并且所述第一金属焊盘和所述第二金属焊盘组合形成所述第二无源器件的板。
7.根据权利要求6所述的方法，其中，所述第一器件管芯包括屏蔽环的第一部分，并且所述第二器件管芯包括所述屏蔽环的第二部分，并且所述第一部分接合至所述屏蔽环的第二部分，并且其中，所述屏蔽环包围所述第二无源器件。
8.根据权利要求1所述的方法，其中，所述第一器件管芯包括第三无源器件，其中，所述第三无源器件包括导电板，并且所述间隙填充材料与所述第三无源器件的导电板接触。
9.一种形成半导体器件的方法，包括：
将第一器件管芯与第二器件管芯接合，其中，所述第一器件管芯中的第一金属焊盘接合至所述第二器件管芯中的第二金属焊盘；
将所述第二器件管芯密封在隔离区中；
在所述第二器件管芯和所述隔离区上方形成介电层；
在所述介电层中形成第一无源器件；以及
在所述介电层上方形成第一焊料区和第二焊料区，其中，所述第一焊料区和所述第二焊料区电连接至所述第一无源器件的相对端子。
10.一种封装件，包括：
第一器件管芯；
第二器件管芯，位于所述第一器件管芯上方并且接合至所述第一器件管芯；
隔离区，包围所述第二器件管芯；
第一贯通孔和第二贯通孔，穿过所述隔离区以分别连接至所述第一器件管芯中的第一接合焊盘和第二接合焊盘；以及
第一无源器件，包括分别连接至所述第一贯通孔和所述第二贯通孔的第一端子和第二端子。
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