TWI812961B - 封裝及其製造方法 - Google Patents

封裝及其製造方法 Download PDF

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TWI812961B
TWI812961B TW110121585A TW110121585A TWI812961B TW I812961 B TWI812961 B TW I812961B TW 110121585 A TW110121585 A TW 110121585A TW 110121585 A TW110121585 A TW 110121585A TW I812961 B TWI812961 B TW I812961B
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Taiwan
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die
capacitor
layer
dielectric layer
aluminum
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TW110121585A
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TW202232609A (zh
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余振華
蔡仲豪
王垂堂
陳頡彥
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種封裝的製造方法，包含將電容器晶 粒接合至裝置晶粒。裝置晶粒包含：第一半導體基底；主動裝置，位於第一半導體基底的表面處；多個低k介電層；第一介電層，位於多個低k介電層中的頂部低k介電層上方且接觸頂部低k介電層；以及多個第一接合墊，位於第一介電層中。電容器晶粒包含：第二介電層，接合至第一介電層；多個第二接合墊，位於第二介電層中且接合至多個第一接合墊；以及電容器，電耦接至多個第二接合墊。在電容器晶粒接合至裝置晶粒之後，含鋁接墊形成於電容器晶粒上方且電耦接至裝置晶粒。聚合物層形成於含鋁接墊上方。

Description

封裝及其製造方法
本發明實施例是有關於一種封裝及其製造方法。
高效能邏輯電路通常需要高密度電容器以減少同步切換雜訊及減小電壓降。當前使用的電容器的密度通常較低，且無法滿足高效能封裝的電源完整性的要求。
根據本發明的一些實施例，一種封裝的製造方法包括以下步驟。將電容器晶粒接合至裝置晶粒，其中裝置晶粒包括：第一半導體基底；主動裝置，位於第一半導體基底的表面處；多個低k介電層；第一介電層，位於多個低k介電層中的頂部低k介電層上方且接觸所述頂部低k介電層；以及多個第一接合墊，位於第一介電層中。電容器晶粒包括：第二介電層，接合至第一介電層；多個第二接合墊，位於第二介電層中，其中多個第二接合墊接合至多個第一接合墊；以及電容器，電耦接至多個第二接合墊。在電容器晶粒接合至裝置晶粒之後，在電容器晶粒上方形成含鋁接墊，其中含鋁接墊電耦接至裝置晶粒。在含鋁接墊上方形成聚合物層。
根據本發明的一些實施例，一種封裝包括裝置晶粒、電容器晶粒、含鋁接墊以及聚合物層。裝置晶粒包括：半導體基底；主動裝置，位於半導體基底的表面處；多個低k介電層；第一介電層，位於多個低k介電層中的頂部低k介電層上方且接觸所述頂部低k介電層；以及多個第一接合墊，位於第一介電層中。電容器晶粒包括：第二介電層，接合至第一介電層；多個第二接合墊，位於第二介電層中，其中多個第二接合墊接合至多個第一接合墊；以及電容器，電耦接至多個第二接合墊。含鋁接墊位於電容器晶粒上方，其中含鋁接墊電耦接至裝置晶粒。聚合物層位於含鋁接墊上方。
根據本發明的一些實施例，一種封裝包括裝置晶粒、電容器晶粒、多個含鋁接墊、聚合物層以及多個電連接件。裝置晶粒包括第一半導體基底；多個第一介電層；以及多個第一鑲嵌結構，位於多個第一介電層中。電容器晶粒包括第二半導體基底；多個第二介電層；以及多個第二鑲嵌結構，位於多個第二介電層中，其中多個第二鑲嵌結構的底部表面與多個第二介電層中的對應者的底部表面共面，其中多個第二介電層中的底部層接合至多個第一介電層中的頂部層。多個含鋁接墊位於電容器晶粒上方，其中多個含鋁接墊電耦接至裝置晶粒。聚合物層包括覆蓋多個含鋁接墊中的每一者的邊緣部分的一部分。多個電連接件位於多個含鋁接墊上方且電連接至多個含鋁接墊。
2:晶圓
4:晶片
20,44,162:半導體基底
22:積體電路裝置
24:層間介電質
26,46,70,158:穿孔
27,106,164:記憶體裝置
28:接觸插塞
30:內連線結構
32,51,52,56,74,75,76,116:介電層
34:金屬線
36:通孔
38:表面介電層
40A,40B,50:接合墊
42:電容器晶粒
44-BS1,44-BS2:虛線
48:內連線結構
49,49':電容器
49A,49C:電容器電極
49B:電容器絕緣體
53:金屬線及通孔
54:蝕刻終止層
58:間隙填充區
66:開口
68:光阻
72,73,114:重佈線
76,82:鈍化層
80:金屬接墊
84,88:聚合物層
86:後鈍化內連線
90:凸塊下金屬
92:電連接件
94:重建構晶圓
96,150:封裝
102:支撐基底
110:扇出封裝
112,166:包封體
118:扇出重佈線結構
126:封裝基底
128:底部填充劑
140,152:記憶體晶粒
142:電容器晶圓
143:記憶體
154:熱界面材料
156:散熱器
200:製程流程
202,204,206,208,210,212,214,216,218:製程
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本 揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意增加或減小各種特徵之尺寸。
圖1至圖12示出根據一些實施例的形成具有深分割電容器的封裝的中間階段的橫截面圖。
圖13及圖14示出根據一些實施例的具有深分割電容器的封裝的橫截面圖。
圖15至圖20示出根據一些實施例的在支撐基底上形成具有深分割電容器的封裝的中間階段的橫截面圖。
圖21至圖28示出根據一些實施例的具有深分割電容器的封裝的橫截面圖。
圖29示出根據一些實施例的用於形成具有深分割電容器的封裝的製程流程。
以下揭露提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及佈置的特定實例以簡化本揭露。當然，這些組件及佈置僅為實例，且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可形成於第一特徵與第二特徵之間使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複參考標號及/或字母。此重複是出於簡單及清晰目的，且本身並不指示所論述的各種實施例及/或配置之間的關係。
此外，為易於描述，本文中可使用諸如「在......之下」、「在......下方」、「下部」、「在......上方」、「上部」以及類似者的空間相對術語來描述如諸圖中所示出的一個元件或特徵相對於另一(些)元件或特徵的關係。除了諸圖中所描繪的定向以外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
本發明實施例提供一種具有深分割電容器的封裝及其形成方法。根據本揭露的一些實施例，高密度電容器(其可為深溝渠電容器)形成於諸如晶粒的封裝組件上，所述封裝組件可包含或可不包含基底。含有電容器的封裝組件直接接合至裝置晶粒(其可為邏輯晶粒)的下部重佈線層，使得高密度電容器可由裝置晶粒存取。裝置晶粒的上部層在接合之後形成且形成於電容器晶粒上方。高密度電容器可由裝置晶粒中的電源輸送網路使用。藉由此設計，可在不干擾邏輯晶粒的設計的情況下達成極高的電容器密度。又，由於電容器晶粒相當於插入在裝置晶粒的下部層與上部層之間，故電容器晶粒中的電容器具有通向裝置晶粒中的裝置的較短路徑。本文中所論述的實施例將提供使得能夠製造或使用本揭露的主體的實例，且所屬領域中具有通常知識者將易於理解在保持於不同實施例的所涵蓋範疇內的同時可進行的修改。貫穿各種視圖及說明性實施例，相同的參考標號用於指代相同元件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1至圖12示出根據本揭露的一些實施例的形成具有深 分割電容器的封裝的中間階段的截面視圖。對應製程亦示意性地反映於如圖29中所展示的製程流程200中。
圖1示出在晶圓2形成時的截面視圖。相應製程在圖29中所展示的製程流程中示出為製程202。根據本揭露的一些實施例，晶圓2為裝置晶圓，其包含諸如電晶體及/或二極體的主動裝置，且可能包含諸如電容器、電感器、電阻器或類似者的被動裝置。裝置晶圓2可在其中包含多個晶片4，其中示出晶片4中的一個。晶片4在下文中被替代地稱作(裝置)晶粒。根據本揭露的一些實施例，裝置晶粒4為邏輯晶粒，其可為中央處理單元(Central Processing Unit；CPU)晶粒、圖形處理單元(Graphics Processing Unit；GPU)、Xtreme處理單元(Xtreme Processing Unit；XPU)、微控制單元(Micro Control Unit；MCU)晶粒、基頻(BaseBand；BB)晶粒、應用處理器(Application processor；AP)晶粒或類似者。
根據本揭露的一些實施例，實例晶圓2包含半導體基底20及形成於半導體基底20的頂部表面處的特徵。半導體基底20可由結晶矽、結晶鍺、結晶矽鍺及/或III-V化合物半導體形成，所述III-V化合物半導體諸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP以及類似者。半導體基底20亦可為塊狀矽基底或絕緣層上矽(Silicon-On-Insulator，SOI)基底。淺溝渠隔離(Shallow Trench Isolation，STI)區(圖中未示)可形成於半導體基底20中，以隔離半導體基底20中的主動區。儘管圖中未示，但穿孔可形成為延伸至半導體基底20中，其中穿孔用於將晶圓2的相對側上的特徵相互電耦接。
根據本揭露的一些實施例，晶圓2包含積體電路裝置22，其形成於半導體基底20的頂部表面上。實例積體電路裝置22可包含互補金屬氧化物半導體(Complementary Metal-Oxide Semiconductor；CMOS)電晶體、電阻器、電容器、二極體及/或類似者。本文中並未說明積體電路裝置22的細節。根據替代實施例，晶圓2用於形成插入件(interposer)，其中基底20可為半導體基底或介電基底。
層間介電質(Inter-Layer Dielectric；ILD)24形成於半導體基底20上方，且填充積體電路裝置22中的電晶體的閘極堆疊(圖中未示)之間的空間。根據一些實例實施例，ILD 24由磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、氟摻雜矽酸鹽玻璃(FSG)、原矽酸四乙酯(TEOS)或類似者形成。ILD 24可使用旋塗、可流動化學氣相沉積(Flowable Chemical Vapor Deposition；FCVD)、化學氣相沉積(Chemical Vapor Deposition；CVD)或類似方法形成。根據本揭露的一些實施例，ILD 24使用沉積方法形成，所述沉積方法諸如電漿增強式化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition；PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition；LPCVD)或類似方法。
接觸插塞28形成於ILD 24中，且用於將積體電路裝置22電連接至上覆金屬線及通孔。根據本揭露的一些實施例，接觸插塞28由下列各者中選出的導電材料形成：鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金及/或其多層。接觸插塞28的形成可包含：在ILD 24中形成接觸開口；將導電材料填充至接觸開口中； 以及執行平坦化(諸如化學機械研磨(Chemical Mechanical Polish，CMP)製程)，以使接觸插塞28的頂部表面與ILD 24的頂部表面齊平。
ILD 24及接觸插塞28上方配置有內連線結構30。內連線結構30包含形成於介電層32中的金屬線34及通孔36。介電層32在下文中替代地稱作金屬間介電(Inter-Metal Dielectric，IMD)層32。根據本揭露的一些實施例，介電層32中的至少一些或全部由低k介電材料形成，所述低k介電材料具有小於約3.0、約2.5或甚至更小的介電常數(k值)。介電層32可由黑鑽(Black Diamond)(所應用材料的註冊商標)、含碳低k介電材料、三氧化矽烷(HSQ)、甲基矽倍半氧烷(MSQ)或類似者形成。根據本揭露的替代實施例，介電層32中的一些或全部由非低k介電材料形成，所述非低k介電材料諸如氧化矽、碳化矽(SiC)、碳氮化矽(SiCN)、碳氮氧化矽(SiOCN)或類似者。根據本揭露的一些實施例，介電層32的形成包含：沉積含致孔劑的介電材料；以及接著執行固化製程以去除致孔劑，且因此留下的介電層32為多孔的。可由碳化矽、氮化矽或類似者形成的蝕刻終止層(圖中未示)形成於IMD層32之間，且為簡單起見並未展示。
金屬線34及通孔36形成於介電層32中。處於同一層級處的金屬線34在下文中共同稱為金屬層。根據本揭露的一些實施例，內連線結構30包含經由通孔36內連的多個金屬層。金屬線34及通孔36可由銅或銅合金形成，且其亦可由其他金屬形成。形成製程可包含單鑲嵌製程及雙鑲嵌製程。在實例單鑲嵌製程中，首先在介電層32中的一者中形成溝渠，接著用導電材料填充溝渠。 接著執行諸如CMP製程的平坦化製程，以移除導電材料的高於IMD層的頂部表面的多餘部分，從而在溝渠中留下金屬線。在雙鑲嵌製程中，在IMD層中形成溝渠及通孔開口兩者，其中通孔開口在溝渠之下且連接至溝渠。接著將導電材料填充至溝渠及通孔開口中以分別形成金屬線及通孔。導電材料可包含擴散障壁層以及擴散障壁層上方的含銅金屬材料。擴散障壁層可包含鈦、氮化鈦、鉭、氮化鉭或類似者。
金屬線34及通孔36可包含電源輸送網路(Power Delivery Network；PDN)及訊號輸送網路。電源輸送網路可包含電源平面，其為用於輸送VDD及VSS且用以減小電壓降的大型金屬板。電源輸送網路可連接至隨後接合的電容器晶粒42(圖12)中的高密度電容器49以減少同步切換雜訊(simultaneous switching noise；SSN)且減小電壓降。
圖1進一步示出根據本揭露的一些實施例的表面介電層38。表面介電層38可由諸如氧化矽的非低k介電材料形成，且可與根據一些實施例的下伏低k介電層32實體接觸。表面介電層38替代地稱作鈍化層，此是因為其具有將下伏低k介電層(若存在)隔離以免受有害化學品及濕氣不利影響的功能。表面介電層38可具有單層結構或包含多於一個層的複合結構，其可由氧化矽、氮化矽、未摻雜矽酸鹽玻璃(Undoped Silicate Glass，USG)或類似者形成。裝置晶粒4中可不含有含鋁接墊及有機材料(諸如聚合物)。
接合墊40A及接合墊40B形成於表面介電層38中。根據本揭露的一些實施例，接合墊40A及接合墊40B經由單鑲嵌製程形成，且亦可包含障壁層及形成於障壁層上方的含銅材料。根據 本揭露的替代實施例，接合墊40A及接合墊40B可經由雙鑲嵌製程形成。對頂部表面介電層38及接合墊40A、40B進行平坦化以使得其頂部表面共面，此可由於在形成接合墊40A、40B時進行的CMP而產生。
圖2示出包含電容器49於其中的電容器晶粒42的截面視圖。根據一些實施例，電容器晶粒42包含半導體基底44，其可為矽基底或可由其他半導體材料形成。有時被稱作半導體穿孔或穿孔的矽穿孔(Through-Silicon Via，TSV)46形成為延伸至半導體基底44中。又，電容器晶粒42包含用於將電容器晶粒42中的金屬線及深溝渠電容器49連接至接合墊50的內連線結構48。內連線結構48包含介電層51以及金屬線及通孔53。金屬線及通孔53以及接合墊50可使用鑲嵌製程形成。
電容器49可包含電容器電極49A及電容器電極49C以及位於電容器電極49A與電容器電極49C之間的電容器絕緣體49B。電極49A及電極49C以及電容器絕緣體49B可延伸至基底44中，使得電容器49可為深溝渠電容器，且電容密度(每單位面積的電容)較高。此外，可存在多個電容器絕緣體，其位於多個電容器絕緣體之間以形成多個子電容器。子電容器並聯連接以形成積體電容器。根據一些實施例，電容器晶粒42中的電容密度可大於約100奈法/平方毫米、大於約500奈法/平方毫米或大於約1,000奈法/平方毫米，且可介於約250奈法/平方毫米與約5,000奈法/平方毫米之間。較大電容密度值有益於形成一些應用所需的具有大電容值的電容器。
電容器晶粒42包含位於電容器晶粒42的所示出頂部表 面處的接合墊50及介電層52。接合墊50的頂部表面與介電層52的頂部表面實質上共面。根據本揭露的一些實施例，電容器晶粒42不含諸如電晶體及二極體的主動裝置。根據一些實施例，電容器49中的每一者具有兩個端子，每一端子連接至接合墊50中的一個。
接著，多個電容器晶粒42接合至晶圓2，如圖3中所展示。相應製程在圖29中所展示的製程流程中示出為製程204。可經由混合接合來達成接合。舉例而言，經由金屬至金屬直接接合將接合墊50接合至接合墊40A。根據本揭露的一些實施例，金屬至金屬直接接合為銅至銅直接接合。此外，介電層52經由熔融接合，例如藉由所產生的Si-O-Si鍵而接合至表面介電層38。
為達成混合接合，首先藉由將電容器晶粒42輕輕抵壓在晶粒4上而將電容器晶粒42預接合至介電層38及接合墊40A。儘管示出兩個電容器晶粒42，但可執行晶圓層級混合接合，並且與所示出的包含電容器晶粒42的晶粒群組相同的多個裝置晶粒群組經預接合且排列為列及行。
在預接合所有電容器晶粒42之後，執行退火製程以使得接合墊40A及對應上覆接合墊50中的金屬相互擴散。根據一些實施例，退火溫度可在約200℃與約400℃之間的範圍內，且可在約300℃與約400℃之間的範圍內。根據一些實施例，退火時間可在約1.5小時與約3.0小時之間的範圍內，且可在約1.5小時與約2.5小時之間的範圍內。
介電層38亦接合至介電層52，其間形成鍵。舉例而言，介電層38及介電層52中的一者中的原子(諸如氧原子)與介電層38及介電層52中的另一者中的原子(諸如矽原子)形成化學 鍵或共價鍵。介電層38與介電層52之間的所得接合為介電質至介電質接合，且可為熔融接合。相鄰電容器晶粒42之間留下間隙53。
參考圖4，可執行背側研磨製程以薄化電容器晶粒42。相應製程在圖29中所展示的製程流程中示出為製程206。亦可跳過此製程，且因此，圖29中的製程206展示為虛線以表示可執行或可不執行此製程。圖4示意性地示出虛線44-BS1及實線44-BS2，所述虛線44-BS1及實線44-BS2分別為在背側研磨製程之前及之後的電容器晶粒42的背表面。經由薄化電容器晶粒42，相鄰電容器晶粒42之間的間隙53的縱橫比減小以便執行間隙填充。此外，歸因於間隙53的原本較高縱橫比，間隙填充可為困難的。根據一些實施例，在背側研磨之後，並未露出TSV 46，也就是說，可在TSV 46被較薄基底層覆蓋時就停止背側研磨。根據替代實施例，在研磨之後露出TSV 46。
圖5示出間隙填充層的形成。相應製程在圖29中所展示的製程流程中示出為製程208。根據本揭露的一些實施例，間隙填充層包含蝕刻終止層54及介電層56，所述介電層56位於蝕刻終止層54上方且接觸蝕刻終止層54。可使用諸如原子層沉積(Atomic Layer Deposition，ALD)或化學氣相沉積(CVD)的共形沉積製程來沉積蝕刻終止層54。因此，蝕刻終止層54可為共形層，例如，其中水平部分的厚度及垂直部分的厚度實質上彼此相等，例如具有小於約20%的變化。蝕刻終止層54由介電材料形成，所述介電材料對電容器晶粒42的側壁以及介電層38及接合墊40B的頂部表面具有良好的黏著力。根據本揭露的一些實施例，蝕刻終 止層54由含氮化物材料形成或包括含氮化物材料，所述含氮化物材料諸如氮化矽。
介電層56由與蝕刻終止層54的材料不同的材料形成。根據本揭露的一些實施例，介電層56由氧化矽形成或包括氧化矽，但亦可使用其他介電材料，諸如碳化矽、氮氧化矽、碳氮氧化矽或類似者。介電層56可為共形層(其中水平部分及垂直部分的厚度實質上彼此相等)或可為非共形層。
參考圖6，執行諸如CMP製程或機械研磨製程的平坦化製程，以移除間隙填充層56及蝕刻終止層54的多餘部分，使得電容器晶粒42暴露且接著進行研磨。相應製程在圖29中所展示的製程流程中示出為製程210。又，暴露穿孔46。蝕刻終止層54及間隙填充層56的剩餘部分共同地稱作(隔離)間隙填充區58。
圖7示出蝕刻間隙填充區58以形成開口66。相應製程在圖29中所展示的製程流程中示出為製程212。根據本揭露的一些實施例，形成並圖案化光阻68，且使用經圖案化光阻68作為蝕刻罩幕來蝕刻介電層56。開口66因此形成為向下延伸至蝕刻終止層54。接著，進一步對蝕刻終止層54進行蝕刻，使得開口66向下延伸至經由開口66暴露的接合墊40B。蝕刻製程亦可為乾式蝕刻製程或濕式蝕刻製程。根據本揭露的一些實施例，蝕刻終止層54由氮化矽形成，且使用乾式蝕刻來執行蝕刻。蝕刻氣體可包含：CF4、O2與N2的混合物；NF3與O2的混合物；SF6；或SF6與O2的混合物。隨後移除光阻68。
圖8示出形成穿孔70，其填充開口66(圖7)且連接至接合墊40B。相應製程在圖29中所展示的製程流程中示出為製程 214。根據本揭露的一些實施例，形成穿孔70包含執行鍍覆製程，諸如電化學鍍覆製程或無電鍍覆製程。穿孔70可包含金屬材料，諸如鎢、鋁、銅或類似者。亦可在金屬材料之下形成導電障壁層(諸如鈦、氮化鈦、鉭、氮化鉭或類似者)。執行諸如CMP製程的平坦化製程，以移除經鍍覆金屬材料的多餘部分，且金屬材料的剩餘部分形成穿孔70。穿孔70可具有實質上筆直且垂直的側壁。並且，穿孔70可具有逐漸變窄的輪廓，其中頂部寬度略微大於各別底部寬度。
如圖8中所展示，根據其中在接合之前預形成TSV 46的一些實施例，TSV 46可具有小於各別底部寬度的上部寬度。相反，當並未預形成TSV 46時，例如在形成間隙填充區58之後，可蝕刻電容器晶粒42以在形成開口66之前或之後形成額外開口(由所示出的TSV 46佔據)。可同時填充電容器晶粒42中的所述額外開口及開口66，以形成TSV 46以及穿孔70。所得穿孔46可具有寬於各別下部部分的上部部分。
參考圖9，形成背側重佈線(redistribution line，RDL)72及介電層74。相應製程在圖29中所展示的製程流程中示出為製程216。根據本揭露的一些實施例，介電層74由諸如氧化矽的氧化物、諸如氮化矽的氮化物或類似者形成，或可由與介電層32的低k介電材料類似的低k介電材料形成。可使用鑲嵌製程形成RDL 72，所述製程包含蝕刻介電層74以形成開口，將導電障壁層沉積至開口中，鍍覆諸如銅或銅合金的金屬材料，以及執行平坦化以移除RDL 72的多餘部分。儘管示出了背側RDL 72的一個層及介電層74，但可存在背側RDL的多個層。根據本揭露的一些實施例， 金屬接墊80(圖10)下方的整個結構不含有機材料(諸如聚合物層)，使得用於形成金屬接墊80下方的結構的製程可採用鑲嵌製程，且可能製得具有較小間距及線寬的細間距RDL(諸如RDL 72)。金屬接墊80下方的所有介電材料均為無機介電材料。
圖10示出形成鈍化層、金屬接墊以及上覆介電層。根據一些實施例，鈍化層76(有時稱作鈍化-1)形成於介電層74上方，且通孔78形成於鈍化層76中以電連接至RDL 72。金屬接墊80形成於鈍化層76上方，且經由通孔78電耦接至RDL 72。相應製程亦在圖29中所展示的製程流程中示出為製程216。金屬接墊80可為鋁接墊或鋁銅接墊，但可使用其他金屬材料。金屬接墊80可藉由沉積毯覆式層且經由蝕刻對所述毯覆式層進行圖案化而形成。
亦如圖10中所示，鈍化層82(有時稱作鈍化-2)形成於鈍化層76上方。鈍化層76及鈍化層82中的每一者可為單層或複合層，且可由無孔材料形成。根據本揭露的一些實施例，鈍化層76及鈍化層82中的一者或兩者為複合層，其包含氧化矽層(圖中未單獨示出)及位於氧化矽層上方或下方的氮化矽層(圖中未單獨示出)。鈍化層76及鈍化層82亦可由諸如未摻雜矽酸鹽玻璃(USG)、氮氧化矽及/或類似者的其他無孔介電材料形成。
接著，圖案化鈍化層82，使得鈍化層82的一些部分覆蓋金屬接墊80的邊緣部分，且金屬接墊80的一些部分經由鈍化層82中的開口暴露。接著形成聚合物層84，且接著圖案化所述聚合物層84以暴露金屬接墊80。聚合物層84可由聚醯亞胺、聚苯并噁唑(PBO)或類似者形成。
參考圖11，形成後鈍化內連線(Post-Passivation Interconnect，PPI)86，其可包含形成金屬晶種層及所述金屬晶種層上方的經圖案化罩幕層(未示出)，以及在經圖案化罩幕層中鍍覆PPI 86。接著在蝕刻製程中移除經圖案化罩幕層以及與經圖案化罩幕層重疊的金屬晶種層的部分。接著形成聚合物層88，其可由PBO、聚醯亞胺或類似者形成。
參考圖12，形成凸塊下金屬(Under-bump metallurgy；UBM)90，且UBM 90延伸至聚合物層88中以連接至PPI 86。根據本揭露的一些實施例，UBM 90中的每一者包含障壁層(圖中未示)及障壁層上方的晶種層(圖中未示)。障壁層可為鈦層、氮化鈦層、鉭層、氮化鉭層或由鈦合金或鉭合金形成的層。晶種層的材料可包含銅或銅合金。諸如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金以及其組合的其他金屬亦可包含於UBM 90中。
亦如圖12中所展示，形成電連接件92。用於形成UBM 90及電連接件92的實例形成製程包含沉積毯覆式UBM層以及形成且圖案化罩幕(其可為光阻，圖中未示)，其中毯覆式UBM層的部分經由罩幕中的開口暴露。在形成UBM 90之後，將所示出的封裝置放於鍍覆溶液(圖中未示)中，且執行鍍覆製程以在UBM 90上形成電連接件92。根據本揭露的一些實例實施例，電連接件92包含非焊料部分(未示出)，所述部分在後續回焊製程中不會熔化。非焊料部分可由銅形成，且因此在下文中稱作銅凸塊，但所述非焊料部分亦可由其他非焊料材料形成。電連接件92可更包含焊料蓋，其可由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金或類似者形成，且可不含鉛或含鉛。
形成於前述步驟中的結構被稱作重建構晶圓94。對重建構晶圓94執行晶粒鋸切(單體化)製程，以將重建構晶圓94分成多個封裝96。相應製程在圖29中所展示的製程流程中示出為製程218。
在所得封裝中，電容器晶粒42接合至低層級介電層及裝置晶粒4中的各別接合墊。舉例而言，表面介電層38可直接位於下伏低k介電層上方且接觸下伏低k介電層。此外，金屬接墊40、RDL 34以及通孔36皆可經由鑲嵌製程而非沉積及蝕刻形成。原本為裝置晶粒4的上部特徵的金屬接墊80、聚合物層84、PPI 86、電連接件92或類似者在接合電容器晶粒42之後形成。因此，電容器晶粒42相當於插入在裝置晶粒4的下部層與上部層之間。電容器49與裝置晶粒4中的內連線結構30內部的電源網路之間的電路徑因此減小。作為比較，在習知結構中，諸如金屬接墊80、聚合物層84、PPI 86、電連接件92等上部特徵將在接合電容器晶粒42之前形成，且電容器晶粒42將接合於諸如金屬接墊80、聚合物層84、PPI 86、電連接件92等的上部特徵上方。在習知結構中，電容器49及積體電路裝置22與裝置晶粒4中的電源網路之間的電路徑將較長。電容器49被稱作深分割電容器，此是因為這些電容器並非形成於裝置晶粒4內部，而是分割成進一步插入在介電層38與諸如金屬接墊80、聚合物層84、PPI 86、電連接件92等的上覆特徵之間的另一電容器晶粒。
根據一些實施例，貫穿本揭露的所有實施例，電容器晶粒42中的電容器49中的每一者可具有兩個端子，每一端子連接至接合墊50中的一個。另一方面，電容器49可不連接至穿孔46中的 任一個及穿孔70中的任一個。此外，若電容器晶粒42包含主動裝置及/或記憶體裝置(如將在後續實施例中進行論述)，則電容器49亦與電容器晶粒42中的主動裝置及記憶體裝置電性斷開且不由所述主動裝置及記憶體裝置使用。取而代之的是，電容器49由裝置晶粒4使用。
圖13示出根據替代實施例形成的重建構晶圓94及封裝96。這些實施例與圖12中所展示的實施例類似，不同之處在於並非將離散電容器晶粒42接合至晶圓2，而是將電容器晶圓142接合至晶圓2。電容器晶圓142中同樣包含多個電容器晶粒42。用於形成對應重建構晶圓94及封裝96的製程及材料基本上與如圖1至圖12中所展示的實施例相同，不同之處在於在圖13中的實施例中，執行晶圓至晶圓接合，且不再形成間隙填充區58及穿孔70(圖12)。
圖14示出根據其他替代實施例形成的重建構晶圓94及封裝96。這些實施例與圖13中所展示的實施例類似，不同之處在於並未形成諸如圖13中所展示的重佈線72及對應介電層(諸如介電層74)的額外重佈線層。反之，可為含鋁襯墊的金屬襯墊80直接形成於穿孔46上。用於形成對應重建構晶圓94及封裝96的製程與如圖1至圖12中所展示的實施例類似，不同之處在於不再形成一些特徵。
圖15至圖20示出根據本揭露的一些實施例的形成包含深分割電容器的封裝的中間階段的截面視圖。除非另外指定，否則這些實施例中的組件的材料及形成製程基本上與類似組件相同，所述類似組件在圖1至圖12中所展示的前述實施例中由類似參考 標號表示。因此，關於圖15至圖20中所展示的組件的形成製程及材料的細節可在對前述實施例的論述中找到。
參考圖15，晶圓2(及其中的對應裝置晶粒4)接合至支撐基底102。晶圓2基本上與如圖1中所展示的晶圓2相同，不同之處在於穿孔26形成為延伸至基底20中。根據一些實施例，支撐基底102為半導體基底，諸如矽基底。根據替代實施例，支撐基底102為介電基底，諸如氧化矽基底、氮氧化矽基底或類似者。整個支撐基底102可由其中沒有其他材料(諸如金屬)的均質材料(諸如矽)形成。氧化矽層可以或可不形成於支撐基底102的表面上。接合可為熔融接合，其中晶圓2中的表面介電層38例如藉由所形成的Si-O-Si鍵接合至支撐基底102。
參考圖16，對裝置晶圓2執行背側研磨製程直至暴露穿孔26為止。在後續製程中，如圖17中所展示，背側RDL 73及介電層75形成為電耦接至前側內連線結構30及積體電路裝置22。背側RDL 73亦可使用鑲嵌製程形成。介電層75可由低k介電材料及/或非低k介電材料形成。舉例而言，頂部介電層75可為非低k介電層，而介電層75中的下伏層可為低k介電層。背側RDL 73可用於形成電源分佈網路(Power Distribution Network；PDN)，其包含用於繞線(routing)傳送諸如VDD及VSS的電源的金屬平面(板)及通孔。根據一些實施例，背側RDL 73的大部分(超過50%)金屬區域由PDN使用，且較小部分金屬區域用於訊號繞線傳送。在另一方面，大部分訊號繞線傳送在位於基底20前側上的內連線結構30內進行。儘管未詳細展示，但介電層75(及RDL 73)的總厚度大於內連線結構30的厚度。在介電層75(及RDL 73)的 總厚度大於內連線結構30的情況下，可形成具有較小電壓降的PDN。
接著，如圖18中所展示，其中包含電容器晶粒42的電容器晶圓142經由混合接合而接合至裝置晶圓2。如前述實施例中詳細論述，電容器49形成於電容器晶粒42中，且可為深溝渠電容器或其他類型的高密度電容器(諸如多層MIM電容器)。電容器晶粒49電耦接至接合墊。舉例而言，電容器49中的每一者可具有兩個端子，每一端子電連接至接合墊50中的一個。因此，在接合之後，電容器49中的每一者電連接至裝置晶粒4中的裝置，且由所述裝置使用。
圖19示出第二平坦化製程，其中研磨基底44直至暴露穿孔46為止。接著，如圖20中所展示，根據一些實施例形成金屬接墊80以連接至穿孔46。根據替代實施例，與重佈線72及介電層74(圖9)類似的更多重佈線形成於基底44的背側上，且所述重佈線連接至穿孔46。額外介電層亦可包含低k介電層，且可使用鑲嵌製程形成對應的RDL。
在後續製程中，形成上覆鈍化層82、聚合物層84及聚合物層88、PPI 86、UBM 90以及電連接件92。細節可參考圖1至圖12中所展示的實施例找到，且並未在其中重複。
在圖20中的實施例中，電容器晶粒42接合於裝置晶粒4的積體電路裝置22與諸如金屬接墊80、聚合物層84、PPI 86、電連接件92等的上覆特徵之間，且因此電容器晶粒42中的電容器49與裝置晶粒4的積體電路裝置22之間的電路徑縮短。
圖21示出根據替代實施例形成的重建構晶圓94及封裝 96。這些實施例與圖20中所展示的實施例類似，不同之處在於除深溝渠電容器49外，MIM電容器49'亦形成於電容器晶粒4的前側上。MIM電容器49'亦連接至裝置晶粒4中的積體電路裝置22，且由積體電路裝置22使用。同樣，在封裝96中，裝置晶粒4中的背側RDL 73可用於形成PDN，所述PDN包含用於繞線傳送諸如VDD及VSS的電源的金屬板及通孔。根據一些實施例，背側RDL 73的大部分金屬區域由PDN使用，及較小部分金屬區域用於訊號繞線傳送。在另一方面，大部分訊號繞線傳送在位於基底20前側上的內連線結構30內進行。儘管未詳細展示，但介電層75(及RDL 73)的總厚度亦可大於內連線結構30的厚度。
圖22示出根據替代實施例形成的重建構晶圓94及封裝96。這些實施例與圖20中所展示的實施例類似，不同之處在於除深溝渠電容器49外，MIM電容器49'亦形成於電容器晶粒4的前側上，且可包含多個層以使得電容密度增大。此外，電容器晶粒42包含記憶體裝置27，所述記憶體裝置27可形成於半導體基底44的前表面(所示出的底部表面)上。記憶體裝置27可包含靜態隨機存取記憶體(Static Random Access Memory；SRAM)、動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)或其他類型的記憶體。電容器晶粒42中可不存在深溝渠電容器。記憶體裝置27及MIM電容器49'兩者連接至裝置晶粒4中的積體電路裝置22且由積體電路裝置22使用，並且可不連接至穿孔46。根據一些實施例，支撐基底102為整體由均質材料形成的毯覆式基底。根據替代實施例，記憶體裝置106形成於支撐基底102的頂部表面處，並且電連接至裝置晶粒4中的積體電路裝置22且由積體電 路裝置22使用。
圖23示出根據替代實施例形成的重建構晶圓94及封裝96。這些實施例與圖22中所展示的實施例類似，不同之處在於電容器晶粒42不包含任何半導體基底，且MIM電容器49'形成為電容器晶粒42中的重佈線結構的一部分。MIM電容器49'可包含多個層以使得電容密度增大。根據一些實施例，支撐基底102為整體由均質材料形成的毯覆式基底。根據替代實施例，記憶體裝置形成於支撐基底102的表面處，並且電連接至裝置晶粒4中的積體電路裝置22且由積體電路裝置22使用。根據替代實施例，記憶體裝置106形成於支撐基底102的頂部表面處，並且電連接至裝置晶粒4中的積體電路裝置22且由積體電路裝置22使用。
圖24示出併有前述實施例中所揭露的封裝96的扇出封裝110。扇出封裝包含包封於包封體112中的封裝96。包封體112可為模製化合物、模製底部填充劑或類似者。包含RDL 114及介電層116的扇出重佈線結構118形成於封裝96及包封體112上。電連接件120形成於重佈線結構118的表面上。
圖25示出包含如前述實施例中所揭露的封裝96的封裝110。封裝96經由倒裝晶片接合而接合至封裝基底126。底部填充劑128施配於封裝96與封裝基底126之間。
圖26示出包含根據替代實施例形成的封裝96的封裝110。這些實施例與圖22中所展示的實施例類似，不同之處在於記憶體晶粒140接合至裝置晶粒4的背側。記憶體晶粒140可包含記憶體143，其可包含SRAM記憶體、DRAM記憶體或類似者。圖26中的裝置晶粒4的前側向上且朝向電容器晶粒42。
圖27示出包含根據替代實施例形成的封裝96的封裝110。這些實施例可藉由使用裝置晶粒(諸如記憶體晶粒)替換圖15至圖23中的支撐基底來形成。所得結構與圖26中所展示的實施例類似，不同之處在於圖27中的裝置晶粒4的前側向下且背向電容器晶粒42。
圖28示出包含與電容器晶粒42接合的裝置晶粒4的封裝150。電容器晶粒42包含電容器49，根據一些實施例，所述電容器49可為深溝渠電容器。此外，電容器晶粒42中可包含記憶體裝置27。電容器晶粒42中的穿孔158可具有不同橫向尺寸。
亦示出了電連接件92、鈍化層82/聚合物層84/聚合物層88、金屬接墊80以及PPI 86。封裝更包含記憶體晶粒152，其包含半導體基底162及形成於半導體基底162的表面上的記憶體裝置164。可為模製化合物的包封體166施配成將記憶體晶粒152包封於其中。支撐晶粒102進一步接合至記憶體晶粒152，所述支撐晶粒102可為整體由均質材料(諸如矽)形成的毯覆式晶粒。熱界面材料154及散熱器156附接至支撐晶粒102。在不同實施例中可採用或可不採用支撐晶粒102，且若不採用支撐晶粒102，則熱界面材料154將與基底162接觸。晶粒4、晶粒42以及晶粒152的大小可彼此相等或彼此不同，其中較小晶粒由間隙填充材料(諸如氧化物、氮化物或類似者)包圍。此外，可存在堆疊在一起的多於一個電容器晶粒42、多於一個記憶體晶粒152等。
在圖21至圖28中的實施例的每一者中，電容器晶粒42接合於裝置晶粒4的積體電路裝置22與諸如金屬接墊80、聚合物層84、PPI 86、電連接件92等的上覆特徵之間，且因此電容器晶 粒中的電容器與裝置晶粒4中的積體電路裝置22之間的電路徑縮短。
本發明之實施例具有一些有利特徵。藉由在電容器晶粒中形成高密度電容器，以及在邏輯晶粒的鑲嵌結構與各別上覆特徵(諸如鋁接墊、聚合物層或類似者)之間接合/插入高密度電容器，可使用高密度電容器且縮短高密度電容器與邏輯晶粒(諸如CPU、GPU、XPU或類似者)中的積體電路之間的電路徑。
根據本揭露的一些實施例，一種方法包括以下步驟。將電容器晶粒接合至裝置晶粒，其中裝置晶粒包括：第一半導體基底；主動裝置，位於第一半導體基底的表面處；多個低k介電層；第一介電層，位於多個低k介電層中的頂部低k介電層上方且接觸所述頂部低k介電層；以及多個第一接合墊，位於第一介電層中。電容器晶粒包括：第二介電層，接合至第一介電層；多個第二接合墊，位於第二介電層中，其中多個第二接合墊接合至多個第一接合墊；以及電容器，電耦接至多個第二接合墊。在電容器晶粒接合至裝置晶粒之後，在電容器晶粒上方形成含鋁接墊，其中含鋁接墊電耦接至裝置晶粒。在含鋁接墊上方形成聚合物層。在實施例中，裝置晶粒及電容器晶粒中的每一者中不含聚合物層。在實施例中，裝置晶粒及電容器晶粒中的每一者中不含含鋁接墊。在實施例中，電容器晶粒包括第二半導體基底，且電容器包括延伸至第二半導體基底中的深溝渠電容器。在實施例中，所述方法更包括在形成含鋁接墊之前：形成間隙填充區以包封電容器晶粒；以及對間隙填充區及電容器晶粒進行平坦化。在實施例中，所述方法更包括將支撐晶粒接合至裝置晶粒；以及研磨裝置晶粒以露出裝置晶粒中的穿 孔，其中穿孔延伸至第一半導體基底中。在實施例中，第一介電層及多個第一接合墊形成於經研磨的裝置晶粒上。在實施例中，支撐晶粒及電容器晶粒接合至裝置晶粒的相對側。在實施例中，電容器晶粒接合至裝置晶粒的前側。在實施例中，電容器晶粒接合至裝置晶粒的背側。在實施例中，電容器晶粒中不含主動裝置。在實施例中，電容器晶粒中不含任何半導體基底。在實施例中，所述方法更包括在電容器晶粒中形成記憶體裝置。
根據本揭露的一些實施例，一種封裝包括裝置晶粒、電容器晶粒、含鋁接墊以及聚合物層。裝置晶粒包括：半導體基底；主動裝置，位於半導體基底的表面處；多個低k介電層；第一介電層，位於多個低k介電層中的頂部低k介電層上方且接觸所述頂部低k介電層；以及多個第一接合墊，位於第一介電層中。電容器晶粒包括：第二介電層，接合至第一介電層；多個第二接合墊，位於第二介電層中，其中多個第二接合墊接合至多個第一接合墊；以及電容器，電耦接至多個第二接合墊。含鋁接墊位於電容器晶粒上方，其中含鋁接墊電耦接至裝置晶粒。聚合物層位於含鋁接墊上方。在實施例中，電容器晶粒及裝置晶粒中的每一者不含含鋁接墊。在實施例中，電容器晶粒及裝置晶粒中的每一者不含有機材料。在實施例中，所述封裝更包括環繞電容器晶粒的間隙填充區。
根據本揭露的一些實施例，一種封裝包括裝置晶粒、電容器晶粒、多個含鋁接墊、聚合物層以及多個電連接件。裝置晶粒包括第一半導體基底；多個第一介電層；以及多個第一鑲嵌結構，位於多個第一介電層中。電容器晶粒包括第二半導體基底；多個第二介電層；以及多個第二鑲嵌結構，位於多個第二介電層中，其中多 個第二鑲嵌結構的底部表面與多個第二介電層中的對應者的底部表面共面，其中多個第二介電層中的底部層接合至多個第一介電層中的頂部層。多個含鋁接墊位於電容器晶粒上方，其中多個含鋁接墊電耦接至裝置晶粒。聚合物層包括覆蓋多個含鋁接墊中的每一者的邊緣部分的一部分。多個電連接件位於多個含鋁接墊上方且電連接至多個含鋁接墊。在實施例中，裝置晶粒及電容器晶粒中的所有材料均為無機材料。在實施例中，電容器晶粒包括深溝渠電容器。
前文概述若干實施例的特徵，使得所屬領域中具通常知識者可較佳地理解本揭露的態樣。所屬領域中具有通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
200:製程流程
202,204,206,208,210,212,214,216,218:製程

Claims (10)

  1. 一種封裝的製造方法，包括：將電容器晶粒接合至裝置晶粒，其中所述裝置晶粒包括：第一半導體基底；主動裝置，位於所述第一半導體基底的表面處；多個低k介電層；第一介電層，位於所述多個低k介電層中的頂部低k介電層上方且接觸所述頂部低k介電層；以及多個第一接合墊，位於所述第一介電層中；其中所述電容器晶粒不含主動裝置且所述電容器晶粒包括：第二介電層，接合至所述第一介電層；多個第二接合墊，位於所述第二介電層中，其中所述多個第二接合墊接合至所述多個第一接合墊；以及電容器，電耦接至所述多個第二接合墊；在所述電容器晶粒接合至所述裝置晶粒之後，在所述電容器晶粒上方形成含鋁接墊，其中所述含鋁接墊電耦接至所述裝置晶粒；以及在所述含鋁接墊上方形成聚合物層。
  2. 如請求項1所述的方法，其中所述裝置晶粒及所述電容器晶粒中的每一者中不含聚合物層。
  3. 如請求項1所述的方法，其中所述裝置晶粒及所述電容器晶粒中的每一者中不含含鋁接墊。
  4. 如請求項1所述的方法，其中所述電容器晶粒包括第二半導體基底，且所述電容器包括延伸至所述第二半導體基底 中的深溝渠電容器。
  5. 如請求項1所述的方法，更包括在形成所述含鋁接墊之前：形成間隙填充區以包封所述電容器晶粒；以及對所述間隙填充區及所述電容器晶粒進行平坦化。
  6. 如請求項1所述的方法，更包括：將支撐晶粒接合至所述裝置晶粒；以及研磨所述裝置晶粒以露出所述裝置晶粒中的穿孔，其中所述穿孔延伸至所述第一半導體基底中。
  7. 一種封裝，包括：裝置晶粒，包括：半導體基底；主動裝置，位於所述半導體基底的表面處；多個低k介電層；第一介電層，位於所述多個低k介電層中的頂部低k介電層上方且接觸所述頂部低k介電層；以及多個第一接合墊，位於所述第一介電層中；電容器晶粒，所述電容器晶粒不含主動裝置且所述電容器晶粒包括：第二介電層，接合至所述第一介電層；多個第二接合墊，位於所述第二介電層中，其中所述多個第二接合墊接合至所述多個第一接合墊；以及電容器，電耦接至所述多個第二接合墊；含鋁接墊，位於所述電容器晶粒上方，其中所述含鋁接墊電 耦接至所述裝置晶粒；以及聚合物層，位於所述含鋁接墊上方。
  8. 如請求項7所述的封裝，其中所述電容器晶粒及所述裝置晶粒中的每一者不含含鋁接墊。
  9. 一種封裝，包括：裝置晶粒，包括：第一半導體基底；多個第一介電層；以及多個第一鑲嵌結構，位於所述多個第一介電層中；電容器晶粒，包括：第二半導體基底；多個第二介電層；以及多個第二鑲嵌結構，位於所述多個第二介電層中，其中所述多個第二鑲嵌結構的底部表面與所述多個第二介電層中的對應者的底部表面共面，其中所述多個第二介電層中的底部層接合至所述多個第一介電層中的頂部層；多個含鋁接墊，位於所述電容器晶粒上方，其中所述多個含鋁接墊電耦接至所述裝置晶粒；聚合物層，包括覆蓋所述多個含鋁接墊中的每一者的邊緣部分的一部分；以及多個電連接件，位於所述多個含鋁接墊上方且電連接至所述多個含鋁接墊。
  10. 如請求項9所述的封裝，其中所述裝置晶粒及所述電容器晶粒中的所有材料均為無機材料。
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