TW202349522A - 形成封裝體的方法 - Google Patents

形成封裝體的方法 Download PDF

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Publication number
TW202349522A
TW202349522A TW112120493A TW112120493A TW202349522A TW 202349522 A TW202349522 A TW 202349522A TW 112120493 A TW112120493 A TW 112120493A TW 112120493 A TW112120493 A TW 112120493A TW 202349522 A TW202349522 A TW 202349522A
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Taiwan
Prior art keywords
wafer
layer
die
metal
package
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TW112120493A
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English (en)
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陳憲偉
陳潔
鄭心圃
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台灣積體電路製造股份有限公司
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Publication of TW202349522A publication Critical patent/TW202349522A/zh

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Abstract

一種方法包括將第一晶圓接合到第二晶圓、形成貫穿第一晶圓且進一步延伸到第二晶圓中的第一穿孔以及在第一晶圓上形成重分佈線。重分佈線以及第一穿孔將第一晶圓中的第一導電特徵電性連接到第二晶圓中的第二導電特徵。在第一晶圓之上形成電性連接器。

Description

形成封裝體的方法
本發明實施例是關於一種形成封裝體的方法，特別是關於接合封裝部件的方法。
隨著同一封裝體中封裝了更多的裝置裸晶以實現更多的功能，積體電路的封裝變得越來越複雜。例如，封裝結構已發展成在同一封裝中包括複數個裝置裸晶(例如，處理器以及記憶體立方體(memory cubes))。封裝結構可包括使用不同技術形成的裝置裸晶且具有結合到相同裝置裸晶的不同功能，從而形成系統。這可節省製造成本且最佳化裝置性能。
本揭露實施例提供一種方法，此方法包括將第一晶圓接合到第二晶圓；形成第一穿孔，第一穿孔貫穿第一晶圓且進一步延伸至第二晶圓中；在第一晶圓上形成重分佈線，其中重分佈線以及第一穿孔將第一晶圓中的第一導電特徵電性連接到第二晶圓中的第二導電特徵；以及在第一晶圓之上形成電性連接器。
本揭露實施例提供一種結構，此結構包括第一裝置裸晶、第二裝置裸晶以及穿孔，第一裝置裸晶包括第一半導體基材、第一互連結構以及第一金屬墊，第一互連結構位於第一半導體基材之上，第一金屬墊位於第一半導體基材之上，第二裝置裸晶在第一裝置裸晶之上且附接到第一裝置裸晶，其中第二裝置裸晶包括第二半導體基材、第二互連結構以及第二金屬墊，第二半導體基材位於第一互連結構之上，第二互連結構位於第二半導體基材之上，第二金屬墊位於第二半導體基材之上，穿孔貫穿第二裝置裸晶且進一步延伸到第一裝置裸晶中，其中穿孔電性互連第一金屬墊以及第二金屬墊。
本揭露實施例提供一種結構，此結構包括第一裝置裸晶、裸晶附接膜、第二裝置裸晶以及第一穿孔，第一裝置裸晶包括第一鈍化層、金屬墊、第二鈍化層以及平坦化層，金屬墊位於第一鈍化層之上，第二鈍化層位於第一鈍化層以及金屬墊之上且接觸第一鈍化層以及金屬墊，平坦化層包括第一部分以及第二部分，第一部分延伸到第二鈍化層中以接觸金屬墊，第二部分位於第二鈍化層之上，裸晶附接膜位於平坦化層之上且接觸平坦化層，第二裝置裸片位於裸晶附接膜之上且黏合到裸晶附接膜，第一穿孔貫穿第二裝置裸晶，其中第一穿孔進一步貫穿平坦化層的第一部分以接觸金屬墊。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方，即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外，以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所論述的不同實施例及/或結構之間有特定的關係。
此外，其與空間相關用詞。例如“在…下方”、“下方”、“較低的”、“上方”、“較高的” 及類似的用詞，係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
提供一種封裝體及其形成方法。根據一些實施例，第一封裝部件以及第二封裝部件彼此接合，若不是通過裸晶附接膜彼此黏合，就是通過熔融結合(fusion bonding)彼此結合。穿孔形成以貫穿第一封裝部件，且將第一封裝部件與第二封裝部件彼此電性耦接。因此，電性連接不經過多個導電特徵(例如，焊接區域、結合墊(bond pads)等)以及界面。接觸電阻降低，且訊號延遲也減少。本文論述的實施例旨在提供示例以實現或使用本揭露的標的，且本領域具有一般知識者將容易理解在保持在不同實施例的預期範圍中的可進行的修改。在各種視圖以及說明性實施例中，相同的參考符號用來標示相同的元件。儘管方法實施例可被論述為以特定順序執行，但是其他方法實施例可以任何邏輯順序執行。
第1圖至第9圖示出根據一些實施例的形成封裝體的中間階段的剖面圖。對應的過程也示意性地反映在如第16圖所顯示的製程流程200中。
第1圖至第3圖示出第一封裝部件的形成以及為接合而準備的第一封裝部件。第1圖示出晶圓級(wafer-level)封裝部件10的形成過程中的剖面圖。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程202。根據一些實施例，封裝部件10是裝置晶圓，其中包括複數個裝置裸晶12，其中示出一個示例裝置裸晶12。根據一些實施例，裝置裸晶12是記憶體裸晶，例如動態隨機存取記憶體(Dynamic Random-Access Memory, DRAM)裸晶、靜態隨機存取記憶體(Static Random-Access Memory, SRAM)裸晶等。裝置裸晶12也可為邏輯裸晶，其可為中央處理單元(Central Processing Unit, CPU)裸晶、微控制單元(Micro Control Unit, MCU)裸晶、基帶(BaseBand, BB)裸晶、應用處理器(Application processor, AP)裸晶等。裝置裸晶12也可為輸入-輸出(Input-output, IO)裸晶。
根據一些實施例，封裝部件10是未切割的晶圓，其包括連續地延伸遍及封裝部件10中的所有裸晶的半導體基材20。根據替代實施例，封裝部件10是重構的晶圓，其包括分離式(discrete)裝置裸晶以及將分離式裝置封裝在其中的密封劑。例如，虛線區域41示意性地示出了當封裝部件10包括重構晶圓時的密封劑。在隨後的論述中，封裝部件10被稱為晶圓10，其作為示例被圖示為裝置晶圓。本揭露的實施例還可應用於其他類型的封裝部件，例如中介層晶圓、重構晶圓、封裝體等。
根據一些實施例，晶圓10包括半導體基材20以及形成在半導體基材20的頂部表面的特徵。半導體基材20可由晶體矽、晶體鍺、晶體矽鍺等形成或包括晶體矽、晶體鍺、晶體矽鍺等。半導體基材20也可為體(bulk)矽基材或絕緣體上矽(Silicon-On-Insulator, SOI)基材。可在半導體基材20中形成淺溝槽隔離(Shallow Trench Isolation, STI)區域(未顯示)以隔離半導體基材20中的主動區域(active regions)。
根據一些實施例，晶圓10包括積體電路裝置22，其形成在半導體基材20的頂部表面上。示例性積體電路裝置22可包括主動裝置，例如互補式金屬氧化物半導體(Complementary Metal-Oxide Semiconductor, CMOS)電晶體以及二極體，以及被動裝置(例如，電阻器、電容器、二極體等)。積體電路裝置22的細節未在此說明。根據替代實施例，晶圓10用來形成中介層，其中基材20可為半導體基材或介電基材。
層間電介質(Inter-Layer Dielectric, ILD)24形成在半導體基材20之上，且填充積體電路裝置22中電晶體(未顯示)的柵極堆疊之間的空間。根據一些實施例，層間電介質24可由磷矽玻璃(Phospho Silicate Glass, PSG)、硼矽酸鹽玻璃(Boro Silicate Glass, BSG)、硼摻雜磷矽玻璃(Boron-Doped Phospho Silicate Glass, BPSG)、氟摻雜矽玻璃(Fluorine-Doped Silicate Glass, FSG)、氧化矽等形成。層間電介質24可使用旋轉塗布、流動式化學氣相沉積(Flowable Chemical Vapor Deposition, FCVD)、化學氣相沉積(Chemical Vapor Deposition, CVD)、電漿輔助化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition, PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition, LPCVD)等形成。
接觸栓塞(未顯示)形成在層間電介質24中，且用來將積體電路裝置22電性連接到上層的金屬線34以及通孔36。根據一些實施例，接觸栓塞由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金以及/或其多層的導電材料形成。接觸栓塞的形成可包括在層間電介質24中形成接觸開口、將導電材料填充到接觸開口中以及執行平坦化(例如，化學機械拋光(Chemical Mechanical Polish, CMP)製程)以使接觸栓塞的頂部表面與層間電介質24的頂面齊平(level)。
互連結構30形成在層間電介質24以及接觸栓塞之上。互連結構30包括介電層32以及形成在介電層32中的金屬線34和通孔36。介電層32在下文中可替代地稱為金屬間介電(Inter-Metal Dielectric, IMD)層32。根據一些實施例，至少介電層32的下層由介電係數(k-value)大約低於3.0的低介電係數材料形成。介電層32可由含碳低介電係數材料、氫矽酸鹽(Hydrogen SilsesQuioxane, HSQ)、甲基矽氧烷(MethylSilsesQuioxane, MSQ)等形成或包括碳低介電係數材料、氫矽酸鹽、甲基矽氧烷等。根據本揭露的替代實施例，一些或所有介電層32由非低介電係數材料形成，例如氧化矽、碳化矽(SiC)、碳氮化矽(SiCN)、碳氧矽-氮化物(SiOCN)等。可由氮化鋁、氧化鋁、碳氧化矽等形成的蝕刻停止層(未顯示)形成在金屬間介電層32之間，且在此未顯示。
金屬線34以及通孔36形成在介電層32中。以下將同一層的金屬線34統稱為金屬層。根據一些實施例，互連結構30包括通過通孔36互連的複數個金屬層。金屬線34以及通孔36可由銅或銅合金形成，且金屬線34以及通孔36也可由其他金屬形成。形成製程可包括單鑲嵌(single damascene)製程以及雙鑲嵌(dual damascene)製程。
金屬線34包括頂部介電層32A中的一些金屬線，這些金屬線被稱為頂部金屬線。頂部金屬線34也統稱為頂部金屬層。相應的介電層32A可由例如未摻雜矽玻璃(Un-doped Silicate Glass, USG)、氧化矽、氮化矽等的非低介電係數材料形成。介電層32A也可由低介電係數材料形成，其可選自下層的金屬間介電層32的同一組候選材料。
根據一些實施例，也被稱為鈍化層的介電層38沉積在頂部金屬層之上。介電層38可由含矽介電材料形成，例如氧化矽、氮化矽、氮氧化矽、碳氧化矽等、其組合以及/或其多層。根據一些實施例，介電層38包括蝕刻停止層以及蝕刻停止層之上的另一介電層。根據一些實施例，蝕刻停止層包括氮化矽，而蝕刻停止層也可具有複合結構。例如，複合蝕刻停止層可包括氮化鋁層、氮化鋁層之上的碳氧化矽層以及碳氧化矽層之上的氧化鋁層。蝕刻停止層之上的介電層可由氧化矽、氮氧化矽、碳化矽等形成或包括氧化矽、氮氧化矽、碳化矽等。
根據其中晶圓10是重構晶圓(而不是未切割的裝置晶圓)的一些實施例，由虛線區域41表示的密封劑將裝置裸晶12彼此分離。密封劑41可包括模製化合物、模製底部填充劑等。密封劑41可包括基底材料以及基底材料中的填充顆粒。基底材料可由聚合物、環氧樹脂、樹脂以及/或類似物形成或包括聚合物、環氧樹脂、樹脂以及/或類似物。填充顆粒可為SiO 2、Al 2O 3、氧化矽等的介電顆粒，且可具有球形形狀。此外，球形填充顆粒可具有相同或不同的直徑。根據一些實施例，密封劑41的頂部表面以及底部表面與裝置裸晶12的頂部表面以及底部表面共面(coplanar)。密封劑41可形成將裝置裸晶12彼此分離的網格圖案(grid pattern)，其中裝置裸晶12在網格中。
參照第2圖，晶圓10被倒置，且附接到進一步形成在載體42上的釋放膜40。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程204。載體42可為玻璃載體、有機載體等。根據一些實施例，釋放膜40可由基於聚合物的材料(例如，光熱轉換(Light-To-Heat-Conversion, LTHC)材料)形成，其在受熱時可分解。根據替代實施例，膜40是由例如氧化矽、氮化矽、氮氧化矽等的含矽介電材料形成的結合膜，且載體42可為矽晶圓。因此，結合膜可通過熔融結合而結合到介電層38，形成Si-O-Si鍵。
在隨後的製程中，對半導體基材20執行背面研磨製程，從而薄化半導體基材20。例如，薄化的半導體基材20的厚度可在大約3μm到大約10μm之間的範圍中。背面研磨製程可通過化學機械拋光(CMP)製程或機械研磨製程來執行。
參照第3圖，接合膜44形成在基材20的背面上。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程206。根據一些實施例，接合膜44是黏合膜，其具有將接合膜44的相對側上的特徵黏合在一起的功能。根據這些實施例，接合膜44可替代地稱為裸晶附接膜(Die-Attach Film, DAF)。根據一些實施例，接合膜44包括有機材料，其可包括聚合物。接合膜44可包括環氧樹脂、樹脂等。根據一些實施例，接合膜44包括無機材料，例如氧化矽、氮化矽、氮氧化矽等。根據一些實施例，接合膜44可預先形成，且預先形成的接合膜44黏合到晶圓10。根據替代實施例，接合膜44形成在晶圓10上，例如，通過塗布製程，接合膜44在處於可流動形式時被塗布。塗布之後可能有或可能沒有固化製程(例如，熱固化製程)。
根據替代實施例，接合膜44由含矽(無機)介電材料形成或包括含矽(無機)介電材料，其可包括矽以及附加元素，例如碳、氮、氧等及其組合。接合膜44的示例材料可包括氧化矽、氮氧化矽(SiON)、氮化矽(SiN)、碳氮氧化矽(SiOCN)、碳氮化矽(SiCN)、碳氧化矽(SiOC)、碳化矽(SiC)等。形成製程可包括原子層沉積(Atomic Layer Deposition, ALD)、化學氣相沉積(CVD)、電漿輔助化學氣相沉積(PECVD)等。
第4圖以及第5圖示出第二封裝部件的形成以及為接合而準備的第二封裝部件。第4圖示出晶圓級封裝部件50的形成過程中的剖面圖。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程208。根據一些實施例，封裝部件50是未切割的裝置晶圓，其中包括複數個裝置裸晶52，其中示出一個裝置裸晶52。根據替代實施例，封裝部件50為重構晶圓或可包括重構晶圓。根據一些實施例，裝置裸晶52為邏輯裸晶，例如中央處理單元裸晶、微控制單元裸晶、基帶(BB)裸晶、應用處理器裸晶等。裝置裸晶52還可包括記憶體裸晶，例如動態隨機存取記憶體裸晶、靜態隨機存取記憶體裸晶等。
根據其中封裝部件50為未切割晶圓或包括未切割晶圓的一些實施例，封裝部件50包括連續地延伸遍及封裝部件50中的所有裸晶52的半導體基材60。根據替代實施例，封裝部件50為重構晶圓或包括重構晶圓，其包括分離式裝置裸晶52以及將分離式裝置裸晶52封裝在其中的密封劑(未顯示)。在隨後的論述中，封裝部件50被稱為晶圓50，其使用裝置晶圓作為示例來說明。
半導體基材60可由晶體矽、晶體鍺、晶體矽鍺等形成。半導體基材60也可為體矽基材或絕緣體上矽基材。根據一些實施例，晶圓50包括積體電路裝置62，其形成在半導體基材60的頂部表面上。示例性積體電路裝置62可包括主動裝置(例如，互補式金屬氧化物半導體電晶體和二極體)以及被動裝置(例如，電阻器、電容器的、二極體等)。積體電路裝置62的細節未在此說明。
層間電介質64形成在半導體基材60之上，且填充積體電路裝置62中電晶體(未顯示)的柵極堆疊之間的空間。層間電介質64的材料可選自用於形成層間電介質24的同一組候選材料(第1圖)。接觸栓塞(未顯示)形成在層間電介質64中。互連結構66形成在層間電介質64以及接觸栓塞之上。互連結構66包括介電層72以及形成在介電層72中的金屬線68以及通孔70。根據一些實施例，這些特徵的結構以及形成過程可相似於晶圓10中對應的特徵的結構以及形成過程。
金屬線68包括在頂部的介電層72(標示為頂部介電層72A)中的一些金屬線，這些金屬線被稱為頂部金屬線68A。頂部金屬線68A也統稱為頂部金屬層。相應的介電層72A可由例如未摻雜矽玻璃、氧化矽、氮化矽等或其多層的非低介電係數材料形成。
鈍化層74(有時稱為鈍化-1(passivation-1或pass-1))形成於互連結構66之上。根據一些實施例，鈍化層74由介電係數等於或大於氧化矽的介電係數的非低介電係數材料形成。鈍化層74可由無機介電材料形成或包括無機介電材料，其可包括選自(但不限於)氮化矽、氧化矽、氮氧化矽、碳氧化矽、碳氮化矽等等、其組合以及/或其多層的材料。
鈍化層74在蝕刻製程中被圖案化以形成開口(被通孔76占據)。蝕刻製程可包括乾蝕刻製程，其包括形成圖案化的蝕刻光罩(未顯示)(例如，圖案化的光阻)，然後蝕刻鈍化層74。然後去除圖案化的蝕刻光罩，且通過對應的開口暴露金屬線(墊)68A。
接下來，形成通孔76以及導電特徵78(以下也稱為金屬墊)。通孔76延伸到鈍化層74中的開口中，且金屬墊78形成在鈍化層74之上。根據一些實施例，金屬墊78以及通孔76的形成包括電鍍製程，其可包括沉積金屬種晶層、在金屬種晶層之上形成圖案化的電鍍光罩(未顯示)以及在圖案化的電鍍光罩的開口中電鍍通孔76以及金屬墊78。然後去除圖案化的電鍍光罩，隨後進行蝕刻製程以去除金屬種晶層的暴露部分。根據替代實施例，通孔76以及金屬墊78的形成包括沉積製程(例如，物理氣相沉積(Physical Vapor Deposition, PVD)製程)，隨後是通過蝕刻的圖案化製程。金屬墊78以及通孔76可包括鋁銅、銅、鋁、鎳、鎢等或其合金。根據替代實施例，金屬墊78以及通孔76包括銅且不含鋁。
鈍化層80沉積在金屬墊78以及鈍化層74之上。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程210。根據一些實施例，鈍化層80由無機介電材料形成或包括無機介電材料，其可包括但不限於氮化矽、氧化矽、氮氧化矽、碳氧化矽等、其組合以及/或其多層。例如，鈍化層80可包括作為蝕刻停止層的氮化矽層、蝕刻停止層之上的氧化矽層以及氧化矽層之上的另一氮化矽層。第4圖示意性地示出了兩個層，其中層80A可包括氧化矽層，而層80B可包括氮化矽層。鈍化層80的沉積可通過共形(conformal)沉積製程(例如，原子層沉積、化學氣相沉積等)來執行。
鈍化層80通過沉積製程被圖案化以形成開口82，例如通過微影製程。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程212。一些金屬墊78因此被暴露。根據一些實施例，鈍化層74(而不是金屬墊78)暴露於一些開口82。根據替代實施例，鈍化層74的任何部分都沒有通過任何開口暴露，且所有開口82都與金屬墊78重疊。
參照第5圖，形成平坦化層84。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程214。根據一些實施例，平坦化層84由無機介電材料形成或可包括無機介電材料，其可為含矽介電材料，例如SiO 2、SiOC、SiON、SiOCN、SiCN等。根據替代實施例，平坦化層84由聚合物形成或包含聚合物，其可由聚酰亞胺、聚苯噁唑(polybenzoxazole, PBO)等形成或包括聚酰亞胺、聚苯噁唑等。然後執行平坦化製程(例如，化學機械拋光製程或機械拋光製程)，以使平坦化層84的頂部表面是平坦的。
第6圖示出晶圓10與晶圓50的接合(其可通過黏合或熔融結合)。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程216。接合可為面對背(face-to-back)的接合，其中晶圓50的正面(所述面)接合到晶圓10的背面。
根據接合膜44是例如裸晶附接膜的黏合膜的一些實施例，接合膜44與平坦化層84的接合是通過黏合進行的。根據這些實施例，平坦化層84可由無機材料或有機材料形成或包括無機材料或有機材料，如在前面的段落中所論述的。根據一些實施例，在晶圓10通過黏合接合膜44而黏合到晶圓50之後，可執行熱定型製程以熱定型(固化)接合膜44。根據替代實施例，從晶圓10以及晶圓50已經接合的時間開始到在第8圖中所顯示的製程已經執行的時間結束的整個製程期間，不執行熱定型過程。
根據替代實施例，接合通過結合製程執行，其中接合膜44通過熔融結合而結合至平坦化層84。在這些實施例中，接合膜44以及平坦化層84皆可由含矽介電材料形成或包括含矽介電材料，例如SiO 2、SiOC、SiON、SiOCN、SiCN等，如前面段落中所論述的。因此，形成Si-O-Si鍵以將接合膜44與平坦化層84接合。根據替代實施例，不形成接合膜44，且晶圓10中的半導體基材20通過熔融結合直接(且物理上)結合到平坦化層84，再形成Si-O-Si鍵。
參照第7圖，載體42從晶圓10釋放，例如，藉由將雷射投射在釋放膜40上以分解釋放膜40，以使重構晶圓10可與載體42分離。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程218。根據替代實施例，其中膜40是通過熔融結合而結合到基材20的結合膜，載體42以及結合膜40可通過機械拋光而被去除。
參照第8圖，形成穿孔86以將晶圓10與晶圓50電性連接以及訊號連接。根據一些實施例，穿孔86的形成可包括在晶圓10上沉積介電層87、蝕刻通過介電層87以及晶圓10、然後蝕刻晶圓50中的平坦化層84，以暴露金屬墊78。蝕刻在金屬墊78的頂部表面上停止。根據其中平坦化層84延伸到鈍化層80中以接觸鈍化層74的一些實施例，由蝕刻製程形成的一些開口貫穿鈍化層74，以暴露金屬墊68A。根據替代實施例，在蝕刻製程之後沒有金屬墊68被暴露。
然後，形成穿孔86。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程220。形成製程包括沉積襯在(lining)開口中的共形介電絕緣層89、執行非等向性(anisotropic)蝕刻製程以去除介電絕緣層89的水平部分(從而再次露出金屬墊78以及金屬墊68A)以及利用導電材料填充開口。導電材料可包括鎢、銅等。然後，執行平坦化製程以去除導電材料的多餘部分，形成穿孔86，穿孔86藉由介電絕緣層89與晶圓10以及晶圓50的周圍部分分開。根據一些實施例，一些穿孔86貫穿鈍化層74以接觸金屬墊68A。這些穿孔86使用虛線顯示以表示可形成或不形成這些穿孔。根據替代實施例，穿孔86均未貫穿鈍化層74以接觸金屬墊68A。
還形成重分佈線(Redistribution lines, RDLs)88以及通孔90，以使晶圓10中的金屬線(墊)34以及晶圓50中的金屬墊78/金屬線68A通過穿孔86、重分佈線88以及通孔90電性互連。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程222。然後，形成介電層92以覆蓋重分佈線88。
第9圖示出根據一些實施例的凸塊下金屬(Under-Bump Metallurgies, UBMs)94以及電性連接器98的形成。為了形成凸塊下金屬94，形成介電層92(使用聚合物或無機介電材料)，且在介電層92中形成開口以暴露下層的金屬墊，其在說明性實施例中是重分佈線88的一部分。然後，例如通過電鍍形成凸塊下金屬94。凸塊下金屬94可由鎳、銅、鈦或其多層形成或包括鎳、銅、鈦或其多層。
然後，在凸塊下金屬94上形成介電層96以及電性連接器98。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程224。電性連接器98的形成可包括沉積以及圖案化介電層96、將焊球(solder balls)放置在凸塊下金屬94的暴露部分上、然後回流焊球，且因此電性連接器98包括焊接區域。根據本揭露的替代實施例，電性連接器98的形成包括執行電鍍製程以形成焊接層，然後回流焊接層。電性連接器98還可包括非焊接金屬柱或非焊接金屬柱之上的金屬柱以及焊帽，其也可通過電鍍形成。在整個實施方式中，包括晶圓10以及晶圓50的結構被稱為重構晶圓100。
根據一些實施例，重構晶圓100被放置在切割膠帶(未顯示)上，其附接至框架(未顯示)。然後，重構晶圓100在裸晶切割製程中被分割，例如，使用刀片，以使重構晶圓100被分離成分離式封裝體100'。相應的製程被示出在如第16圖中所顯示的製程流程200中的製程226。分離式封裝體100'的每一個包括來自切割晶圓10的裝置裸晶12以及來自切割晶圓50的裝置裸晶52。
根據替代實施例，重構晶圓100未被切割，而是在晶圓級使用。例如，在高計算應用(例如，人工智能(Artificial Intelligence, AI)應用)中，重構晶圓100在不被切割的情況下被進一步封裝。在重構晶圓100被使用(通電)時，重構晶圓100可維持為一個整體，且未被切割。
如第9圖中所顯示，裝置裸晶12以及裝置裸晶52之間的訊號以及電性通訊通過穿孔86進行，穿孔86與裝置裸晶12以及裝置裸晶52中的特徵(例如，金屬線/墊)直接連接。沒有使用通過焊接、金屬墊、微凸塊等的結合。因此，通訊路徑較短，且在裝置裸晶12以及裝置裸晶52之間形成的界面的數量減少了。作為比較，如果裝置裸晶12以及裝置裸晶52通過焊接區域、金屬墊、微凸塊等彼此結合，則形成更多的界面，而增加了接觸電阻。通訊路徑也可能更長。
第10圖以及第11圖示出根據替代實施例的重構晶圓100以及封裝體100'。除非另有說明，否則這些實施例中的晶圓100以及封裝體100'的材料以及形成製程與第1圖至第9圖中所顯示的前述實施例中由相同參考符號表示的相同部件基本上相同。關於第10圖以及第11圖中所顯示的部件的形成製程以及材料的細節可因此在前面實施例的論述中找到。
第10圖示出一實施例，其中穿孔86均與頂部介電層72A中的金屬墊68A接觸，且沒有形成金屬墊78(如第9圖中)。根據一些實施例，介電層72A的頂部表面與金屬墊68A的頂部表面共面。鈍化層74因此為平面層。因此，可形成平坦化層84，也可不形成平坦化層84，且因此平坦化層84以虛線顯示。
第11圖示出一實施例，其中有複數個晶圓10(以晶圓10-1以及晶圓10-2為示例)的層列(tiers)。儘管示出了兩個晶圓10以及對應的裝置裸晶12-1以及裝置裸晶12-2，但是還可堆疊更多層列。根據一些實施例，穿孔86-1、86-2等被形成，且通過重分佈線88-1、重分佈線88-2等互連，以使從頂部裸晶12-1至底部裸晶52的電性連接具有較少的界面，且降低了電性路徑中的接觸電阻。本實施例可使用於記憶體堆疊的堆疊。
根據本揭露的實施例形成的封裝體100'可使用於各種封裝體，如第12圖至第15圖中所顯示。第12圖示出封裝體110A，其包括結合到封裝部件102的封裝體100'，封裝部件102進一步結合到封裝部件104。封裝部件102可為裝置裸晶、封裝體、中介層等。封裝部件104可為封裝基板、印刷電路板等。附加的封裝部件106可結合到封裝部件102。所得的封裝體110A可為基材上晶圓上晶片(Chip-on-Wafer-on-Substrate, CoWoS)封裝體。
第13圖示出其中包括封裝體100'的封裝體110B。封裝體110B可為扇出型(fanout)封裝體，其中封裝體100'以及穿孔116被封裝在可為模製化合物的密封劑118中。互連結構114基於封裝體100'、穿孔116以及密封劑118逐層(layer-by-layer)形成，從而形成底部封裝體(扇出型封裝體)120。頂部封裝部件122結合到底部封裝120以形成封裝體110B。裸晶附接膜在密封劑118中。底部填充劑121用來封裝焊接區域123。
第14圖示出基材上晶圓上晶片封裝體110C，其包括結合到矽中介層126的封裝體100'。矽中介層126包括可為矽基材的半導體基材130以及貫穿半導體基材130的穿孔132。中介層126進一步結合到封裝部件128，其可為封裝基材、印刷電路板等。
第15圖示出基於有機中介層的基材上晶圓上晶片封裝體110D，其中封裝體100'結合到有機中介層126'。有機中介層126'包括有機介電層以及有機介電層中的重分佈線。中介層126'進一步結合到封裝部件128，其可為封裝基板、印刷電路板等。
在上面說明的實施例中，根據一些實施例論述了一些製程以及特徵以形成三維(three-dimensional, 3D)封裝體。還可包括其他特徵以及製程。例如，可包括測試結構以幫助三維封裝或三維積體電路裝置的驗證測試。測試結構可包括例如形成在重分佈層中或基材上的測試墊，其允許三維封裝或三維積體電路的測試、探針以及/或探針卡的使用等。可對中間結構以及最終的結構執行驗證測試。此外，本文所揭露的結構以及方法可結合合併已知良好裸晶的中間驗證的測試方法來使用，以增加產量且降低成本。
本揭露的實施例具有一些有利的特徵。藉由將裝置裸晶黏合或結合在一起，且形成穿孔以貫穿一個裝置裸晶以接觸另一個裝置裸晶中的金屬墊，連接兩個裝置裸晶的電性路徑包括更少的界面。接觸電阻因此降低。電性路徑也更短，從而導致更低的訊號延遲。
根據一些實施例，提供一種方法包括將第一晶圓接合到第二晶圓；形成第一穿孔，第一穿孔貫穿第一晶圓且進一步延伸至第二晶圓中；在第一晶圓上形成重分佈線，其中重分佈線以及第一穿孔將第一晶圓中的第一導電特徵電性連接到第二晶圓中的第二導電特徵；以及在第一晶圓之上形成電性連接器。在一實施例中，此方法更包括將裸晶附接膜黏合到第一晶圓，其中第一晶圓以及第二晶圓通過裸晶附接膜彼此接合。在一實施例中，裸晶附接膜包括有機材料，且其中將裸晶附接膜黏合到第一晶圓包括黏合。在一實施例中，此方法更包括預先形成裸晶附接膜，其中預先形成的裸晶附接膜黏合到第一晶圓。
在一實施例中，形成第一穿孔包括蝕刻通過第一晶圓、裸晶附接膜以及第二晶圓的一部分以形成開口；且此方法更包括利用導電材料填充開口以形成第一穿孔。在一實施例中，此方法更包括在第一晶圓上沉積含矽介電層，其中將第一晶圓接合到第二晶圓包括通過熔融結合將含矽介電層結合到第二晶圓。在一實施例中，此方法更包括在第二晶圓中的第一金屬墊之上形成第一鈍化層；以及在第二晶圓上沉積平坦化層，其中平坦化層包括延伸到第一鈍化層中以接觸第一金屬墊的部分，且其中第一晶圓結合到平坦化層。在一實施例中，第一穿孔貫穿平坦化層的一部分以接觸第一金屬墊。
在一實施例中，第一金屬墊位於第二鈍化層之上，第二鈍化層位於第一鈍化層的下層，且其中此方法更包括形成第二穿孔，第二穿孔貫穿第一晶圓且進一步延伸到第二晶圓中，其中第二穿孔貫穿第二鈍化層以落在(land on)位於第二鈍化層的下層的第二金屬墊上。在一實施例中，此方法更包括將第一晶圓以及第二晶圓切割成複數個封裝體，其中複數個封裝體中的每一個包括第一晶圓中的第一裸晶以及第二晶圓中的第二裸晶。在一實施例中，此方法更包括在形成重分佈線之後，將第三晶圓接合到第一晶圓；以及形成貫穿第三晶圓的第二穿孔，其中第二穿孔電性連接至第一穿孔。在一實施例中，第一晶圓的背面接合到第二晶圓的正面。
根據一些實施例，提供一種結構，包括第一裝置裸晶、第二裝置裸晶以及穿孔，第一裝置裸晶包括第一半導體基材、第一互連結構以及第一金屬墊，第一互連結構位於第一半導體基材之上，第一金屬墊位於第一半導體基材之上，第二裝置裸晶在第一裝置裸晶之上且附接到第一裝置裸晶，其中第二裝置裸晶包括第二半導體基材、第二互連結構以及第二金屬墊，第二半導體基材位於第一互連結構之上，第二互連結構位於第二半導體基材之上，第二金屬墊位於第二半導體基材之上，穿孔貫穿第二裝置裸晶且進一步延伸到第一裝置裸晶中，其中穿孔電性互連第一金屬墊以及第二金屬墊。在一實施例中，第一裝置裸晶中的第一介電層通過熔融結合而結合到第二裝置裸晶中的第二介電層。在一實施例中，此結構更包括位於第一裝置裸晶以及第二裝置裸晶之間的黏合膜，其中黏合膜將第一裝置裸晶黏合到第二裝置裸晶。在一實施例中，黏合膜包括有機材料。在一實施例中，黏合膜包含聚合物。
根據一些實施例，提供一種結構，包括第一裝置裸晶、裸晶附接膜、第二裝置裸晶以及第一穿孔，第一裝置裸晶包括第一鈍化層、金屬墊、第二鈍化層以及平坦化層，金屬墊位於第一鈍化層之上，第二鈍化層位於第一鈍化層以及金屬墊之上且接觸第一鈍化層以及金屬墊，平坦化層包括第一部分以及第二部分，第一部分延伸到第二鈍化層中以接觸金屬墊，第二部分位於第二鈍化層之上，裸晶附接膜位於平坦化層之上且接觸平坦化層，第二裝置裸片位於裸晶附接膜之上且黏合到裸晶附接膜，第一穿孔貫穿第二裝置裸晶，其中第一穿孔進一步貫穿平坦化層的第一部分以接觸金屬墊。在一實施例中，平坦化層包括平坦的頂部表面以及非平坦的底部表面。在一實施例中，此結構更包括貫穿第二裝置裸晶的第二穿孔，其中第二穿孔進一步貫穿平坦化層的第二部分以及平坦化層的下層的介電層以接觸第一裝置裸晶中的附加金屬墊。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
10,50:封裝部件/晶圓級封裝部件/晶圓 10-1,10-2:晶圓 12:裝置裸晶 12-1:裝置裸晶/頂部裸晶 12-2:裝置裸晶 20:半導體基材 22,62:積體電路裝置 24,64:層間電介質 30,66,114:互連結構 32:介電層/金屬間介電層 32A:介電層/頂部介電層 34:金屬線/頂部金屬線 36,70,76,90:通孔 38:介電層 40:膜/釋放膜/結合膜 41:虛線區域/密封劑 42:載體 44:接合膜 52:裝置裸晶/底部裸晶 60:半導體基材 68:金屬線/金屬墊 68A:頂部金屬線/金屬線/金屬墊 72:頂部介電層 72A,87:介電層 74:鈍化層 78:金屬墊/導電特徵 80:鈍化層 80A,80B:層 82:開口 84:平坦化層 86,86-1,86-2,116:穿孔 88,88-1,88-2:重分佈線 89:介電絕緣層/共形介電絕緣層 92,96:介電層 94:凸塊下金屬 98:電性連接器 100:重構晶圓 100’:離散封裝體/封裝體 102,104,106,128:封裝部件 110A,110B:封裝體 110C,110D: 基材上晶圓上晶片封裝體 118:密封劑 120:底部封裝體 121:底部填充劑 122:頂部封裝部件 123:焊接區域 126:矽中介層/中介層 126’:有機中介層/中介層 130:半導體基材 132:穿孔 200:製程流程 202,204,206,208,210,212,214,216,218,220,222,224,226:製程
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖示並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。 第1圖到第9圖示出根據一些實施例的封裝製程中的中間階段的剖面圖。 第10圖以及第11圖示出根據一些實施例的一些封裝體的剖面圖。 第12圖到第15圖示出根據一些實施例的一些封裝體的剖面圖。 第16圖示出根據一些實施例的用於形成封裝體的製程流程。
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224,226:製程

Claims (1)

  1. 一種形成封裝體的方法，包括： 將一第一晶圓接合到一第二晶圓； 形成一第一穿孔，貫穿該第一晶圓且進一步延伸至該第二晶圓中； 在該第一晶圓上形成一重分佈線，其中該重分佈線以及該第一穿孔將該第一晶圓中的一第一導電特徵電性連接到該第二晶圓中的一第二導電特徵；以及 在該第一晶圓之上形成一電性連接器。
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