TWI665742B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI665742B
TWI665742B TW107101756A TW107101756A TWI665742B TW I665742 B TWI665742 B TW I665742B TW 107101756 A TW107101756 A TW 107101756A TW 107101756 A TW107101756 A TW 107101756A TW I665742 B TWI665742 B TW I665742B
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Taiwan
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die
interconnected
device die
bonding
forming
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TW107101756A
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TW201923911A (zh
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丁國強
吳集錫
侯上勇
俞篤豪
許家豪
葉庭聿
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括將第一裝置晶粒及第二裝置晶粒接合至內 連晶粒。所述內連晶粒包括：第一部分，位於所述第一裝置晶粒之上且接合至所述第一裝置晶粒；以及第二部分，位於所述第二裝置晶粒之上且接合至所述第二裝置晶粒。所述內連晶粒將所述第一裝置晶粒電性連接至所述第二裝置晶粒。所述方法更包括：將所述內連晶粒包封於包封材料中；以及在所述內連晶粒之上形成多條重佈線。

Description

半導體裝置及其製造方法
本發明實施例是有關於一種半導體裝置及其製造方法。
積體電路的封裝技術隨著在同一封裝體中封裝有更多裝置晶粒來達成更多功能而變得越來越複雜。舉例而言，封裝體可包括接合至同一中介層的多個裝置晶粒(例如處理器及記憶體立方體(memory cube))。中介層可藉由半導體基底來形成，在所述半導體基底中形成有矽穿孔(through-silicon via)，以對在中介層的相對兩側上形成的特徵進行內連。模製化合物將裝置晶粒包封於所述模製化合物中。所述包括中介層及裝置晶粒的封裝體進一步接合至封裝基底。另外，表面安裝裝置(surface mount device)亦可接合至所述基底。
本發明實施例提供一種半導體裝置的製造方法，其步驟如下。將第一裝置晶粒及第二裝置晶粒接合至內連晶粒。所述內 連晶粒包括：第一部分與第二部分。第一部分位於所述第一裝置晶粒之上且接合至所述第一裝置晶粒。第二部分位於所述第二裝置晶粒之上且接合至所述第二裝置晶粒。所述內連晶粒將所述第一裝置晶粒電性連接至所述第二裝置晶粒。將所述內連晶粒包封於包封材料中。在所述內連晶粒之上形成多條重佈線。
本發明實施例提供另一種半導體裝置的製造方法，其步驟如下。在載體之上形成介電層；形成多條重佈線，所述多條重佈線的通孔部分貫穿所述介電層；藉由晶粒貼合膜，以將內連晶粒貼合至所述多條重佈線的表面；將所述內連晶粒包封於包封材料中；以及將第一封裝組件及第二封裝組件接合至所述內連晶粒，其中所述第一封裝組件接合至所述內連晶粒的第一部分，且所述第二封裝組件接合至所述內連晶粒的第二部分。
本發明實施例提供一種半導體裝置，包括第一裝置晶粒、第二裝置晶粒、內連晶粒、包封材料以及穿孔。內連晶粒接合至所述第一裝置晶粒及所述第二裝置晶粒。所述內連晶粒將所述第一裝置晶粒電性連接至所述第二裝置晶粒。包封材料將所述內連晶粒包封於所述包封材料中。穿孔貫穿所述包封材料以連接至所述第一裝置晶粒。
20‧‧‧載體
22‧‧‧離型層
24‧‧‧介電層
26、32、36、68、74、78‧‧‧重佈線
28、34、64、72、76、80‧‧‧介電層
30、66、87‧‧‧開口
38、38A、38B‧‧‧內連晶粒
40、40A、40B‧‧‧積體被動裝置
42、69‧‧‧晶粒貼合膜
44‧‧‧包封材料
45‧‧‧虛線
46‧‧‧區
48‧‧‧穿孔
50、50A、50B、50C‧‧‧封裝組件
52‧‧‧接合接墊
54‧‧‧底部填充膠
56‧‧‧複合晶圓
58、82‧‧‧銲料區
60、88‧‧‧封裝體
62‧‧‧金屬接墊
70‧‧‧虛線
84‧‧‧封裝組件
85‧‧‧切割道
86‧‧‧光阻
88‧‧‧封裝體
110‧‧‧基底
112‧‧‧內連結構
114‧‧‧介電層
116‧‧‧金屬線路及通孔
118、120‧‧‧接合接墊
200、300、400‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、302、 304、306、308、310、312、314、316、318、320、402、404、406、408、410、412‧‧‧步驟
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本業界中的標準慣例，各種特徵並非按比 例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖9示出根據一些實施例的封裝的形成製程中的各中間階段的剖視圖。
圖10至圖20示出根據一些實施例的封裝體的形成製程中的各中間階段的剖視圖。
圖21至圖24示出根據一些實施例的封裝體的形成製程中的各中間階段的剖視圖。
圖25示出根據一些實施例的包括封裝基底或印刷電路板(printed circuit board)的封裝體。
圖26、圖27及圖28示出根據一些實施例的形成封裝體的製程流程。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考標號及/或字母。此種 重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
另外，為了易於說明，本文中可使用例如「在...之下」、「在...下方」、「下部」、「上覆」、「上部」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除了圖中所繪示的定向之外，所述空間相對性用語旨在涵蓋裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)，且本文所用的空間相對性描述詞可同樣相應地作出解釋。
根據各種示例性實施例提供一種封裝體及其形成方法。根據一些實施例來說明形成所述封裝體的中間階段。對一些實施例的一些變形進行論述。在各個圖中及說明性實施例通篇中，相同的參考標號用於標示相同的元件。
圖1至圖9示出根據本揭露一些實施例的封裝體的形成製程中的各中間階段的剖視圖。圖1至圖9所示製程亦被稱為先重佈線(Redistribution Line，RDL)(或RDL-first)製程。圖1至圖9所示步驟亦示意性地反映在圖26所示製程流程200中。
圖1示出載體20及在載體20上形成的離型層22。載體20可為玻璃載體、矽晶圓、有機載體等。載體20可具有圓的俯視圖形狀，且可具有常見矽晶圓的大小。舉例而言，載體20可具有8英吋的直徑、12英吋的直徑等。離型層22可由聚合物系材料(例如光熱轉換(Light To Heat Conversion，LTHC)材料)形成，離 型層22可與載體20一起從將在後續步驟中形成的上覆結構被移除。根據本揭露的一些實施例，離型層22是由環氧系熱釋放材料所形成。可將離型層22塗佈至載體20上。離型層22的頂表面被整平且具有高的共平面度(degree of co-planarity)。
在離型層22上形成介電(緩衝)層24。根據本揭露的一些實施例，介電層24是由聚合物所形成，所述聚合物亦可以是感光性材料，例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)等。所述感光性材料可容易使用微影(photo lithography)製程來進行圖案化。
在介電層24之上形成重佈線(RDL)26。相應步驟在圖26所示製程流程中被稱為步驟202。重佈線26可包括足夠大的一些部分，以當作用於接合至銲料區或金屬凸塊的金屬接墊。重佈線26的形成可包括：在介電層24之上形成晶種層(圖中未示出)，在所述晶種層之上形成例如光阻等圖案化罩幕(圖中未示出)，以及接著在被暴露的晶種層上執行金屬鍍覆。接著移除圖案化罩幕及先前被圖案化罩幕所覆蓋的晶種層的一些部分，以留下重佈線26，如圖1所示。根據本揭露的一些實施例，晶種層包括鈦層及位於所述鈦層之上的銅層。所述晶種層可使用例如物理氣相沈積(Physical Vapor Deposition，PVD)來形成。所述鍍覆可使用例如無電鍍覆(electro-less plating)來執行。
參照圖2，在重佈線26上形成介電層28。相應步驟在圖26所示製程流程中被示出為步驟204。介電層28的底表面接觸重 佈線26的頂表面及介電層24的頂表面。根據本揭露的一些實施例，介電層28是由聚合物所形成，所述聚合物可為例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等感光性材料。另外，介電層28可包含非有機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽等。對介電層28進行圖案化，以在介電層28中形成開口30。因此，重佈線26的一些部分外露於開口30。
接下來，參照圖3，形成重佈線32以連接至重佈線26。相應步驟亦在圖26所示製程流程中被示出為步驟204。重佈線32包括位於介電層28之上的金屬跡線(金屬線路)。重佈線32亦包括延伸至介電層28中的開口中的通孔。重佈線32亦在鍍覆製程中形成，且所得重佈線32中的每一者包括晶種層(圖中未示出)及位於所述晶種層之上的所鍍覆金屬材料。晶種層及所鍍覆材料可由同一種材料或不同的材料所形成。重佈線32可包括金屬或金屬合金，所述金屬或金屬合金包括鋁、銅、鎢或其合金。
參照圖4，在重佈線32及介電層28之上形成介電層34。相應步驟在圖26所示製程流程中被示出為步驟206。介電層34可使用聚合物來形成，所述聚合物可選自與介電層28的材料相同的材料。舉例而言，介電層34可由聚苯並噁唑、聚醯亞胺、苯並環丁烯等所形成。另外，介電層34可包含非有機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽等。
圖4亦示出電性連接至重佈線32的重佈線36的形成。相應步驟亦在圖26所示製程流程中被示出為步驟206。重佈線36 的形成可採用與形成重佈線32的方法及材料相似的方法及材料。應理解，儘管在說明性示例性實施例中，對兩個介電層28及34以及在所述兩個介電層28及34中所形成的相應的重佈線32及36進行論述，然而端視佈線需求(routing requirement)及使用聚合物來緩衝應力的需求而定，可採用更少的或更多的介電層。舉例而言，可存在單層聚合物層或者三層、四層、或更多層聚合物層。由於製程原因，重佈線32及36的通孔部分為錐形，其中上部部分寬於相應的下部部分。
圖5示出內連晶粒38及積體被動裝置(Integrated Passive Device，IPD)40的貼合。相應步驟被示出為圖26所示製程流程中的步驟208。根據本揭露的一些實施例，藉由晶粒貼合膜(Die-Attach Film，DAF，其為黏著膜)42將內連晶粒38及積體被動裝置40貼合至重佈線36。每一晶粒貼合膜42可黏著至一條重佈線36，或者可貼合至多於一條重佈線36，如在圖5中作為實例所示。根據替代實施例，藉由晶粒貼合膜42，以將內連晶粒38及積體被動裝置40貼合至介電層34，其中晶粒貼合膜42接觸介電層34的頂表面。內連晶粒38具有對後續接合的裝置晶粒50(示於圖9中)進行內連的功能。根據本揭露的一些實施例，內連晶粒38包括基底110，基底110可為半導體基底(例如矽基底)。基底110亦可為介電基底，所述介電基底是由例如氧化矽、氮化矽等介電材料所形成。根據本揭露的一些實施例，無論基底110是否由半導體材料或介電材料形成，皆不具有貫穿基底110的穿孔。
根據本揭露的一些實施例，內連晶粒38不具有主動裝置，例如電晶體及二極體。內連晶粒38可具有或可不具有被動裝置，例如電容器、變壓器、電感器、電阻器等。根據本揭露的替代實施例，內連晶粒38包括一些主動裝置及/或被動裝置(圖中未示出)，且主動裝置可形成於半導體基底110的頂表面處。
內連晶粒38更包括內連結構112，內連結構112更包括介電層114及位於介電層114中的金屬線路及通孔116。介電層114可包括金屬間介電(Inter-Metal Dielectric，IMD)層。根據本揭露的一些實施例，介電層114中的一些下部部分是由介電常數(k值)低於約3.0或約2.5的低介電常數介電材料所形成。介電層114可由黑金剛石(Black Diamond)(應用材料公司(Applied Materials)的註冊商標)、含碳的低介電常數介電材料、氫矽倍半氧烷(Hydrogen SilsesQuioxane，HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane，MSQ)等形成。根據本揭露的一些實施例，介電層114的形成包括：沈積含成孔劑(porogen-containing)的介電材料，並接著執行固化製程以移除成孔劑，且因此剩餘的介電層114為多孔的。在各金屬間介電層114之間形成可由碳化矽、氮化矽等形成的蝕刻終止層(圖中未示出)，且為簡潔起見，未示出所述蝕刻終止層。
在介電層114中形成金屬線路及通孔116。形成製程可包括單鑲嵌(single damascene)製程及雙鑲嵌(dual damascene)製程。在示例性單鑲嵌製程中，在介電層114中的一者中首先形成 溝渠，然後以導電材料來填充所述溝渠。接著執行例如化學機械研磨(Chemical Mechanical Polish，CMP)製程等平坦化製程，以移除導電材料的較所對應的介電層的頂表面高的多餘部分，將金屬線路留在溝渠中。在雙鑲嵌製程中，在金屬間介電層中形成溝渠及通孔開口兩者，使所述通孔開口位於所述溝渠之下且連接至所述溝渠。接著將導電材料填充至溝渠及通孔開口中，以分別形成金屬線路及通孔。導電材料可包括擴散障壁層及位於所述擴散障壁層之上的含銅金屬材料。擴散障壁層可包含鈦、氮化鈦、鉭、氮化鉭等。金屬線路及通孔116亦可包括在鈍化層中所形成的一些部分。
內連晶粒38可更包括位於低介電常數介電層114之上的鈍化層(亦被標示為114)。鈍化層具有對底下的低介電常數介電層(若存在)進行隔離，以免受有害化學物質及水分的不利影響的功能。鈍化層可由例如氧化矽、氮化矽、未摻雜矽酸鹽玻璃(Undoped Silicate Glass，USG)等非低介電常數介電材料所形成。鈍化層中可存在金屬接墊，例如鋁接墊(其可由例如鋁銅來形成)。在內連晶粒38的表面處形成接合接墊(或金屬凸塊)118。
積體被動裝置40可為分離的裝置晶粒，積體被動裝置40可包括半導體基底(圖中未示出)及由所述半導體基底所形成的被動裝置。積體被動裝置40可包括單一個被動裝置且無其他被動裝置及主動裝置。被動裝置可為電容器、電感器、電阻器等，且因此積體被動裝置40可為兩端子式裝置(two-terminal device)。 積體被動裝置40亦可包括變壓器，且因此可為四端子式裝置(four-terminal device)。在積體被動裝置40的表面處形成接合接墊(或金屬凸塊)120。積體被動裝置40與內連晶粒38被設計成具有相似的厚度。
參照圖6，將積體被動裝置40及內連晶粒38包封於包封材料(包封劑)44中，包封材料44可由模製化合物、模製底部填充膠等所形成。相應步驟在圖26所示製程流程中被示出為步驟210。包封材料44可包括基材(base material)及位於所述基材中的填料顆粒，所述基材可為樹脂及/或聚合物。填料顆粒可由例如二氧化矽、氧化鋁等介電材料所形成，且可為球形顆粒。在包封之後，包封材料44覆蓋積體被動裝置40及內連晶粒38。接著執行平坦化製程，以移除積體被動裝置40的多餘部分及內連晶粒38的剩餘部分，進而暴露出接合接墊118及120。平坦化製程可為化學機械研磨製程或機械磨削製程(mechanical grinding process)。根據本揭露的一些實施例，包封材料44在積體被動裝置40及內連晶粒38的下方流動以填充間隙。根據另一些實施例，可存在未被包封材料44填充的一些間隙。舉例而言，圖6示出區域46，區域46可被填充或可不被填充(局部地或完全地)，以作為空氣間隙(air gap)。
根據本揭露的一些實施例，在整個包封材料44內部，不存在有主動裝置的裝置晶粒於其中。舉例而言，積體被動裝置40及內連晶粒38不具有主動裝置。
圖7示出穿孔48的形成，穿孔48貫穿包封材料44，以連接至下方的重佈線36。相應步驟在圖26所示製程流程中被示出為步驟212。所述形成製程包括對包封材料44進行蝕刻以形成開口，所述開口暴露出重佈線36的一些部分。接著以導電材料來填充所述開口，然後進行平坦化製程以移除導電材料的剩餘部分。導電材料可由銅、鋁、鎢、鈷或該些金屬的合金形成。穿孔48可包括或可不包括由氮化鈦、氮化鉭、鈦、鉭等所形成的導電障壁層。根據本揭露的一些實施例，由於製程因素，穿孔48可為錐形，其中上部部分寬於相應的下部部分。
根據本揭露的替代實施例，在圖6所示步驟中，當平坦化製程完成時，接合接墊118及120不被暴露出，而是被包封材料44的剩餘層所覆蓋。更確切而言，接合接墊118及120是在圖7所示平坦化製程之後被暴露出。舉例而言，圖6示出虛線45，虛線45表示在相應的平坦化製程之後包封材料44的頂表面。在圖6所示步驟中使接合接墊118及120保持被覆蓋可防止由兩個平坦化製程造成對接合接墊118及120的過度研磨。
參照圖8，將封裝組件(裝置)50(其可包括50A、50B及50C)接合至積體被動裝置40及內連晶粒38。相應步驟在圖26所示製程流程中被示出為步驟214。將封裝組件50的接合接墊52接合至接合接墊118及120，且所述接合可為銲料接合(solder bonding)或金屬至金屬直接接合(metal-to-metal direct bonding)。封裝組件50中的每一者可為(或包括)裝置晶粒，例如邏輯晶粒， 所述邏輯晶粒可為中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入-輸出(input-output，IO)晶粒、基頻(BaseBand，BB)晶粒或應用處理器(Application processor，AP)晶粒。封裝組件50亦可包括記憶體晶粒，例如動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒或靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒。封裝組件50亦可包括封裝體、記憶體堆疊等。
根據本揭露的一些實施例，內連晶粒38用於對封裝組件50進行側向連接。舉例而言，內連晶粒38A接合至封裝組件50A及50B兩者，且用於對封裝組件50A與50B進行電性內連。內連晶粒38B接合至封裝組件50B及50C兩者，且用於對封裝組件50B與50C進行電性內連。所述內連是藉由金屬線路及通孔116來達成。由於內連晶粒38是使用用於形成半導體晶圓/晶粒的製程來形成，因此可因金屬線路及通孔116的小的寬度及小的間距而形成高密度內連。金屬線路及通孔116的間距可較重佈線36及32的間距小得多。另外，製造成本因使用預先成型的內連晶粒38來進行內連而得到降低。
進一步參照圖8，對底部填充膠54進行點膠。相應步驟在圖26所示製程流程中被示出為步驟216。底部填充膠54可填充裝置晶粒50與下方的包封材料44、內連晶粒38以及積體被動裝置40之間的間隙。底部填充膠54亦可填充相鄰的裝置晶粒50之 間的間隙。此外，位於相鄰的裝置晶粒50之間的底部填充膠54的部分的頂表面較封裝組件50的頂表面低。在本說明通篇中，上覆於離型層22之上的結構被統稱為複合晶圓56。
接下來，複合晶圓56可自載體20剝離，其可例如藉由將例如紫外(ultraviolet，UV)光或雷射等光照射在離型層22上，以分解離型層22。相應步驟在圖26所示製程流程中被示出為步驟218。載體20及離型層22從複合晶圓56移除。所得結構示於圖9中。根據本揭露的一些實施例，將緩衝層24留在複合晶圓56上，且例如藉由雷射鑽孔，以在緩衝層24中形成開口。接著形成銲料區58，以藉由延伸至緩衝層24中的開口中而連接至重佈線26，如圖9所示。由於複合晶圓56是晶圓級，因此可將複合晶圓56單體化(藉由鋸切製程)成多個封裝體60，其中每一封裝體60分別具有圖9所示結構。相應步驟在圖26所示製程流程中被示出為步驟220。所得封裝體60可用於進一步的接合製程，例如，如圖25所示。
圖1至圖9所示製程被稱為先重佈線製程，乃因重佈線26、32及36是在裝置晶粒50的接合/貼合之前形成。圖10至圖20示出根據本揭露一些實施例的封裝體的形成製程中的各中間階段的剖視圖。該些製程被稱為先晶粒製程(die-first process)，乃因裝置晶粒是在重佈線26、32及36形成之前被接合/貼合。除非另外指明，否則該些實施例中的組件的材料及形成方法與在圖1至圖9所示實施例中由相同參考標號標示的相同組件相似。關於 圖10至圖20(以及圖21至圖24)所示組件的形成製程及材料的詳細內容因此可見於對圖1至圖9所示實施例的論述中。圖10至圖20所示步驟亦示意性地反映在圖27所示製程流程300中。
參照圖10，在載體20之上置放封裝組件50(包括封裝組件50A、50B及50C)，且將封裝組件50貼合至離型層22。相應步驟在圖27所示製程流程中被示出為步驟302。聚合物緩衝層24為可形成或可不形成。封裝組件50可包括與參照圖8所論述的裝置類型相似的裝置。根據本揭露的一些實施例，封裝組件50包括接合接墊52及金屬接墊62。金屬接墊62可在與接合接墊52相同的水平高度處形成，或者可相較於接合接墊52凹陷，如圖所示。此外，金屬接墊62可大於接合接墊52。接合接墊52及金屬接墊62兩者電性連接至封裝組件50內部的積體電路裝置/電路(圖中未示出)。
圖11示出將積體被動裝置40A接合至封裝組件50B，將內連晶粒38A接合至封裝組件50A及50B，並將內連晶粒38B接合至封裝組件50B及50C。相應步驟在圖27所示製程流程中被示出為步驟304。內連晶粒38A用作封裝組件50A與50B之間的電性內連線。內連晶粒38B用作封裝組件50B與50C之間的電性內連線。接合可藉由銲料接合、金屬至金屬直接接合等來進行。
接著對底部填充膠54進行點膠，以填充積體被動裝置40A、內連晶粒38、及相應的下方的封裝組件50A、50B及50C之間的間隙。相應步驟在圖27所示製程流程中被示出為步驟 306。此外，底部填充膠54可包括一些部分，其流入相鄰的封裝組件50A、50B及50C之間的間隙中。底部填充膠54的該些部分可與上覆的內連晶粒38重疊。根據本揭露的一些實施例，底部填充膠54的底表面可(或可不)與封裝組件50A、50B及50C的底表面共面。
參照圖12，分配並固化包封材料44。相應步驟在圖27所示製程流程中被示出為步驟308。封裝組件50A、50B及50C、內連晶粒38以及積體被動裝置40A因此被包封於包封材料44中。包封材料44包括：下部部分，其與封裝組件50A、50B及50C處於相同的水平高度處且包圍封裝組件50A、50B及50C；以及上部部分，其高於內連晶粒38及積體被動裝置40A或是與內連晶粒38及積體被動裝置40A處於相同的水平高度處且包圍內連晶粒38及積體被動裝置40A。應理解，封裝製程為晶圓級，因此包封材料44包封多個組件，其與具有封裝組件50A、50B及50C、內連晶粒38以及積體被動裝置40A在內的組件相同。
圖13示出穿孔48的形成，穿孔48貫穿包封材料44以連接至下方的金屬接墊62。相應步驟在圖27所示製程流程中被示出為步驟310。所述形成製程包括對包封材料44進行蝕刻以形成開口，所述開口暴露出金屬接墊62的一些部分。接著以導電材料來填充所述開口，然後進行平坦化製程以移除導電材料的多餘部分。穿孔48的材料及結構可相似於圖7所示穿孔48的材料及結構，於此便不再贅述。根據本揭露的一些實施例，由於製程原因， 穿孔48可為錐形，其中上部部分寬於相應的下部部分。
參照圖14，形成介電層64，介電層64可由例如聚醯亞胺、聚苯並噁唑等聚合物所形成。相應步驟在圖27所示製程流程中被示出為步驟312。另外，介電層64可包括無機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽等。舉例來說，藉由微影製程在介電層64中形成開口66，所述微影製程包括使用微影罩幕對介電層64進行曝光，並接著對介電層64進行顯影。穿孔48暴露至開口66。
接下來，參照圖15，形成重佈線68以連接至穿孔48。相應步驟亦在圖27所示製程流程中被示出為步驟312。材料及形成製程可相似於圖1至圖4所示重佈線26、32及36的形成，因此在本文中便不再贅述。重佈線68包括延伸至介電層64中的通孔部分以及上覆於介電層64之上的跡線(線路)部分。
參照圖16，舉例來說，藉由晶粒貼合膜69，以將積體被動裝置40B貼合於介電層64上。相應步驟在圖27所示製程流程中被示出為步驟314。根據本揭露的一些實施例，並非將積體被動裝置40B貼合至介電層64，而是可將積體被動裝置40B黏著至重佈線68的頂表面。舉例而言，虛線70示意性地示出重佈線68中的一者可延伸之處，且可將積體被動裝置40B及晶粒貼合膜69直接置放於重佈線68的虛線部分70上。積體被動裝置40A及40B可彼此相同或彼此不同。
圖17示出介電層72及延伸至介電層72中的重佈線74 的形成。相應步驟亦在圖27所示製程流程中被示出為步驟316。介電層72可由例如聚醯亞胺、聚苯並噁唑等聚合物所形成，或者可由例如氧化矽、氮化矽、碳化矽、氮氧化矽等無機材料所形成。積體被動裝置40B可被暴露至介電層72之外，或者可被埋入於介電層72中。因此，積體被動裝置40B的接合接墊120可被暴露出或被覆蓋。重佈線74電性連接至重佈線68。
接下來，參照圖18，形成介電層76以覆蓋重佈線74，然後形成重佈線78。相應步驟亦在圖27所示製程流程中被示出為步驟318。介電層76可由選自用於形成介電層64及/或72的相似材料的材料形成。重佈線78包括位於介電層76之上的跡線(金屬線路)以及延伸至介電層76中的開口中的通孔。重佈線78可在鍍覆製程中形成，且所形成的重佈線78中的每一者可包括晶種層(圖中未示出)及位於所述晶種層之上的經鍍覆的金屬材料。
重佈線78的通孔部分亦可包括連接至積體被動裝置40B的接合接墊120的一些部分。因此，積體被動裝置40B電性連接至重佈線78。在一些實施例中，介電層72包括覆蓋積體被動裝置40B的頂表面層，重佈線78中的通孔貫穿介電層76並進一步延伸至介電層72的頂表面層中以接觸接合接墊120。
接下來，在重佈線78之上形成介電層80。相應步驟被示出為圖27所示製程流程中的步驟320。介電層80可使用聚合物來形成，且可選自與介電層64、72及76的材料相同的材料。舉例而言，介電層80可由聚苯並噁唑、聚醯亞胺、苯並環丁烯等來形 成。另外，介電層80可包括無機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽等。
圖19示出銲料區82的形成。相應步驟亦在圖27所示製程流程中被示出為步驟320。所述形成可包括例如藉由雷射鑽孔在介電層80中形成開口。接著形成銲料區82以連接至重佈線78。上覆於離型層22之上的所得結構被稱為複合晶圓56。在後續的步驟中，複合晶圓56自載體20剝離。接下來，藉由鋸穿切割道(scribe line)85來單體化複合晶圓56，以形成多個封裝體60。圖20示出所得的封裝體60。
圖21至圖24示出根據本揭露一些實施例的封裝體的形成製程中的各中間階段的剖視圖。該些製程亦為先晶粒製程，乃因裝置晶粒是在重佈線形成之前被接合/貼合。圖21至圖24所示步驟亦示意性地反映在圖28所示製程流程400中。除了穿孔48是在包封材料形成之前自金屬接墊生長，而非先形成包封材料之後再形成穿孔48於包封材料44中的開口中(如圖12及圖13所示)以外，所述製程相似於圖10至圖20所示製程。
參照圖21，藉由離型層22，以將封裝組件50置放於載體20之上。相應步驟在圖28所示製程流程中被示出為步驟402。介電緩衝層24為可形成或可不形成。接下來，施加光阻86並接著進行圖案化。相應步驟在圖28所示製程流程中被示出為步驟404。在光阻86中形成開口87，以暴露出金屬接墊62的一些部分。接下來，執行鍍覆製程，以形成亦被標示為48的金屬柱。相應步 驟在圖28所示製程流程中被示出為步驟406。由於鍍覆是自金屬接墊62開始，因此不需要晶種層，且自金屬接墊62開始進行鍍覆。接著例如在灰化製程(ashing process)中移除光阻86，且所得的結構示於圖22中。
圖22進一步示出將內連晶粒38及積體被動裝置40A接合至封裝組件50。相應步驟在圖28所示製程流程中被示出為步驟408。所述結構、材料以及製程可相似於圖11所示及參照圖11所論述的結構、材料以及製程。因此在本文中不再贅述。接著對底部填充膠54進行點膠以填充積體被動裝置40A、內連晶粒38以及相應的下方的封裝組件50A、50B及50C之間的間隙。此外，底部填充膠54可包括一些部分，其流入相鄰的封裝組件50A、50B及50C之間的間隙中。底部填充膠54的該些部分可與上覆的內連晶粒38重疊。根據本揭露的一些實施例，底部填充膠54的底表面可(或可不)與封裝組件50A、50B及50C的底表面共面。
圖23示出包封製程，以將封裝組件50A、50B及50C、內連晶粒38以及積體被動裝置40A包封於包封材料44中。相應步驟在圖28所示製程流程中被示出為步驟410。包封材料44亦包括：下部部分，其與封裝組件50A、50B及50C處於相同的水平高度處且包圍封裝組件50A、50B及50C；以及上部部分，其高於內連晶粒38及積體被動裝置40A或是與內連晶粒38及積體被動裝置40A處於相同的水平高度處且包圍內連晶粒38及積體被動裝置40A。應理解，封裝製程為晶圓級，因此包封材料44包封多個 經接合結構，其與包括封裝組件50A、50B及50C、內連晶粒38以及積體被動裝置40A的結構相同。
接著自圖23所示結構開始執行圖14至圖20所示製程步驟。相應步驟在圖28所示製程流程中被示出為步驟412。詳細內容(材料、結構、及形成製程)本質上相同於參照圖14至圖20所示及所述，且在本文中不再予以贅述。所得封裝體60示於圖24中。
圖25示出其中將封裝體60接合至另一封裝組件84，以形成封裝體88的示例性實施例。封裝組件84可為封裝基底、印刷電路板等。應理解，儘管封裝體60被示出為具有圖24所示結構，然而圖9及圖20所示封裝體60亦可以相似的方式接合至封裝組件84以形成封裝體88。根據一些實施例，封裝組件50A、50B及50C中的一些組件包括封裝體或晶粒堆疊。舉例而言，圖25示意性地示出封裝組件50A及50C為包括多個裝置晶粒的晶粒堆疊。
在以上所示示例性實施例中，根據本揭露的一些實施例來論述一些示例性製程及特徵。亦可包括其他特徵及製程。舉例而言，可包括測試結構來幫助對三維(three-dimensional，3D)封裝體或三維積體電路(three-dimensional integrated circuit，3DIC)裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或在基底上形成的測試接墊，所述測試接墊能夠對三維封裝體或三維積體電路進行測試、使用探針及/或探針卡等。所述驗證測試可在中間結構以及最終結構上執行。另外，本文所揭露的結構及方法 可結合測試方法來使用。所述測試方法結合對已知良好晶粒(known good die)進行中間驗證，其可提高良率及降低成本。
本揭露的實施例具有一些有利特徵。藉由使用內連晶粒對置放於同一水平高度處的裝置晶粒(或其他類型的封裝組件)進行內連，不再需要傳統中介層。可使用重佈線將裝置晶粒連接至封裝基底及/或印刷電路板，以使得不再需要在中介層中的矽穿孔。因此會節省與中介層的形成相關聯的高成本。可使用用於形成裝置晶粒的製程來形成內連晶粒，且因此內連線的間距小，進而可達成高密度內連。
根據本揭露的一些實施例，一種方法包括：將第一裝置晶粒及第二裝置晶粒接合至內連晶粒。所述內連晶粒包括：第一部分，位於所述第一裝置晶粒之上且接合至所述第一裝置晶粒；以及第二部分，位於所述第二裝置晶粒之上且接合至所述第二裝置晶粒。所述內連晶粒將所述第一裝置晶粒電性連接至所述第二裝置晶粒。所述方法更包括：將所述內連晶粒包封於包封材料中；以及在所述內連晶粒之上形成多條重佈線。在一實施例中，所述方法更包括形成貫穿所述包封材料的穿孔，以將所述第一裝置晶粒電性連接至所述多條重佈線。在一實施例中，所述方法更包括：所述形成所述穿孔包括：移除所述包封材料的一部分以形成開口，所述第一裝置晶粒的導電接墊外露於所述開口；以及在所述開口中填充導電材料。在一實施例中，所述方法更包括：所述形成所述穿孔包括：形成圖案化光阻，其中所述第一裝置晶粒的導 電接墊外露於所述圖案化光阻中的開口；在所述開口中鍍覆所述穿孔；以及移除所述圖案化光阻，其中在所述圖案化光阻被移除之後，所述包封材料被包封於所述穿孔上。在一實施例中，所述方法更包括：在將所述第一裝置晶粒及所述第二裝置晶粒接合至所述內連晶粒之前形成所述多條重佈線。在一實施例中，所述方法更包括：在將所述第一裝置晶粒及所述第二裝置晶粒接合至所述內連晶粒之後形成所述多條重佈線。在一實施例中，所述方法更包括：將積體被動裝置接合至所述第一裝置晶粒及所述第二裝置晶粒中的一者。
根據本揭露的一些實施例，一種方法包括：在載體之上形成介電層；形成多條重佈線，所述多條重佈線的通孔部分貫穿所述介電層；藉由晶粒貼合膜，以將內連晶粒貼合至所述多條重佈線的表面；將所述內連晶粒包封於包封材料中；以及將第一封裝組件及第二封裝組件接合至所述內連晶粒，其中所述第一封裝組件接合至所述內連晶粒的第一部分，且所述第二封裝組件接合至所述內連晶粒的第二部分。在一實施例中，所述方法更包括：藉由附加晶粒貼合膜，以將積體被動裝置貼合至所述多條重佈線的另外的表面；以及將所述第一封裝組件接合至所述積體被動裝置。在一實施例中，所述方法更包括：形成貫穿所述包封材料的穿孔，其中所述穿孔接合至所述第一封裝組件及所述第二封裝組件中的一者。在一實施例中，所述方法更包括：所述內連晶粒將所述第一封裝組件電性連接至所述第二封裝組件。在一實施例 中，所述方法更包括：所述內連晶粒包括基底，且所述內連晶粒中不具有基底穿孔及主動裝置。在一實施例中，所述方法更包括：所述內連晶粒中更不具有被動裝置。在一實施例中，所述方法更包括：所述晶粒貼合膜接觸所述多條重佈線中的兩條相鄰重佈線的頂表面，且其中在所述內連晶粒被包封於所述包封材料中之後，在所述多條重佈線中的所述兩條相鄰重佈線之間存在空氣間隙。
根據本揭露的一些實施例，一種裝置包括：第一裝置晶粒及第二裝置晶粒；內連晶粒，包括第一部分，位於所述第一裝置晶粒之上且接合至所述第一裝置晶粒；以及第二部分，位於所述第二裝置晶粒之上且接合至所述第二裝置晶粒，其中所述內連晶粒將所述第一裝置晶粒電性連接至所述第二裝置晶粒；包封材料，將所述內連晶粒包封於所述包封材料中；以及穿孔，貫穿所述包封材料以連接至所述第一裝置晶粒。在一實施例中，所述裝置更包括積體被動裝置，其接合至所述第一裝置晶粒及所述第二裝置晶粒中的一者。在一實施例中，所述裝置更包括底部填充膠，所述底部填充膠包括：第一部分，位於所述第一裝置晶粒與所述內連晶粒之間；以及第二部分，位於所述第一裝置晶粒與所述第二裝置晶粒之間。在一實施例中，所述包封材料的頂表面部分位於所述內連晶粒的頂表面之上且接觸所述內連晶粒的所述頂表面。在一實施例中，所述裝置更包括位於所述內連晶粒的頂表面之上且接觸所述內連晶粒的所述頂表面的晶粒貼合膜，其中所述 晶粒貼合膜位於所述包封材料中。在一實施例中，所述穿孔接合至所述第一裝置晶粒及所述第二裝置晶粒中的一者。
前述內容概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，此類等效構造並不背離本揭露的精神及範圍，且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。

Claims (10)

  1. 一種半導體裝置的製造方法，包括：將第一裝置晶粒及第二裝置晶粒直接接合至內連晶粒，其中所述內連晶粒包括：第一部分，位於所述第一裝置晶粒之上且直接接合至所述第一裝置晶粒；以及第二部分，位於所述第二裝置晶粒之上且直接接合至所述第二裝置晶粒，其中所述內連晶粒將所述第一裝置晶粒電性連接至所述第二裝置晶粒；將所述內連晶粒包封於包封材料中；以及在所述內連晶粒之上形成多條重佈線。
  2. 如申請專利範圍第1項所述的半導體裝置的製造方法，更包括形成貫穿所述包封材料的穿孔，以將所述第一裝置晶粒電性連接至所述多條重佈線，其中所述形成所述穿孔包括：移除所述包封材料的一部分以形成開口，所述第一裝置晶粒的導電接墊外露於所述開口；以及在所述開口中填充導電材料。
  3. 如申請專利範圍第1項所述的半導體裝置的製造方法，更包括形成貫穿所述包封材料的穿孔，以將所述第一裝置晶粒電性連接至所述多條重佈線，其中所述形成所述穿孔包括：形成圖案化光阻，其中所述第一裝置晶粒的導電接墊外露於所述圖案化光阻中的開口；在所述開口中鍍覆所述穿孔；以及移除所述圖案化光阻，其中在所述圖案化光阻被移除之後，所述包封材料被包封於所述穿孔上。
  4. 如申請專利範圍第1項所述的半導體裝置的製造方法，其中所述多條重佈線是在將所述第一裝置晶粒及所述第二裝置晶粒接合至所述內連晶粒之前形成，或其中所述多條重佈線是在將所述第一裝置晶粒及所述第二裝置晶粒接合至所述內連晶粒之後形成，或更包括：將積體被動裝置(IPD)接合至所述第一裝置晶粒及所述第二裝置晶粒中的一者。
  5. 一種半導體裝置的製造方法，包括：在載體之上形成介電層；形成多條重佈線，所述多條重佈線的通孔部分貫穿所述介電層；藉由晶粒貼合膜，以將內連晶粒貼合至所述多條重佈線的表面；將所述內連晶粒包封於包封材料中；以及將第一封裝組件及第二封裝組件接合至所述內連晶粒，其中所述第一封裝組件接合至所述內連晶粒的第一部分，且所述第二封裝組件接合至所述內連晶粒的第二部分。
  6. 如申請專利範圍第5項所述的半導體裝置的製造方法，更包括：藉由附加晶粒貼合膜，以將積體被動裝置(IPD)貼合至所述多條重佈線的另外的表面；以及將所述第一封裝組件接合至所述積體被動裝置，或更包括：形成貫穿所述包封材料的穿孔，其中所述穿孔接合至所述第一封裝組件及所述第二封裝組件中的一者。
  7. 如申請專利範圍第5項所述的半導體裝置的製造方法，其中所述內連晶粒將所述第一封裝組件電性連接至所述第二封裝組件，或其中所述內連晶粒包括基底，且所述內連晶粒中不具有基底穿孔及主動裝置，或其中所述內連晶粒中更不具有被動裝置。
  8. 如申請專利範圍第5項所述的半導體裝置的製造方法，其中所述晶粒貼合膜接觸所述多條重佈線中的兩條相鄰重佈線的頂表面，且其中在所述內連晶粒被包封於所述包封材料中之後，在所述多條重佈線中的所述兩條相鄰重佈線之間存在空氣間隙。
  9. 一種半導體裝置，包括：第一裝置晶粒及第二裝置晶粒；內連晶粒，直接接合至所述第一裝置晶粒及所述第二裝置晶粒，其中所述內連晶粒將所述第一裝置晶粒電性連接至所述第二裝置晶粒；包封材料，將所述內連晶粒包封於所述包封材料中；以及穿孔，貫穿所述包封材料以連接至所述第一裝置晶粒。
  10. 如申請專利範圍第9項所述的半導體裝置，更包括積體被動裝置，其接合至所述第一裝置晶粒或所述第二裝置晶粒中的一者，或更包括底部填充膠，所述底部填充膠包括：第一部分，位於所述第一裝置晶粒與所述內連晶粒之間；以及第二部分，位於所述第一裝置晶粒與所述第二裝置晶粒之間，或其中所述包封材料的頂表面部分位於所述內連晶粒的頂表面之上且接觸所述內連晶粒的所述頂表面，或更包括位於所述內連晶粒的頂表面之上且接觸所述內連晶粒的所述頂表面的晶粒貼合膜，其中所述晶粒貼合膜位於所述包封材料中，或其中所述穿孔接合至所述第一裝置晶粒或所述第二裝置晶粒中的一者。
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