CN107408546B - 具有底部填充封围腔的半导体装置组合件 - Google Patents

具有底部填充封围腔的半导体装置组合件 Download PDF

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CN107408546B
CN107408546B CN201680012840.7A CN201680012840A CN107408546B CN 107408546 B CN107408546 B CN 107408546B CN 201680012840 A CN201680012840 A CN 201680012840A CN 107408546 B CN107408546 B CN 107408546B
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semiconductor
cavity
die
semiconductor device
device assembly
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CN107408546A (zh
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A·查杜鲁
W·H·黄
S·S·瓦德哈维卡
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本文揭示具有底部填充封围腔的半导体装置组合件。在一个实施例中，半导体装置组合件可包含第一半导体裸片，所述第一半导体裸片具有由衬底材料形成的基底区域、沿着所述基底区域的凹入表面、由所述衬底材料形成且从所述基底区域突出的外围区域及沿着所述外围区域且与所述凹入表面在所述外围区域中界定腔的侧壁表面。所述半导体装置组合件进一步包含邻近所述腔而附接到所述第一裸片的所述外围区域的热传递结构及至少部分填充所述腔且包含所述外围区域与第二半导体裸片堆叠之间的填角料的底部填充材料。

Description

具有底部填充封围腔的半导体装置组合件
技术领域
所揭示实施例涉及半导体装置组合件，且特定来说涉及，具有底部填充封围腔的半导体装置组合件。
背景技术
包含存储器芯片、微处理器芯片及成像器芯片的封装半导体裸片通常包含安装于衬底上且围封于塑料保护壳体中的半导体裸片。所述裸片包含功能特征(例如存储器单元、处理器电路及成像器装置)以及电连接到所述功能特征的接合垫。接合垫可电连接到保护壳体外部的端子以允许裸片连接到较高级电路。
半导体制造商不断减小裸片封装的大小以装配于电子装置的空间约束内，同时还增加每一封装的功能容量以满足操作参数。用于增加半导体封装的处理能力而基本上不增加由封装覆盖的表面积(即，封装的“占据面积”)的方法是在单个封装中将多个半导体裸片垂直堆叠于彼此的顶部上。可通过使用穿硅通孔(TSV)电耦合个别裸片的接合垫与相邻裸片的接合垫而使此垂直堆叠封装中的裸片互连。
在垂直堆叠的封装中，产生的热难以消散，这增加个别裸片、裸片之间的结及封装整体的操作温度。在许多类型的装置中，这可导致堆叠裸片达到高于其最大操作温度(Tmax)的温度。
附图说明
图1是根据本发明技术的实施例的半导体装置组合件的横截面图。
图2A到2D说明根据本发明技术的实施例制造半导体装置组合件的方法的横截面图。
图2E是说明根据本发明技术的实施例制造半导体装置组合件的方法的横截面图，且图2F是说明根据本发明技术的实施例制造半导体装置组合件的方法的俯视图。
图2G是说明根据本发明技术的实施例制造半导体装置组合件的方法的横截面图，且图2H是说明根据本发明技术的实施例制造半导体装置组合件的方法的俯视图。
图3是根据本发明技术的实施例的半导体装置组合件的俯视图。
图4是根据本发明技术的实施例的包含半导体装置的系统的示意图。
具体实施方式
下文描述具有底部填充封围腔或经配置以包含过量底部填充材料的相关坝特征的堆叠半导体裸片组合件的若干实施例的特定细节。术语“半导体装置”大体上是指包含半导体材料的固态装置。半导体装置可包含举例来说半导体衬底、晶片或从晶片或衬底分割的裸片。贯穿本发明，在半导体裸片的上下文中大体上描述半导体装置，然而，半导体装置不限于半导体裸片。
术语“半导体装置封装”可为指代具有并入到共同封装中的一或多个半导体装置的布置。半导体封装可包含部分或完全囊封至少一个半导体装置的外壳或壳体。半导体装置封装还可包含承载一或多个半导体装置且附接到壳体或以其它方式并入到壳体中的插入器衬底。术语“半导体装置组合件”可指代一或多个半导体装置、半导体装置封装及/或衬底(例如插入器、支撑件或其它适合衬底)的组合件。
如本文中使用，鉴于图中所展示的定向，术语“垂直”、“横向”、“上”及“下”可指代半导体装置中的特征的相对方向或位置。举例来说，“上”或“最上”可指代经定位比另一特征更靠近页面顶部的特征。然而，这些术语可广泛地理解以包含具有其它定向(例如，颠倒或倾斜定向，其中顶部/底部、上方/下方、上面/下面、上/下及左/右可取决于定向而互换)的半导体装置。
图1是根据本发明技术的实施例配置的半导体装置组合件100(“组合件100”)的横截面图。如展示，组合件100包含封装支撑衬底102、衬底102上的第一半导体裸片104、附接到第一裸片104的热传递结构或壳体118及安装到第一裸片104的多个第二半导体裸片106。第一裸片104包含具有凹入表面110的基底区域105、突出远离基底区域105且具有顶部表面115的外围区域112(所属领域的技术人员称为“廊道”或“搁板”)及沿着外围区域112的内部的侧壁表面116。凹入表面110及侧壁表面116在外围区域112内界定底部填充封围腔140。第二裸片106以堆叠108(“裸片堆叠108”)布置于腔140的凹入表面110上且由间隙g1与侧壁表面116分离。在图1展示的实施例中，壳体118包含附接到外围区域112的第一壁部分120及横向延伸于裸片堆叠108上方的第二壁部分124。第一壁部分120及第二壁部分124在腔140上方界定凹槽114(其包含裸片堆叠108的部分)。在其它实施例中，第一半导体裸片104的外围区域112可延伸到最上第二裸片106或高于最上第二裸片106的高度，且壳体118可为不具有第一壁部分120的单个面板。在至少一些实施例中，壳体118经配置以大体上在第一壁部分120处吸收及消散热能远离第一裸片104，且大体上在第二壁部分124处吸收及消散热能远离裸片堆叠108。
第一裸片104及第二裸片106可包含多种类型的半导体组件及功能特征，例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器、其它形式的集成电路存储器、处理电路、成像组件及/或其它半导体特征。在各种实施例中，举例来说，组合件100可经配置为混合存储器立方体(HMC)，其中堆叠第二裸片106是DRAM裸片或提供数据存储的其它存储器裸片，且第一裸片104是在HMC内提供存储器控制(例如DRAM控制)的高速逻辑裸片。在图1中说明的实施例中，第一裸片104包含至少部分延伸到外围区域112中的集成电路128。在一个实施例中，延伸到外围区域112中的集成电路128的部分可包含在操作期间产生相对大量热的一或多个电路组件，例如串行/解串行器(SERDES)电路。在其它实施例中，第一裸片104及第二裸片106可包含其它半导体组件及/或裸片堆叠108中的个别第二裸片106的半导体组件可不同。
组合件100进一步包含介于第二裸片106中的每一者之间及介于第一裸片104与底部第二裸片106之间的底部填充材料130。底部填充材料130可包含延伸到裸片堆叠108与侧壁表面116之间的间隙g1中的过量部分134。过量部分134至少部分覆盖侧壁表面116，且包含填角料132。如下文中更详细描述，侧壁表面116与裸片堆叠108之间的间隙g1可经定大小以在沉积底部填充材料130期间防止或抑制过量底部填充材料134扩散到外围区域112上。在其它装置(其将导热部件附接到下伏裸片的外围区域或隔屏)中，底部填充材料通常在外围区域上方横向扩散。一般来说，与导热部件(例如，壳体118或第一半导体裸片104的衬底材料)相比，底部填充材料通常是不良热导体，且因而，此类装置中的外围区域与传导部件之间的底部填充材料可增加热阻。此外，此类装置中的底部填充材料的填角料产生传导部件与外围区域之间的大间隔，其减小传导部件在外围区域上的覆盖区域。
图1中展示的组合件100的若干实施例因此可提供增强热性质，其降低组合件100中的个别裸片104、106的操作温度使得所述裸片保持低于其指定最大温度(Tmax)。当组合件100布置为HMC时，这可非常有用，因为第一裸片104通常是逻辑裸片且第二裸片106通常是存储器裸片，且逻辑裸片通常以远高于存储器裸片的功率电平(例如5.24W相较于0.628W)操作。此外，在外围区域112中的集成电路128(例如SERDES电路)通常具有高于在存储器裸片下方的逻辑裸片的部分中的集成电路组件的功率密度，这导致外围区域处的较高温度。因而，通过在腔140内包含底部填充材料130，可改进外围区域112与壳体118的第一壁部分120之间的热传递量。
图2A到2H说明根据本发明技术的实施例制造组合件100的方法的方面。图2A是制造组合件100的阶段的横截面图。如展示，第一裸片104(图1)可由半导体衬底250(例如，硅晶片)形成，半导体衬底250已经由例如背部研磨而从第一厚度t1薄化为第二厚度t2。第二厚度t2大体上界定外围区域112的厚度(图1)。厚外围区域112的一个优点在于其可改进第一裸片104的外围处的热消散。此外，厚外围区域112可减小裸片翘曲。在一个实施例中，第二厚度t2可微约300μm。在其它实施例中，第二厚度t2可小于300μm(例如，约200μm)或大于300μm(例如，约500μm)。
如图2A中进一步展示，衬底250可包含多个穿硅通孔(TSV)252，其部分延伸到基底区域105处衬底的前侧表面254中。TSV 252可在先前制造阶段通过在前侧表面254中蚀刻多个孔且接着使用传导材料(例如铜或铜合金)填充孔而形成。每一TSV 252可包含导电材料(例如铜)及包围导电材料以使TSV 252与周围衬底250隔离的电绝缘材料(未展示)。
图2B是说明在衬底250中已蚀刻凹陷以形成侧壁116及凹入表面110(其在外围区域112内且在基底区域105上方界定腔140)之后制造组合件100的方法的后续阶段的横截面图。可通过图案化抗蚀剂材料(未展示)层及使用湿式或干式蚀刻工艺而形成所述凹陷。因此，外围区域112及基底区域105是衬底250的材料的集成区域。举例来说，外围区域及基底区域可都包含硅。在图2B中展示的实施例中，腔140的深度d1经选择使得TSV 252的表面258在腔140的凹入表面110处暴露。在至少一些实施例中，腔深度d1可在约50μm到约200μm(例如100μm)的范围中。在另一实施例中，腔深度d1可为至少200μm。在又另一实施例中，腔深度d1可为至少300μm。
在至少一些实施例中，腔深度d1可基于待定位于腔140内的第二裸片106(图1)的数目及/或第二裸片106的厚度而选择。在若干实施例中，第二裸片106具有在约50μm到约200μm(例如约60μm)的范围中的厚度。在一个实施例中，半导体裸片的整个堆叠(例如三个、四个、六个、八个、十二个、二十个或更多个裸片的堆叠)可定位于腔140中。在另一实施例中，裸片堆叠108的仅一部分定位于腔140中使得一或多个上半导体裸片定位在腔140的顶部上方。举例来说，一半的裸片堆叠、多于一半的堆叠、少于一半的堆叠或堆叠的仅单个裸片可定位于腔140中。此外，腔140的宽度、长度及/或形状可基于裸片堆叠108的大小(例如裸片堆叠108的占据面积)及/或形状而选择。在一个实施例中，腔140及裸片堆叠108具有类似平面形状(例如正方形或矩形形状)。
图2C是说明在外围区域112的顶部表面115及基底区域105的凹入表面110上已沉积电介质材料260之后且还在基底区域105处在TSV 252上形成第一接合垫262之后制造组合件100的方法的后续阶段的横截面图。电介质材料260可包含举例来说保形膜(例如氧化硅膜)，其覆盖在腔140的基底处的凹入表面110。可通过图案化电介质材料260以暴露TSV252且接着将传导材料(例如铜)电镀于经暴露TSV 252上而形成第一接合垫262。
图2D是说明在将裸片堆叠108定位在凹入表面110处的接合垫262上之后制造组合件100的方法的后续阶段的横截面图。如图2D中展示，底部第二裸片106包含第二接合垫268及将第二接合垫268连接到第一裸片104的对应第一接合垫262的多个导电元件264。第二接合垫268又可耦合到TSV 266(其延伸穿过底部第二裸片106)，且TSV 266可在裸片堆叠108的每一层级耦合到额外传导元件264、接合垫268及TSV 266。导电元件264可具有多种适合结构(例如支柱、柱、支杆、凸块)且可由铜、镍、焊料(例如基于SnAg的焊料)制成。除电通信之外，导电元件264及TSV 252、266还可提供热导管，可通过所述热导管将热传递远离第一裸片104及第二裸片106。
图2E是说明已在第二裸片106之间及第一裸片104与底部第二裸片106之间沉积底部填充材料130之后制造组合件100的方法的另一阶段的横截面图，且图2F是说明所述另一阶段的俯视图。一起参考图2E及2F，底部填充材料130通常是填充第二裸片106与导电元件264之间的空隙空间的可流动材料。在一个实施例中，可通过将底部填充材料130微喷射于个别第二裸片106之间而将底部填充材料注入到空隙空间中。底部填充材料130的体积经选择以充分填充空隙空间，使得过量底部填充材料134进入侧壁表面116与裸片堆叠108之间的间隙g1中以形成填角料132。间隙g1的大小及/或腔深度d1可经选择以防止或抑制过量底部填充材料134流动到外围区域112的顶部表面115上且容纳底部填充材料130的填角料132。在某些实施例中，在底部填充材料130未完全填充间隙g1的情况中，可暴露侧壁表面116的部分236。在至少一些实施例中，底部填充材料130可为非传导环氧膏(例如由日本，新泻县，纳美仕公司(Namics Corporation)制造的XS8448-171)、毛细底部填充物、非传导膜、模制底部填充物及/或包含其它适合电绝缘材料。底部填充材料130可替代性地为电介质底部填充物(例如由德国杜塞尔多夫(Düsseldorf)的汉高(Henkel)制造的FP4585)。在一些实施例中，底部填充材料130可基于其导热性而选择以增强通过裸片堆叠108的热消散。
图2G是说明在已将壳体118附接到第一裸片104的外围区域112之后制造组合件100的方法的另一阶段的横截面图，且图2H是说明所述另一阶段的俯视图。首先参考图2G，壳体118的第一壁部分120通过第一粘合剂222附接到外围区域112的顶部表面115，且壳体118的第二壁部分124通过第二粘合剂226附接到顶部第二裸片106。粘合剂222及226可为相同粘合剂，或其可彼此不同。举例来说，第一粘合剂222及第二粘合剂226可为热界面材料(“TIM”)或另一适合粘合剂。举例来说，TIM及其它粘合剂可包含基于聚硅硅酮的油脂、凝胶或掺杂有传导材料(例如碳纳米管、焊料材料、类钻石碳(DLC)等)以及相变材料的粘合剂。在若干实施例中，壳体118由导热材料(例如镍、铜、铝、具有高热导性的陶瓷材料(例如氮化铝))及/或其它适合的导热材料制成。
在所说明实施例中，壳体118的凹槽114具有符合裸片堆叠108的形状的形状。在此类情况下，凹槽114具有高度h1(其基于待定位于壳体118中的第二裸片106的数目而选择)，且第一壁部分120由间隙g2与裸片堆叠108隔开，间隙g2经配置以在裸片堆叠108与第一壁部分120的内表面270之间提供足够空间以容纳填角料132。在一个实施例中，壳体118不与底部填充材料130接触。在至少一些实施例中，第一壁部分120的宽度w1可经选择使得第一壁部分覆盖显著百分比的外围区域112。在这些及其它实施例中，第一壁部分120的内表面270可基本上与侧壁表面116共面。参考图2H，第一壁部分120可经配置以围绕裸片堆叠108的至少一部分延伸。在其它实施例中，壳体118并未经配置以符合裸片堆叠108的形状。
图3是根据本发明技术的实施例的半导体装置组合件300(“组合件300”)的另一实施例的横截面俯视图。组合件300的若干特征与上文关于组合件100描述的特征类似。举例来说，组合件300可包含定位于第一半导体裸片304的腔340中的第二半导体裸片的裸片堆叠108。然而，在图3中说明的实施例中，第一裸片304包含面向裸片堆叠108的第一侧壁表面316及成角度远离第一侧壁表面316的第二侧壁表面317。过量底部填充材料134至少部分覆盖第一侧壁表面316及第二侧壁表面317。在图3中说明的实施例的一个方面中，第二侧壁317可增加腔340的体积以包含多于图1中展示的腔140的过量底部填充材料134。在相关实施例中，可使用第二侧壁317以增加腔340的体积而不增加腔深度d1(图2B)。
可将上文参考图1到3描述的堆叠半导体装置组合件中的任一者并入无数个更大及/或更复杂系统中的任一者中，其代表性实例是图4中示意性展示的系统480。系统480可包含半导体装置组合件400、电源482、驱动器484、处理器486及/或其它子系统或组件488。半导体装置组合件400可包含大体上与上文参考图1到3描述的半导体装置组合件的特征类似的特征，且因此可包含增强热消散的多种特征。所得系统480可执行任何广泛多种功能，例如存储器存储、数据处理及/或其它适合功能。因此，代表性系统480可包含(不限于)手持式装置(例如移动电话、平板计算机、数字读取器及数字音频播放器)、计算机、车辆、家电及其它产品。可将系统480的组件容置于单个单元中或分布于多个互连单元(例如通过通信网络)上。系统480的组件还可包含远程装置及任何广泛多种计算机可读媒体。
从前述内容，应了解，出于说明目的已在本文中描述本发明技术的特定实施例，但在不偏离本发明的情况下可作出多种修改。举例来说，在一个实施例中，可将底部填充封围腔140定位成偏离中心，且所述腔的一个侧上的外围区域112可大于另一侧上的外围区域。此外，虽然关于HMC描述半导体裸片组合件的许多实施例，但在其它实施例中，半导体裸片组合件可经配置为其它存储器装置或其它类型的堆叠裸片组合件。另外，也可在其它实施例中组合或消除在特定实施例的上下文中描述的新技术的一些方面。此外，虽然已在所述实施例的上下文中描述与新技术的特定实施例相关联的优点，但其它实施例也可展现此类优点且并非所有实施例需要展现此类优点以落在本发明技术的范围内。因此，本发明及相关联技术可涵盖本文中未明确展示或描述的其它实施例。

Claims (35)

1.一种半导体装置组合件，其包括：
第一半导体裸片，其具有由衬底材料形成的基底区域、沿着所述基底区域的凹入表面、由所述衬底材料形成且从所述基底区域突出的外围区域及沿着所述外围区域的侧壁表面，且其中所述凹入表面及所述侧壁表面在所述外围区域内界定腔；
第二半导体裸片堆叠，其至少部分在所述腔中；
热传递结构，其附接到第一半导体裸片的所述外围区域上；及
底部填充材料，其至少部分填充所述腔且包含所述外围区域与所述第二半导体裸片堆叠之间的填角料，其中
所述侧壁表面向内面向所述第二半导体裸片堆叠；且
所述热传递结构包含大体上与所述侧壁表面共面的内表面。
2.根据权利要求1所述的半导体装置组合件，其中所述侧壁表面包含暴露的一部分。
3.根据权利要求2所述的半导体装置组合件，其中所述填角料包含介于所述侧壁表面与所述第二半导体裸片堆叠之间的第一部分，及介于所述热传递结构与所述第二半导体裸片堆叠之间的第二部分。
4.根据权利要求1所述的半导体装置组合件，其中：
所述侧壁表面界定面向所述第二半导体裸片堆叠的第一侧壁表面且所述第一半导体裸片进一步包含以非零角度延伸远离所述第一侧壁表面的第二侧壁表面；及
所述底部填充材料，其至少部分覆盖所述第一侧壁表面及所述第二侧壁表面。
5.根据权利要求1所述的半导体装置组合件，其中：
所述热传递结构包含界定凹槽的第一壁部分及第二壁部分；及
所述第二半导体裸片中的至少一者定位于所述凹槽内。
6.根据权利要求1所述的半导体装置组合件，其中所述第一半导体裸片包含延伸穿过基底区域的多个穿硅通孔，且所述穿硅通孔电耦合到所述第二半导体裸片堆叠。
7.根据权利要求1所述的半导体装置组合件，其中所述第一半导体裸片包含集成电路。
8.根据权利要求7所述的半导体装置组合件，其中所述集成电路至少部分定位于所述外围区域中。
9.根据权利要求7所述的半导体装置组合件，其中：
所述集成电路是逻辑电路；且
所述第二半导体裸片是存储器裸片。
10.根据权利要求1所述的半导体装置组合件，其中所述腔具有至少200μm的深度。
11.根据权利要求10所述的半导体装置组合件，其中所述第二半导体裸片各自具有在50μm到200μm的范围中的厚度。
12.根据权利要求1所述的半导体装置组合件，其中所述腔具有至少300μm的深度。
13.根据权利要求1所述的半导体装置组合件，其中所述第二半导体裸片堆叠包含所述腔中的至少两个半导体裸片。
14.一种半导体装置组合件，其包括：
逻辑裸片，其具有腔；
第一存储器裸片，其在所述腔中；
热传递结构，其附接到所述逻辑裸片；
第二存储器裸片，其在所述第一存储器裸片上；及
底部填充材料，其介于所述第一存储器裸片与所述第二存储器裸片之间且至少部分填充所述腔，其中
所述逻辑裸片包含邻近所述热传递结构且由间隙与所述第一存储器裸片分离的侧壁表面；
所述侧壁表面向内面向所述第一存储器裸片；且
所述热传递结构包含大体上与所述侧壁表面共面的内表面。
15.根据权利要求14所述的半导体装置组合件，其进一步包括在所述第一存储器裸片下方且延伸穿过所述逻辑裸片的多个穿硅通孔。
16.根据权利要求14所述的半导体装置组合件，其中：
所述底部填充材料包含至少在所述间隙中的填角料。
17.根据权利要求14所述的半导体装置组合件，其中所述热传递结构附接到所述第二存储器裸片。
18.根据权利要求14所述的半导体装置组合件，其中所述热传递结构不接触所述底部填充材料。
19.根据权利要求14所述的半导体装置组合件，其中所述逻辑裸片包含：
外围区域，其邻近所述腔且附接到所述热传递结构；及
集成电路组件，其至少部分定位于所述外围区域中。
20.根据权利要求19所述的半导体装置组合件，其中所述集成电路组件包含串行/解串行器电路。
21.一种形成半导体装置组合件的方法，其包括：
在半导体衬底中形成腔，其中所述腔由所述半导体衬底的凹入表面和侧壁表面界定；
将半导体裸片堆叠附接到所述腔中的所述凹入表面；
将底部填充材料沉积于所述半导体裸片堆叠的个别半导体裸片之间；
在所述半导体裸片堆叠与邻近所述腔的所述衬底的外围区域之间积累过量底部填充材料；及
将热传递结构附接到所述外围区域，其中
所述侧壁表面向内面向所述半导体裸片堆叠；且
所述热传递结构包含大体上与所述侧壁表面共面的内表面。
22.根据权利要求21所述的方法，其中沉积所述底部填充材料包含：在所述个别半导体裸片之间注入所述底部填充材料。
23.根据权利要求21所述的方法，其进一步包括：将所述热传递结构附接到所述半导体裸片堆叠。
24.根据权利要求21所述的方法，其中形成所述腔包含：将孔蚀刻到所述衬底中达至少200μm的深度。
25.根据权利要求24所述的方法，其进一步包括：使所述衬底薄化到300μm或更小的厚度。
26.根据权利要求21所述的方法，其中形成所述腔包含：将孔蚀刻到所述衬底中达至少300μm的深度。
27.根据权利要求21所述的方法，其中：
形成所述腔包含在所述衬底中蚀刻孔以在所述腔的基底处暴露多个穿硅通孔TSV；及
附接所述半导体裸片堆叠包含将所述堆叠中的所述半导体裸片的最底部半导体裸片的接合垫接合到所述TSV。
28.根据权利要求21所述的方法，其中所述半导体衬底包含集成电路。
29.根据权利要求21所述的方法，其中附接所述热传递结构包含：将所述半导体裸片中的至少一者定位于所述热传递结构的凹槽中。
30.一种形成半导体装置组合件的方法，其包括：
将存储器裸片堆叠至少部分定位于逻辑裸片的腔中，其中所述腔由所述逻辑裸片的凹入表面和侧壁表面界定；
用底部填充材料至少部分填充所述腔；
将所述存储器裸片中的至少一者定位于热传递结构的凹槽中；及
将所述热传递结构附接到所述逻辑裸片邻近所述腔的外围区域，其中
所述侧壁表面向内面向所述存储器裸片堆叠；且
所述热传递结构包含大体上与所述侧壁表面共面的内表面。
31.根据权利要求30所述的方法，其中用所述底部填充材料至少部分填充所述腔包含：使过量底部填充材料流动到所述存储器裸片堆叠与所述外围区域之间的间隙中。
32.根据权利要求30所述的方法，其进一步包括：将所述存储器裸片堆叠电耦合到所述腔的基底处的多个穿硅通孔。
33.根据权利要求30所述的方法，其进一步包括：将所述热传递结构附接到所述存储器裸片的所述至少一者。
34.根据权利要求30所述的方法，其中所述逻辑裸片包含至少部分定位于所述外围区域中的集成电路组件。
35.根据权利要求34所述的方法，其中所述集成电路组件包含串行/解串行器电路。
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US9397078B1 (en) 2016-07-19
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