TWI588915B - 製造具有高效率散熱路徑之堆疊式半導體晶粒總成之方法 - Google Patents

製造具有高效率散熱路徑之堆疊式半導體晶粒總成之方法 Download PDF

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TWI588915B
TWI588915B TW104121887A TW104121887A TWI588915B TW I588915 B TWI588915 B TW I588915B TW 104121887 A TW104121887 A TW 104121887A TW 104121887 A TW104121887 A TW 104121887A TW I588915 B TWI588915 B TW I588915B
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die
heat transfer
transfer structure
peripheral region
underfill material
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TW104121887A
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TW201606886A (zh
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沙彌爾Ｓ 維哈卡
李曉
史蒂芬Ｋ 古斯厄斯
李健
傑斯皮德Ｓ 甘德席
詹姆士Ｍ 戴德里安
大衛Ｒ 亨布里
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美光科技公司
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Description

製造具有高效率散熱路徑之堆疊式半導體晶粒總成之方法
所揭示實施例係關於半導體晶粒總成。特定言之，本技術係關於具有高效率散熱路徑之堆疊式半導體晶粒總成及相關聯之系統及方法。
包含記憶體晶片、微處理器晶片及成像器晶片之封裝式半導體晶粒通常包含安裝在一基板上且被包納在一塑膠保護罩中之一半導體晶粒。晶粒包含功能特徵，諸如記憶體單元、處理器電路及成像器裝置，以及電連接至功能特徵之結合襯墊。結合襯墊可電連接至保護罩外部之終端以允許晶粒連接至較高階層電路。
市場壓力不斷驅使半導體製造商減小晶粒封裝之大小以裝配在電子裝置之空間約束內，同時亦施壓於其等以增加每一封裝之功能容量以滿足操作參數。用於增加一半導體封裝之處理能力而不實質上增加由封裝覆蓋之表面積(即，封裝的「佔據面積」)之一種方法係在一單個封裝中將多個半導體晶粒垂直堆疊在彼此的頂部上。此等垂直堆疊式封裝中之晶粒可藉由使用穿矽通孔(TSV)電耦合個別晶粒之結合襯墊與相鄰晶粒之結合襯墊而互連。
與垂直堆疊式晶粒封裝相關聯之一項挑戰在於來自個別晶粒之 熱量係加成性且難以耗散由堆疊式晶粒產生之彙總熱量。總之，此增加個別晶粒、晶粒之間之接面及封裝之操作溫度，這可造成堆疊式晶粒達到高於其等最大操作溫度(Tmax)之溫度。問題亦由於封裝中之晶粒之密度增加而惡化。此外，當裝置在晶粒堆疊中具有不同類型的晶粒時，裝置之最大操作溫度被限制於具有最低的最大操作溫度之晶粒。
100‧‧‧半導體晶粒總成
102‧‧‧封裝支撐基板
103a‧‧‧第一側
103b‧‧‧第二側
104a‧‧‧電連接器
104b‧‧‧電連接器
110‧‧‧第一半導體晶粒
111‧‧‧安裝區域
112‧‧‧周邊區域
114‧‧‧前向表面
120‧‧‧第二半導體晶粒
122‧‧‧堆疊
124‧‧‧導電元件
126‧‧‧穿矽通孔(TSV)
128‧‧‧熱傳導元件
130‧‧‧熱傳遞結構(TTS)
131‧‧‧第一部分
132‧‧‧第二部分
133‧‧‧黏附劑
138‧‧‧腔
142‧‧‧基座
144‧‧‧凸肩
146‧‧‧側壁
148‧‧‧黏附劑
152‧‧‧頂部
154‧‧‧底部
156‧‧‧側壁
160‧‧‧底部填充材料
162‧‧‧填角料
400‧‧‧半導體晶粒總成
430‧‧‧內部殼體
431‧‧‧第一支撐件
432‧‧‧第二支撐件
433‧‧‧第一內表面
434‧‧‧第二內表面
435‧‧‧頂部
436‧‧‧腔
440‧‧‧外部殼體
442‧‧‧側壁
444‧‧‧內表面
446‧‧‧頂部
448‧‧‧腔
500‧‧‧半導體裝置總成
530‧‧‧熱傳遞結構(TTS)
532‧‧‧頂部
534‧‧‧側壁
535‧‧‧內表面
536‧‧‧基座
537‧‧‧凸肩
538‧‧‧腔
539‧‧‧內表面
540a‧‧‧入口
540b‧‧‧出口
600‧‧‧半導體晶粒總成
630‧‧‧熱傳遞結構(TTS)
632‧‧‧頂部/頂部組件
634‧‧‧側壁
636‧‧‧內表面
638‧‧‧腔
640a‧‧‧入口
640b‧‧‧出口
670‧‧‧熱傳導介電液體
900‧‧‧半導體晶粒總成
910a‧‧‧入口
910b‧‧‧出口
1000‧‧‧系統
1010‧‧‧半導體晶粒總成
1020‧‧‧電源
1030‧‧‧驅動器
1040‧‧‧處理器
1050‧‧‧其他子系統或組件
C‧‧‧覆蓋面積
F‧‧‧箭頭
G‧‧‧間隙
H1‧‧‧高度
H2‧‧‧高度
L1‧‧‧第二晶粒之長度
L2‧‧‧第一晶粒之長度
圖1係圖解說明根據本技術之實施例之一半導體晶粒總成之一截面圖。
圖2A係圖解說明製造根據本技術之實施例之一半導體晶粒總成之一方法之一截面圖，且圖2B係圖解說明該方法之一俯視平面圖。
圖2C係圖解說明製造根據本技術之實施例之一半導體晶粒總成之一方法之一截面圖，且圖2D係圖解說明該方法之一俯視平面圖。
圖2E及圖2F係圖解說明製造根據本技術之實施例之一半導體晶粒總成之一方法之截面圖。
圖3係圖解說明根據本技術之實施例之一半導體晶粒總成之一截面圖。
圖4A係圖解說明製造根據本技術之實施例之一半導體晶粒總成之一方法之一截面圖，且圖4B係圖解說明該方法之一俯視平面圖。
圖4C係圖解說明製造根據本技術之實施例之一半導體晶粒總成之一方法之一截面圖。
圖4D係圖解說明製造根據本技術之實施例之一半導體晶粒總成之一方法之一截面圖，且圖4E係圖解說明該方法之一俯視平面圖。
圖5A係根據本技術之實施例之一半導體晶粒總成之一截面圖且圖5B係該半導體晶粒總成之一俯視平面圖。
圖6係根據本技術之實施例之一半導體晶粒總成之一截面圖。
圖7係根據本技術之實施例之一半導體晶粒總成之一截面圖。
圖8係根據本技術之實施例之一半導體晶粒總成之一截面圖。
圖9係根據本技術之實施例之一半導體晶粒總成之一截面圖。
圖10係包含根據本技術之實施例組態之一半導體晶粒總成之一系統之一示意圖。
下文描述具有高效率散熱路徑之堆疊式半導體晶粒總成及相關聯之系統及方法之若干實施例之具體細節。術語「半導體晶粒」通常係指具有積體電路或組件、資料儲存元件、處理組件及/或製造在半導體基板上之其他特徵之一晶粒。例如，半導體晶粒可包含積體電路記憶體及/或邏輯電路。半導體晶粒及/或半導體晶粒封裝中之其他特徵可被視為彼此「熱接觸」，前提係該兩種結構可經由例如傳導、對流及/或輻射透過熱量交換能量。熟習相關技術者亦將瞭解，本技術可具有額外實施例，且本技術可在無下文參考圖1至圖10描述之實施例之若干細節的情況下實踐。
如本文中使用，鑑於圖中所示之定向，術語「垂直」、「橫向」、「上部」及「下部」可能係指半導體晶粒總成中之特徵之相對方向或位置。例如，「上部」或「最上面」可能係指經定位比一特徵更接近一頁面之頂部之另一特徵。然而，此等術語應被大概解釋為包含具有其他定向(諸如顛倒或傾斜定向，其中頂部/底部、上方/下方、以上/以下、上/下及左/右取決於定向可互換)之半導體裝置。
圖1係圖解說明根據本技術之一實施例之一半導體晶粒總成100(「總成100」)之一截面圖。總成100可包含一封裝支撐基板102、安裝至封裝支撐基板102之一第一半導體晶粒110，及在一堆疊區域(諸如第一晶粒110之一中心區域或一偏心區域)處配置在一堆疊122中之複數個第二半導體晶粒120。第一晶粒110可進一步包含在第二晶粒 120之外側橫向之一周邊區域112及一熱傳遞結構(TTS)130，熱傳遞結構130具有由一黏附劑133附接至第一晶粒110之周邊區域112之一第一部分131及覆蓋、圍封或以其他方式在第二晶粒120之堆疊122上方之一第二部分132。例如，黏附劑133可為一散熱介面材料(「TIM」)或另一適當黏附劑。例如，TIM及其他黏附劑可包含基於聚矽氧之油脂、凝膠或摻雜有導電材料(例如，碳奈米管、焊錫材料、類鑽石碳(DLC)等等)之黏附劑，以及相變材料。在圖1中圖解說明之實施例中，第一部分131係至少自第一晶粒110之周邊區域112延伸至第二晶粒120之堆疊122之一中間高度處之一高度之一底座，諸如一屏障部件。第二部分132係由黏附劑133附接至第一部分131及最上面第二晶粒120之一罩。第一部分131及第二部分132可一起界定由一金屬(例如，銅或鋁)或其他高熱傳導材料製成之一殼體，且第一部分131及第二部分132可一起界定其中定位有第二晶粒120之堆疊122之一腔138。
總成100進一步包含第二晶粒120之各者之間及第一晶粒110與底部第二晶粒120之間之一底部填充材料160。底部填充材料160可在靠近第一晶粒110之一區域中形成自第二晶粒120之堆疊122向外延伸之一填角料162。總成100預期提供來自第一晶粒110及第二晶粒120之堆疊122之熱量之增強熱耗散。例如，TTS 130可由具有高熱傳導率之一材料製成以沿直接自第一晶粒110之周邊區域112之一大部分之一第一路徑且沿穿過第二晶粒120之一第二路徑有效地傳遞熱量。TTS 130之第一部分131附接至第一晶粒110之周邊區域112之可用區域之一大的百分比，因為第一部分131提供一屏障，該屏障防止底部填充材料160之填角料162覆蓋周邊區域112之一顯著百分比。此增強第一熱路徑之效率，因為與其中在第一部分131附接至第一晶粒110之周邊區域112之前沈積底部填充材料之裝置相比，TTS 130之第一部分131可覆蓋周邊區域112之更多表面區域。
圖1中所示之總成100之若干實施例可因此提供增強的散熱性質，其等降低總成100中之個別晶粒110、120之操作溫度使得該等晶粒保持在其等指定最大溫度(Tmax)以下。當總成100被配置為一混合記憶體立方體(HMC)時此可極為有用，因為第一晶粒110通常係一較大襯底邏輯晶粒，且第二晶粒120通常係記憶體晶粒，且邏輯晶粒通常係以遠高於記憶體晶粒之一功率等級操作(例如，與0.628W相比的5.24W)。邏輯晶粒HMC組態通常將大量熱量集中在第一晶粒110之周邊區域112處。邏輯晶粒亦可在周邊區域處具有較大功率密度，從而造成周邊區域處進一步集中熱量且溫度較高。因而，藉由將第一晶粒110之周邊區域112之一大的百分比耦合至TTS 130之高度傳導第一部分131，熱量可有效地自第一晶粒之周邊區域112移除。
圖2A至圖2F圖解說明製造根據本技術之實施例之總成100之一方法之態樣。圖2A係製造總成100之一階段之一截面圖且圖2B係該階段之一俯視平面圖。參考圖2A，封裝支撐基板102經組態以將第一晶粒110及第二晶粒120連接至較高階層封裝(未展示)之外部電組件。例如，封裝支撐基板102可為一中介板或印刷電路板，其包含半導體組件(例如，經摻雜矽晶圓或砷化鎵晶圓)、不導電組件(例如，各種陶瓷基板，諸如氧化鋁(Al2O3)、氮化鋁(AlN)等等)，及/或導電部分(例如，互連電路、TSV等等)。在圖2A中圖解說明之實施例中，封裝支撐基板102在封裝支撐基板102之一第一側103a處經由第一複數個電連接器104a電耦合至第一晶粒110，且在封裝支撐基板102之一第二側103b處經由第二複數個電連接器104b電耦合至外部電路(未展示)(電連接器104a及電連接器104b統稱為「電連接器104」)。電連接器104可為焊球、導電凸塊及支柱、導電環氧樹脂，及/或其他適當的導電元件。在各個實施例中，封裝支撐基板102可由具有相對較高熱傳導率之一材料製成以增強第一半導體晶粒110之背側處之熱耗散。
如圖2A及圖2B中所示，第一晶粒110可具有大於堆疊式第二晶粒120之一佔據面積。第一晶粒110因此包含一安裝區域111(圖2A)或堆疊區域，在堆疊區域中，第二晶粒120附接至第一晶粒110且周邊區域112向外橫向延伸超出安裝區域111之至少一側。周邊區域112因此係在第二晶粒120外側(例如，超出第二晶粒120之長度及/或寬度)。
第一晶粒110及第二晶粒120可包含各種類型的半導體組件及功能特徵，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式的積體電路記憶體、處理電路、成像組件，及/或其他半導體特徵。在各個實施例中，例如，總成100可被組態為一HMC，其中堆疊式第二晶粒120係DRAM晶粒或提供資料儲存之其他記憶體晶粒，且第一晶粒110係提供HMC內之記憶體控制(例如DRAM控制)之一高速邏輯晶粒。在其他實施例中，第一晶粒110及第二晶粒120可包含其他半導體組件，及/或堆疊122中之個別第二晶粒120之半導體組件可不同。
第一晶粒110及第二晶粒120可為矩形、圓形及/或其他適當形狀，且可具有各種不同尺寸。例如，個別第二晶粒120可各自具有大約10mm到11mm(例如，10.7mm)之一長度L1及大約8mm到9mm(例如，8.6mm、8.7mm)之一寬度。第一晶粒110可具有大約12mm到13mm(例如，12.67mm)之一長度L2及大約8mm到9mm(例如，8.5mm、8.6mm等等)之一寬度。在其他實施例中，第一晶粒110及第二晶粒120可具有其他適當尺寸，及/或個別第二晶粒120可具有彼此不同之尺寸。
第一晶粒110之周邊區域112(被熟習此項技術者稱為一「門廊」(porch)或「擱板」(shelf))可由第一晶粒110及第二晶粒120之相對尺寸及第一晶粒110之一前向表面114上之堆疊122之位置來界定。在圖2A及圖2B中圖解說明之實施例中，堆疊122相對於第一晶粒110之長度L2 居中，使得周邊區域112橫向地延伸超出堆疊122之兩個相對側。例如，若第一晶粒110之長度L2比第二晶粒120之長度L1大大約1.0mm，則周邊區域112將延伸超出居中第二晶粒120之任一側大約0.5mm。堆疊122亦可相對於第一晶粒110之寬度居中，且在其中第一晶粒110之寬度及長度兩者皆大於居中堆疊122之實施例中，周邊區域112可圍繞第二晶粒120之整個周長延伸。在其他實施例中，堆疊122可相對於第一晶粒110之前向表面114(圖2A)偏移，及/或第一晶粒110之周邊區域112可圍繞小於堆疊122之全周長延伸。在進一步實施例中，第一晶粒110及第二晶粒120可為圓形，且因此第一晶粒110及第二晶粒120之相對直徑界定周邊區域112。
如圖2A中所示，第二晶粒120可在堆疊122中彼此電耦合，且由定位在相鄰晶粒110、120之間之複數個導電元件124電耦合至襯底第一晶粒110。雖然圖1中所示之堆疊122包含電耦合在一起之8個第二晶粒120，但是在其他實施例中，堆疊122可包含多於或少於8個晶粒(例如，2至4個晶粒，或至少9個晶粒等等)。導電元件124可具有各種適當結構，諸如支柱、柱、支桿、凸塊，且可由銅、鎳、焊錫(例如，基於SnAg之焊錫)、填充導體之環氧樹脂及/或其他導電材料製成。在選定實施例中，例如，導電元件124可為銅柱，而在其他實施例中，導電元件124可包含更複雜的結構，諸如氮化物上凸塊(bump-on-nitride)結構。
如圖2A中進一步所示，個別第二晶粒120可各自包含複數個TSV 126，其等在一或兩側上與對應導電元件124對準以在第二晶粒120之相對側處提供電連接。每一TSV 126可包含完全行進穿過個別第二晶粒120之一導電材料(例如，銅)及一電絕緣材料，該電絕緣材料包圍導電材料以電隔離TSV 126與第二晶粒120之剩餘部分。雖然圖1中未展示，但是第一晶粒110亦可包含將第一晶粒110電耦合至較高階層電 路之複數個TSV 126。在電通信之外，TSV 126及導電元件124提供散熱導管，熱量可透過散熱導管被傳遞遠離第一晶粒110及第二晶粒120(例如，通過第一散熱路徑)。在一些實施例中，導電元件124及/或TSV 126之尺寸可增加以增強垂直通過堆疊122之熱傳遞。例如，個別導電元件124可各自具有大約15μm至30μm之一直徑或其他適當尺寸以增強穿過晶粒110、120之散熱通路。在其他實施例中，第二晶粒120可彼此電耦合且使用亦可提供穿過堆疊122之散熱通路之其他類型的電連接器(例如導線結合)電耦合至第一晶粒110。
在各個實施例中，總成100亦可包含填隙地定位在導電元件124之間的複數個熱傳導元件128(以虛線展示)。個別熱傳導元件128在結構及組份方面可至少通常類似於導電元件124(例如銅柱)。然而，熱傳導元件128並未電耦合至TSV 126或晶粒110及120之其他電活性組件，且因此不提供第二晶粒120之間的電連接。相反地，熱傳導元件128係電隔離「啞元件」，其等增加通過堆疊122之整體熱傳導率以增強沿第一散熱路徑之熱傳遞。例如，在其中總成100被配置為一HMC之實施例中，導電元件124之間添加熱傳導元件128已被示為將HMC之操作溫度降低若干度(例如大約6℃至7℃)。
圖2C係圖解說明用於在TTS 130(圖1)之第一部分131附接至第一晶粒110及封裝支撐基板102之後製造總成100之一方法之一後續階段之一截面圖，且圖2D係圖解說明該後續階段之一俯視平面圖。參考圖2C，第一部分131之此實施例具有經組態以圍繞第一晶粒110之至少一部分延伸之一基座142(例如，基腳)及經組態以定位在第一晶粒110之周邊區域112上方之一凸肩144。第一部分131可進一步包含延伸至相對於第二晶粒120之堆疊122之一高度(H1)之一側壁146。側壁146亦藉由一間隙(G)與第二晶粒120之堆疊122分隔開，使得凸肩144覆蓋周邊區域112之一顯著百分比(例如，覆蓋面積(C))。基座142可由一黏附 劑148附接至封裝支撐基板102，且凸肩144可由熱傳導黏附劑133附接至第一晶粒110之周邊區域112。黏附劑133及148可為相同黏附劑，或其等可彼此不同。黏附劑133例如可為一TIM。如圖2D中所示，第一部分131可為包圍第一晶粒110及第二晶粒120之一環。
圖2E係圖解說明在第二晶粒120之間及第一晶粒110與底部第二晶粒120之間沈積底部填充材料160之後製造總成100之方法之另一階段之一截面圖。底部填充材料160通常係可流動材料，其填充第二晶粒120、導電元件124及熱傳導元件128之間的填隙空間。TTS 130之第一部分131提供一屏障部件，其抑制填角料162覆蓋第一晶粒110之周邊區域112之程度。例如，填角料162沿側壁146之一部分向上延伸，而非如同在沈積底部填充材料160之後將熱傳導部件附接至周邊區域112之其他裝置中一樣，填角料162在周邊區域112上方橫向地展開。底部填充材料160可為一不導電環氧樹脂糊狀物(例如由日本新舄市Namics Corporation製造的XS8448-171)、一毛細管底部填充物、一不導電膜、一模製底部填充物及/或包含其他適當的電絕緣材料。底部填充材料160可替代地為一介電底部填充物，諸如由德國杜塞爾多夫Henkel製造的FP4585。在一些實施例中，底部填充材料160可基於其熱傳導率選擇以增強通過堆疊122之熱耗散。底部填充材料160的量經選擇以充分填充填隙空間使得底部填充材料160之一過量部分進入第一部分131之側壁146與第二晶粒120之堆疊122之間的間隙(G)中而形成填角料162。高度(H1)、間隙(G)及覆蓋面積(C)經選擇以提供周邊區域112之一大的覆蓋面積(C)，同時亦提供側壁146與第二晶粒120之堆疊122之間的足夠空間以容納底部填充材料160之填角料162。
圖2F係圖解說明TTS 130之第二部分132已附接至第一部分131以完成TTS 130之後圖1之總成100之一截面圖。第二部分132可具有由黏附劑133附接至最上面第二晶粒120之一頂部152、由黏附劑133附接至 第一部分131之一底部154，及自頂部152下垂之一側壁156。第一部分131及第二部分132一起界定包納第二晶粒120之堆疊122之腔138。圖2F中圖解說明之實施例之TTS 130因此係一熱傳導殼體，其提供增強的熱傳遞以移除由第一晶粒110及第二晶粒120產生之熱量。TTS 130之第一部分131及第二部分132之各者可由金屬(諸如銅或鋁)製成，使得TTS 130具有一金屬底座部分及一金屬罩。
圖3係根據本技術之總成100之另一實施例之一截面圖。在此實施例中，TTS 130之第一部分131具有具備延伸至至少與最上面第二晶粒120之頂部近似相同之高度之一高度(H2)之一側壁146，且TTS 130之第二部分132具有附接至側壁146之頂部之一底部154。第二部分132因此不具有自頂部152下垂之一單獨側壁。第二部分132可由黏附劑133附接至第一部分131。
圖4A係在根據本技術之一製造程序之一階段處之一半導體晶粒總成400之一側視截面圖，且圖4B係該半導體晶粒總成400之一俯視平面圖。總成400之若干特徵類似於上文關於總成100描述之特徵，且因此相似元件符號係指圖1至圖4B中之相似組件。圖4A展示一內部殼體430附接至第一晶粒110之後的總成400。內部殼體430可包含具有一第一內表面433之一第一支撐件431、具有一第二內表面434之一第二支撐件432，及在第一支撐件431與第二支撐件432之間延伸之一頂部435。內部殼體430具有一腔436，其用第一支撐件431及第二支撐件432封閉在側邊上，但是在另外兩側上敞開。第一支撐件431及第二支撐件432可用黏附劑133附接至第一晶粒110之周邊區域112。內部殼體430之頂部435亦可由黏附劑133附接至第二晶粒120之頂部。如圖4B中所示，內部殼體430可具有類似於第一晶粒110之佔據面積之一佔據面積。
圖4C係在底部填充材料160已沈積在第二晶粒120之間及第一晶 粒110與底部第二晶粒120之間之後的一後續製造階段處之總成400之一側視截面圖。返回參考圖4B，底部填充材料可藉由如箭頭F所示般將底部填充材料流過內部殼體430之敞開側而分佈在填隙空間內。為增強底部填充材料之流動，總成400可傾斜成某個角度使得重力將底部填充材料160拖曳通過腔436內之填隙空間。
圖4D係一後續製造階段處之總成400之一側視截面圖，且圖4E係該總成400之一俯視平面圖。參考圖4D，總成400進一步包含一外部殼體440，其具有具備一內表面444之一側壁442及與該側壁442一起界定一腔448之一頂部446。如圖4E中所示，側壁442之內表面444具有四側使得腔448圍封第一晶粒110、第二晶粒120之堆疊及內部殼體430。如圖4D中所示，外部殼體440可由黏附劑148附接至封裝支撐基板102且由黏附劑133附接至內部殼體430之頂部435。此實施例提供與如上文解釋之第一晶粒110之周邊區域112且與第二晶粒120之諸側之一良好的散熱介面，因為底部填充材料160可具有高於殼體內之一空隙之一熱傳導率。
圖5A係根據本技術之另一實施例之一半導體裝置總成500(「總成500」)之一截面圖，且圖5B係該半導體裝置總成500之一俯視平面圖。相似元件符號係指遍及圖1至圖5B之相似組件。總成500包含一TTS 530，其具有一頂部532、與頂部532一體式形成之一側壁534，及由頂部532及側壁534界定之一腔538。TTS 530係由具有高熱傳導率之一材料(諸如銅或鋁)形成之一單件式殼體。側壁534可具有一內表面535。在如圖5B中所示之一實施例中，內表面535可具有四側，其等經組態以與第二晶粒120之堆疊122分隔開使得第二晶粒120與側壁534之內表面535之間存在一小間隙。返回參考圖5A，側壁534可進一步包含由黏附劑148附接至封裝支撐基板102之一基座536及由黏附劑133附接至第一晶粒110之周邊區域112之一凸肩537。基座536可為具有自 第一晶粒110之周邊區域112向外橫向地分開之一內表面539之一基腳。TTS 530可進一步包含一入口540a及一出口540b。入口540a可為延伸穿過側壁534之一下部部分之一第一通道，且出口540b可為延伸穿過側壁534之一上部部分之一第二通道。參考圖5B，入口540a及出口540b可彼此橫向地偏移，或在其他實施例中其等可跨腔538彼此對準。在其他實施例中，入口540a及出口540b可以近似相同高度延伸穿過側壁。在又其他實施例中，入口540a可沿側壁534定位的高度相對大於出口540b可沿側壁534定位的高度。
底部填充材料160經由入口540a注入(I)至腔538中，使得底部填充材料160填充第二晶粒120之間及第一晶粒與底部第二晶粒120之間的填隙空間。在一實施例中，底部填充材料160可被注入至腔538中直至底部填充材料160流出出口540b(O)。入口540a及出口540b可藉由用底部填充材料160填充此等通道來密封，或在其他實施例中，入口540a及出口540b之外部開口可用另一材料加蓋以將腔538密封在TTS 530內。因此，TTS 530提供一屏障部件，其有效地含有底部填充材料160，同時亦由側壁534之凸肩537提供第一晶粒110之周邊區域112之一大的表面積的覆蓋。此外，底部填充材料160亦接觸第二晶粒120之諸側，以亦增強熱量傳遞橫向地遠離第二晶粒120。
圖6係根據本技術之另一實施例之一半導體晶粒總成600(「總成600」)之一截面圖。相似元件符號係指圖1至圖6中之相似組件。總成600可包含一TTS 630，其具有一頂部632及具有一內表面636之一側壁634。頂部632及側壁634界定經組態以容納第一晶粒110及第二晶粒120之堆疊122之一腔638。頂部632可由黏附劑133附接至上部第二晶粒120，且側壁634可由黏附劑148附接至封裝支撐基板102。圖6中所示之側壁634之實施例不接觸第一晶粒110之周邊區域112。在其他實施例中，側壁634可具有黏附至第一晶粒110之周邊區域112之一凸 肩，及黏附至封裝支撐基板102之一基座，如由圖5A中所示之側壁534之凸肩537及基座536所示。TTS 630可進一步包括一入口640a及一出口640b。在經圖解說明之實施例中，入口640a及出口640b係延伸穿過TTS 630之頂部632之通道。在其他實施例中，入口640a及/或出口640b可為穿過側壁634之通道。此外，圖6中圖解說明之TTS 630之實施例係其中頂部632與側壁634一體式形成之一單件式殼體。在其他實施例中，頂部632可為由黏附劑附接至側壁634之一單獨組件，諸如上文關於圖3展示並描述。
總成600進一步包含腔638中之一熱傳導介電液體670。介電液體670可經由入口640a注入至腔638中(I)。出口640b可因此提供通風孔，空氣或其他物質隨著注入介電液體670而可透過該通風孔自腔638逸出(O)。介電液體670可作為一液體注入且在腔638內保留為液體狀態，或其可作為一液體注入且部分固化為一凝膠狀物質或完全固化為一固體。適當的熱傳導介電液體670包含例如石蠟流體及由Dow Chemical Company製造之DowthermTM。適當的DowthermTM熱傳遞流體包含Dowtherm ATM、Dowtherm GTM、Dowtherm QTM及Dowtherm TTM，其等全部係由Dow Chemical Company製造。介電液體670應具有大於總成600之最大操作溫度之一沸點以避免在腔中產生一氣體。在一些實施例中，介電液體670可經選擇以在周圍溫度下固化為一固態或半固態材料，但是在最大操作溫度下或附近經歷到一液體狀態之一相變以潛在地增強熱傳遞並當達到最大操作溫度時提供一穩定狀態操作溫度。
介電液體670可填充第二晶粒120之間及第一晶粒110與底部第二晶粒120之間的填隙空間，使得不一定需要一單獨底部填充材料。在其他實施例中，在用介電液體670填充腔638之前，一底部填充材料可沈積在第二晶粒120之間及第一晶粒110與底部第二晶粒120之間。當 介電液體670保持為液體狀態時底部填充材料通常係需要的，以提供對晶粒110、120之結構支撐。然而，當介電液體670固化為一充分固態時，可移除底部填充材料。
在操作中，介電液體670不僅接觸第一晶粒110之周邊區域112，而且接觸第二晶粒120以有效地傳遞熱量至TTS 630。與使用一底部填充材料及/或在殼體與晶粒110及120之間具有空隙之裝置相比，此在具有高熱傳導率之一材料與晶粒110及120之間提供顯著更多表面接觸。在一些實施例中，腔638經完全填充以防止TTS 630出現空隙，且入口640a及出口640b經加蓋以密封腔638。總成600之實施例預期提供自第一晶粒110及第二晶粒120之高效率的熱量傳遞。
圖7係根據本技術之總成600之另一實施例之一截面圖。在此實施例中，入口640a係延伸穿過側壁634之一下部部分之一通道，且出口640b係延伸穿過頂部632之一通道。此實施例提供腔638之自下而上的填充，這預期可減少腔638內氣穴之可能形成。
圖8係根據本技術之總成600之另一實施例之一截面圖。在此實施例中，TTS 630係具有由黏附劑133彼此附接之一頂部組件632及一單獨側壁634之一多件式殼體。側壁634可由黏附劑148附接至封裝支撐基板102，且接著可用介電液體670填充側壁634之內表面636與晶粒110及120之間的空間。頂部632接著由黏附劑133附接至側壁634及上部第二晶粒120。在許多實施例中，腔638將具有由黏附劑133之厚度引起之一小的空隙。為避免腔638內具有一可膨脹氣體，TTS 630之頂部632可在一真空中附接至側壁634。
圖9係根據本技術之另一實施例之一半導體晶粒總成900(「總成900」)之一截面圖。圖9中圖解說明之實施例類似於圖2F中圖解說明之總成100之實施例，且因此相似元件符號係指圖1至圖9中之相似組件。在總成900中，TTS 130可進一步包含TTS 130之第二部分132中之 一入口910a及一出口910b。入口910a及出口910b係曝露於TTS 130內之腔138之通道。總成900進一步包含腔138中之底部填充材料160及介電液體670兩者。底部填充材料160可如上文參考圖2E描述般沈積。介電液體670可經由入口910a注入至腔中，且空氣或過量的介電液體670可經由出口910b自腔138中傳出。在腔138已用介電液體670填充之後，入口910a及出口910b可經加蓋或以其他方式密封以密封腔138使其與外部環境隔離。
上文參考圖1至圖9描述之堆疊式半導體晶粒總成之任一者可併入至大量較大系統及/或更複雜系統之任一者中，該等系統之一代表性實例係圖10中示意地展示之系統1000。系統1000可包含一半導體晶粒總成1010、一電源1020、一驅動器1030、一處理器1040及/或其他子系統或組件1050。半導體晶粒總成1010可包含通常類似於上文描述之堆疊式半導體晶粒總成之特徵之特徵，且可因此包含具有可良好覆蓋第一晶粒110之周邊區域112且增強熱耗散之多個散熱路徑。所得系統1000可執行多種功能之任一者，諸如記憶體儲存、資料處理及/或其他適當功能。因此，代表性系統1000可包含但不限於手持式裝置(例如，行動電話、桌上型電腦、數位閱讀機及數位音訊播放器)、電腦及家電。系統1000之組件可容置在一單個單元中或分佈在多個互連單元(例如，透過一通信網路)內。系統1000之組件亦可包含遠程裝置及多種電腦可讀媒體之任一者。
自前述將明白，本文中已針對圖解說明目的描述本技術之特定實施例，但是可在不脫離本發明的情況下作出各種修改。例如，雖然關於HMC描述半導體晶粒總成之許多實施例，但是在其他實施例中，半導體晶粒總成可被組態為其他記憶體裝置或其他類型的堆疊式晶粒總成。此外，圖1至圖9中圖解說明之半導體晶粒總成包含在第二半導體晶粒上配置成一堆疊之複數個第一半導體晶粒。然而，在其他 實施例中，半導體晶粒總成可包含堆疊在第二半導體晶粒之一或多者上之一第一半導體晶粒。特定實施例之背景中描述之新技術之某些態樣亦可在其他實施例中組合或消除。此外，雖然已在該等實施例之背景中描述與新技術之某些實施例相關聯之優點，但是其他實施例亦可展現出此等優點且並非所有實施例一定展現出此等優點以落在本技術之範疇內。因此，本發明及相關聯之技術可涵蓋本文中未明確展示或描述之其他實施例。
100‧‧‧半導體晶粒總成
102‧‧‧封裝支撐基板
110‧‧‧第一半導體晶粒
112‧‧‧周邊區域
120‧‧‧第二半導體晶粒
122‧‧‧堆疊
130‧‧‧熱傳遞結構(TTS)
131‧‧‧第一部分
132‧‧‧第二部分
133‧‧‧黏附劑
138‧‧‧腔
160‧‧‧底部填充材料
162‧‧‧填角料

Claims (25)

  1. 一種用於封裝具有一第一晶粒及配置成一堆疊且附接至該第一晶粒之複數個第二晶粒之一半導體晶粒總成之方法，其中該第一晶粒具有自該第二晶粒堆疊向外橫向地延伸之一周邊區域，該方法包括：將一熱傳遞結構之至少一部分定位在該第一晶粒之該周邊區域處，其中該熱傳遞結構包括一熱傳導材料及一第一部分，該第一部分具有(a)經組態以至少圍繞該第一晶粒之一部分延伸且附接至一封裝支撐基板之一基座，及(b)經組態以附接至該周邊區域之一上表面之一凸肩；其中將該熱傳遞結構之至少一部分定位在該第一晶粒之該周邊區域上包括將該基座附接至一封裝支撐基板且用該凸肩與該第一晶粒之該周邊區域之間之一散熱介面材料將該凸肩附接至該第一晶粒之該周邊區域；在將該熱傳遞結構定位在該第一晶粒之該周邊區域上之後，使一底部填充材料流入該等第二晶粒之間，其中該底部填充材料具有自該第二晶粒堆疊橫向地延伸之一填角料，且其中該底部填充材料之該橫向延伸受該熱傳遞結構限制；及在流入該底部填充材料之後將該熱傳遞結構之一第二部分附接至該熱傳遞結構之該第一部分，其中該熱傳遞結構之第一部分及第二部分形成具有一腔之一殼體，在該腔中定位有該第一晶粒及該第二晶粒堆疊。
  2. 如請求項1之方法，其中該熱傳遞結構之該第一部分包括一屏障部件，且該熱傳遞結構之該第二部分包括一罩。
  3. 如請求項2之方法，其中該罩具有一頂部及自該頂部下垂之一側 壁，且該側壁附接至該屏障部件。
  4. 如請求項2之方法，其中該屏障部件包括包圍該第一晶粒之一環。
  5. 如請求項1之方法，其中該熱傳遞結構之該第一部分包括延伸至一最上面第二晶粒之一高度之一側壁，且該熱傳遞結構之該第二部分包括一頂部。
  6. 如請求項1之方法，其中該熱傳遞結構包括一金屬殼體，其中該熱傳遞結構之第一部分包括該金屬殼體之一下部部分，且其中將該熱傳遞結構之至少一部分定位在該第一晶粒之該周邊區域處包括用一散熱介面材料將該金屬殼體之該下部部分附接至該第一晶粒之該周邊區域，使得該第二晶粒堆疊係在該熱傳遞結構之該腔中。
  7. 如請求項6之方法，其中：該金屬殼體之該下部部分包括一金屬環；該熱傳遞結構之第二部分包括一金屬罩；將該熱傳遞結構之至少一部分定位在該第一晶粒之該周邊區域處包括將該環附接至該周邊區域；及將該熱傳遞結構之該第二部分附接至該熱傳遞結構之該第一部分包括在使該底部填充材料流入之後將該金屬罩附接至該環，使得該第二晶粒堆疊被包納在該金屬環及該金屬罩內。
  8. 如請求項6之方法，其中：該金屬殼體包括一金屬側壁、與該金屬側壁一起形成該腔之一金屬頂部，及一入口；將該熱傳遞結構之至少一部分定位在該第一晶粒之該周邊區域處包括將該側壁附接至該周邊區域；及使該底部填充材料流入該等第二晶粒之間包括經由該入口將 該底部填充材料注入至該腔中。
  9. 如請求項1之方法，其進一步包括在流入該底部填充材料之後將一介電液體灌入在該殼體內，其中該介電液體是熱傳導的。
  10. 如請求項9之方法，其進一步包括至少部分固化該腔內之該介電液體。
  11. 一種用於封裝具有一第一晶粒及配置成一堆疊且附接至該第一晶粒之複數個第二晶粒之一半導體晶粒總成之方法，其中該第一晶粒具有自該第二晶粒堆疊向外橫向地延伸之一周邊區域，該方法包括：將一熱傳遞結構之至少一部分定位在該第一晶粒之該周邊區域處，其中該熱傳遞結構包括一熱傳導材料、一側壁、與該側壁一體式形成之一頂部、由該側壁及該頂部形成之一腔，及一入口，其中該側壁具有經組態以包圍該第一晶粒之至少一部分之一基座及經組態以定位在該第一晶粒之該周邊區域上方之一凸肩，且其中將該熱傳遞結構定位在該第一晶粒之該周邊區域上包括將該基座附接至一封裝支撐基板且將該凸肩附接至該晶粒之該周邊區域，其中該第二晶粒堆疊係在該腔中；及在將該熱傳遞結構定位在該第一晶粒之該周邊區域上之後，使一底部填充材料流入該等第二晶粒之間，其中該底部填充材料具有自該第二晶粒堆疊橫向地延伸之一填角料，且其中該底部填充材料之該橫向延伸受該熱傳遞結構限制，且其中使該底部填充材料流入該等第二晶粒之間包括經由該入口將該底部填充材料注入至該腔中。
  12. 如請求項11之方法，其中該入口係穿過該側壁之一下部區域之一第一通道，且出口係穿過該側壁之一上部區域之一第二通道。
  13. 如請求項11之方法，其中該入口係穿過該頂部之一第一通道，且 該出口係穿過該頂部之一第二通道。
  14. 一種用於封裝具有一第一晶粒及在該第一晶粒上方配置成一堆疊之複數個第二晶粒之一半導體晶粒總成之方法，其中該第一晶粒具有自該第二晶粒堆疊向外橫向地延伸之一周邊區域，該方法包括：將一熱傳遞結構耦合至該第一晶粒之該周邊區域，其中該熱傳遞結構包括具有一側壁及一頂部之一金屬殼體；且其中將該熱傳遞結構耦合至該第一晶粒之該周邊區域包括將該側壁之一下部部分附接至該第一晶粒之該周邊區域且將該頂部附接至該第二晶粒堆疊之一最上面第二晶粒；及在將該熱傳遞結構耦合至該第一晶粒之該周邊區域之後，使一底部填充材料流入該等第二晶粒之間，且其中該熱傳遞結構限制該底部填充材料之橫向流動，且其中流入該底部填充材料包括在該殼體之至少該側壁與該第二晶粒堆疊之間灌入該底部填充材料。
  15. 如請求項14之方法，其中：該熱傳遞結構之該金屬殼體進一步包括一入口；及流入該底部填充材料進一步包括將該底部填充材料透過該入口注入至該殼體中。
  16. 如請求項15之方法，其中該殼體進一步包括一出口，且該方法進一步包括經由排氣埠自該殼體排放物質且堵塞該出口。
  17. 如請求項14之方法，其中：該熱傳遞結構之該金屬殼體進一步包括一底座；及流入該底部填充材料進一步包括沈積該底部填充材料使得其流入該底座與該第二晶粒堆疊之間。
  18. 如請求項14之方法，其中該熱傳遞結構進一步包括一外部殼 體，且該方法進一步包括將該外部殼體附接至一封裝支撐基板及該內部殼體，其中該外部殼體具有一腔，在該腔中定位有該第二晶粒堆疊、該第一晶粒及該內部殼體。
  19. 如請求項14之方法，其中：將該熱傳遞結構耦合至該第一晶粒之該周邊區域進一步包括將一熱傳導殼體附接至一封裝支撐基板，且其中該殼體具有一腔，在該腔中定位有該第一晶粒及該第二晶粒堆疊；及該方法進一步包括在流入該底部填充材料之後將一介電液體注入至該殼體之該腔中，其中該介電液體具有熱傳導性。
  20. 如請求項19之方法，其進一步包括固化該腔內之該介電液體。
  21. 一種用於封裝具有一第一晶粒及在該第一晶粒上方配置成一堆疊之複數個第二晶粒之一半導體晶粒總成之方法，其中該第一晶粒具有自該第二晶粒堆疊向外橫向地延伸之一周邊區域，該方法包括：將一熱傳遞結構之至少一部分耦合至一封裝支撐基板使得該第一晶粒及該等第二晶粒係在該熱傳遞結構之一腔內；及將一介電液體灌入該熱傳遞結構之該腔中，且其中該介電液體具有一高的熱傳導性。
  22. 如請求項21之方法，其中：該熱傳遞結構具有一側壁、一頂部、由該側壁及該頂部界定之一腔，及一入口；將該熱傳遞結構之至少一部分耦合至該封裝支撐基板包括將該側壁安裝至該封裝支撐基板；及將該介電液體灌入該腔中包括將該介電液體注入至該入口中。
  23. 如請求項21之方法，其中該側壁及該頂部係一體式形成在一 起。
  24. 如請求項21之方法，其中該入口包括穿過該頂部之一通道。
  25. 如請求項21之方法，其中：該熱傳遞結構具有一側壁及一頂部，且該側壁及該頂部係分離組件；將該熱傳遞結構之至少一部分耦合至該封裝支撐基板包括將該側壁安裝至該封裝支撐基板；將該介電液體灌入該腔中包括在將該頂部附接至該側壁之前將該介電液體流至該腔中，及該方法進一步包括在灌入該介電液體之後將該頂部附接至該側壁。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9735082B2 (en) 2013-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packaging with hot spot thermal management features
US9691746B2 (en) 2014-07-14 2017-06-27 Micron Technology, Inc. Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US10068181B1 (en) 2015-04-27 2018-09-04 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafer and methods for making the same
US11329026B2 (en) * 2016-02-17 2022-05-10 Micron Technology, Inc. Apparatuses and methods for internal heat spreading for packaged semiconductor die
US10032695B2 (en) 2016-02-19 2018-07-24 Google Llc Powermap optimized thermally aware 3D chip package
US9865570B1 (en) * 2017-02-14 2018-01-09 Globalfoundries Inc. Integrated circuit package with thermally conductive pillar
US10199356B2 (en) 2017-02-24 2019-02-05 Micron Technology, Inc. Semiconductor device assembles with electrically functional heat transfer structures
US10096576B1 (en) 2017-06-13 2018-10-09 Micron Technology, Inc. Semiconductor device assemblies with annular interposers
US10090282B1 (en) 2017-06-13 2018-10-02 Micron Technology, Inc. Semiconductor device assemblies with lids including circuit elements
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
CN107256850B (zh) * 2017-07-25 2023-03-31 厦门大学 一种内嵌金属微通道的转接板及其制备方法
US10515867B2 (en) * 2017-11-14 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10453820B2 (en) 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
US10971439B2 (en) * 2018-02-22 2021-04-06 Hamilton Sundstrand Corporation Ball grid array underfilling systems
US11094608B2 (en) 2018-06-29 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation structure including stacked chips surrounded by thermal interface material rings
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems
US10529637B1 (en) 2018-10-31 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US11296051B2 (en) * 2019-08-22 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and forming method thereof
KR102562315B1 (ko) * 2019-10-14 2023-08-01 삼성전자주식회사 반도체 패키지
KR102643424B1 (ko) * 2019-12-13 2024-03-06 삼성전자주식회사 반도체 패키지
CN113035801A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 存储器装置及其制造方法
US11011449B1 (en) 2020-02-27 2021-05-18 Micron Technology, Inc. Apparatus and method for dissipating heat in multiple semiconductor device modules
US11410961B2 (en) * 2020-03-17 2022-08-09 Micron Technology, Inc. Methods and apparatus for temperature modification in bonding stacked microelectronic components and related substrates and assemblies
CN113645759B (zh) * 2021-08-09 2024-03-12 维沃移动通信有限公司 电路板组件、电子设备和电路板组件的加工方法
CN114551385B (zh) * 2022-04-28 2022-09-13 之江实验室 含有微流道散热结构的三维堆叠封装结构及其封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080237895A1 (en) * 2007-03-30 2008-10-02 Oki Electric Industry Co., Ltd. Semiconductor device
US20130119528A1 (en) * 2011-11-14 2013-05-16 Micron Technology, Inc. Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4323914A (en) 1979-02-01 1982-04-06 International Business Machines Corporation Heat transfer structure for integrated circuit package
US5001548A (en) 1989-03-13 1991-03-19 Coriolis Corporation Multi-chip module cooling
US5405808A (en) * 1993-08-16 1995-04-11 Lsi Logic Corporation Fluid-filled and gas-filled semiconductor packages
KR100236016B1 (ko) * 1996-12-16 1999-12-15 구자홍 적층형 반도체 패키지 및 그의 어셈블리 방법
US6153929A (en) 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
JP3459891B2 (ja) * 1999-11-26 2003-10-27 埼玉日本電気株式会社 Ｉｃパッケージの補強構造および方法
US6686654B2 (en) 2001-08-31 2004-02-03 Micron Technology, Inc. Multiple chip stack structure and cooling system
KR100446290B1 (ko) * 2001-11-03 2004-09-01 삼성전자주식회사 댐을 포함하는 반도체 패키지 및 그 제조방법
US20050224953A1 (en) 2004-03-19 2005-10-13 Lee Michael K L Heat spreader lid cavity filled with cured molding compound
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
JP4983049B2 (ja) * 2005-06-24 2012-07-25 セイコーエプソン株式会社 半導体装置および電子機器
WO2007053571A2 (en) * 2005-11-01 2007-05-10 Techfilm, Llc Thermal interface material with multiple size distribution thermally conductive fillers
US20070126103A1 (en) 2005-12-01 2007-06-07 Intel Corporation Microelectronic 3-D package defining thermal through vias and method of making same
US20100117209A1 (en) 2007-02-28 2010-05-13 Bezama Raschid J Multiple chips on a semiconductor chip with cooling means
US7592697B2 (en) 2007-08-27 2009-09-22 Intel Corporation Microelectronic package and method of cooling same
JP2009218432A (ja) * 2008-03-11 2009-09-24 Sharp Corp 高周波モジュールおよび高周波モジュールの製造方法
US9142480B2 (en) * 2008-08-15 2015-09-22 Intel Corporation Microelectronic package with high temperature thermal interface material
US8299633B2 (en) * 2009-12-21 2012-10-30 Advanced Micro Devices, Inc. Semiconductor chip device with solder diffusion protection
JP2011216818A (ja) * 2010-04-02 2011-10-27 Elpida Memory Inc 半導体装置の製造方法
US8492911B2 (en) * 2010-07-20 2013-07-23 Lsi Corporation Stacked interconnect heat sink
US9668811B2 (en) 2010-11-16 2017-06-06 Boston Scientific Scimed, Inc. Minimally invasive access for renal nerve ablation
JP5861260B2 (ja) * 2011-03-10 2016-02-16 日本電気株式会社 半導体装置の製造方法及び半導体装置
JP2012253104A (ja) 2011-05-31 2012-12-20 Zycube:Kk インターポーザを用いた積層モジュールの実装構造
US8526186B2 (en) 2011-07-11 2013-09-03 Texas Instruments Incorporated Electronic assembly including die on substrate with heat spreader having an open window on the die
JP2013069988A (ja) * 2011-09-26 2013-04-18 Toshiba Corp 半導体装置とその製造方法
JP2013138177A (ja) * 2011-11-28 2013-07-11 Elpida Memory Inc 半導体装置の製造方法
US20140291834A1 (en) * 2013-03-27 2014-10-02 Micron Technology, Inc. Semiconductor devices and packages including conductive underfill material and related methods
WO2014157455A1 (ja) 2013-03-28 2014-10-02 東芝ホクト電子株式会社 発光装置、その製造方法、および発光装置使用装置
US9287240B2 (en) * 2013-12-13 2016-03-15 Micron Technology, Inc. Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
US9691746B2 (en) 2014-07-14 2017-06-27 Micron Technology, Inc. Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US9337119B2 (en) * 2014-07-14 2016-05-10 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
US9443744B2 (en) * 2014-07-14 2016-09-13 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080237895A1 (en) * 2007-03-30 2008-10-02 Oki Electric Industry Co., Ltd. Semiconductor device
US20130119528A1 (en) * 2011-11-14 2013-05-16 Micron Technology, Inc. Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

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