CN106537588A - 制造具有高效率散热路径的堆叠式半导体裸片组合件的方法 - Google Patents
制造具有高效率散热路径的堆叠式半导体裸片组合件的方法 Download PDFInfo
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- CN106537588A CN106537588A CN201580037974.XA CN201580037974A CN106537588A CN 106537588 A CN106537588 A CN 106537588A CN 201580037974 A CN201580037974 A CN 201580037974A CN 106537588 A CN106537588 A CN 106537588A
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000000429 assembly Methods 0.000 title claims description 11
- 230000000712 assembly Effects 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title description 18
- 230000002093 peripheral effect Effects 0.000 claims abstract description 80
- 238000012546 transfer Methods 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 31
- 238000005538 encapsulation Methods 0.000 claims description 38
- 239000007788 liquid Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 6
- 239000003792 electrolyte Substances 0.000 claims description 3
- 238000007665 sagging Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 230000008878 coupling Effects 0.000 abstract description 3
- 238000010168 coupling process Methods 0.000 abstract description 3
- 238000005859 coupling reaction Methods 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 29
- 239000011230 binding agent Substances 0.000 description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- MHCVCKDNQYMGEX-UHFFFAOYSA-N 1,1'-biphenyl;phenoxybenzene Chemical compound C1=CC=CC=C1C1=CC=CC=C1.C=1C=CC=CC=1OC1=CC=CC=C1 MHCVCKDNQYMGEX-UHFFFAOYSA-N 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 239000002199 base oil Substances 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000013529 heat transfer fluid Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 235000014593 oils and fats Nutrition 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000012188 paraffin wax Substances 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000012056 semi-solid material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/44—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements the complete device being wholly immersed in a fluid other than air
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/13001—Core members of the bump connector
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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Abstract
本发明涉及用于封装半导体裸片组合件的方法。在一个实施例中,一种方法涉及封装具有第一裸片及在所述第一裸片上方布置成堆叠的多个第二裸片的半导体裸片组合件,其中所述第一裸片具有从所述第二裸片堆叠向外横向地延伸的外围区域。所述方法可包括将热传递结构耦合到所述第一裸片的所述外围区域且使底部填充材料流入所述第二裸片之间。所述底部填充材料是在将所述热传递结构耦合到所述第一裸片的所述外围区域之后流入,使得所述热传递结构限制所述底部填充材料的横向流动。
Description
技术领域
所揭示实施例涉及半导体裸片组合件。特定地说,本技术涉及具有高效率散热路径的堆叠式半导体裸片组合件及相关联的系统及方法。
背景技术
包含存储器芯片、微处理器芯片及成像器芯片的封装式半导体裸片通常包含安装在衬底上且被包纳在塑料保护罩中的半导体裸片。裸片包含功能特征,例如存储器单元、处理器电路及成像器装置,以及电连接到功能特征的结合衬垫。结合衬垫可电连接到保护罩外部的端子以允许裸片连接到较高层级电路。
市场压力不断驱使半导体制造商减小裸片封装的大小以装配在电子装置的空间约束内,同时还施压于其以增加每一封装的功能容量以满足操作参数。用于增加半导体封装的处理能力而不基本上增加由封装覆盖的表面积(即,封装的“占据面积”)的一种方法是在单个封装中将多个半导体裸片垂直堆叠在彼此的顶部上。此类垂直堆叠式封装中的裸片可通过使用穿硅通孔(TSV)电耦合个别裸片的结合衬垫与相邻裸片的结合衬垫而互连。
与垂直堆叠式裸片封装相关联的挑战在于来自个别裸片的热量是加成性的且难以耗散由堆叠式裸片产生的汇总热量。总之,此增加了个别裸片、裸片之间的结及封装的操作温度,这可造成堆叠式裸片达到高于其最大操作温度(Tmax)的温度。问题还由于封装中的裸片的密度增加而恶化。此外,当装置在裸片堆叠中具有不同类型的裸片时,装置的最大操作温度被限制于具有最低的最大操作温度的裸片。
附图说明
图1是说明根据本技术的实施例的半导体裸片组合件的横截面图。
图2A是说明制造根据本技术的实施例的半导体裸片组合件的方法的横截面图,且图2B是说明所述方法的俯视平面图。
图2C是说明制造根据本技术的实施例的半导体裸片组合件的方法的横截面图,且图2D是说明所述方法的俯视平面图。
图2E及2F是说明制造根据本技术的实施例的半导体裸片组合件的方法的横截面图。
图3是说明根据本技术的实施例的半导体裸片组合件的横截面图。
图4A是说明制造根据本技术的实施例的半导体裸片组合件的方法的横截面图,且图4B是说明所述方法的俯视平面图。
图4C是说明制造根据本技术的实施例的半导体裸片组合件的方法的横截面图。
图4D是说明制造根据本技术的实施例的半导体裸片组合件的方法的横截面图,且图4E是说明所述方法的俯视平面图。
图5A是根据本技术的实施例的半导体裸片组合件的横截面图且图5B是所述半导体裸片组合件的俯视平面图。
图6是根据本技术的实施例的半导体裸片组合件的横截面图。
图7是根据本技术的实施例的半导体裸片组合件的横截面图。
图8是根据本技术的实施例的半导体裸片组合件的横截面图。
图9是根据本技术的实施例的半导体裸片组合件的横截面图。
图10是包含根据本技术的实施例配置的半导体裸片组合件的系统的示意图。
具体实施方式
下文描述具有高效率散热路径的堆叠式半导体裸片组合件及相关联的系统及方法的若干实施例的具体细节。术语“半导体裸片”通常是指具有集成电路或组件、数据存储元件、处理组件及/或制造在半导体衬底上的其它特征的裸片。例如,半导体裸片可包含集成电路存储器及/或逻辑电路。半导体裸片及/或半导体裸片封装中的其它特征可被视为彼此“热接触”,前提是所述两种结构可经由例如传导、对流及/或辐射通过热量交换能量。所属领域技术人员还将了解,本技术可具有额外实施例,且本技术可在无下文参考图1到10描述的实施例的若干细节的情况下实践。
如本文中使用,鉴于图中所示的定向,术语“垂直”、“横向”、“上部”及“下部”可指代半导体裸片组合件中的特征的相对方向或位置。例如,“上部”或“最上面”可指代经定位成比另一特征更接近页面的顶部的特征。然而,这些术语应被广义地解释为包含具有其它定向(例如颠倒或倾斜定向,其中顶部/底部、上方/下方、以上/以下、上/下及左/右取决于定向可互换)的半导体装置。
图1是说明根据本技术的实施例的半导体裸片组合件100(“组合件100”)的横截面图。组合件100可包含封装支撑衬底102、安装到封装支撑衬底102的第一半导体裸片110,及在堆叠区域(例如第一裸片110的中心区域或偏心区域)处布置在堆叠122中的多个第二半导体裸片120。第一裸片110可进一步包含在第二裸片120的外侧横向的外围区域112及热传递结构(TTS)130,热传递结构130具有由粘合剂133附接到第一裸片110的外围区域112的第一部分131及覆盖、围封或以其它方式在第二裸片120的堆叠122上方的第二部分132。例如,粘合剂133可为散热接口材料(“TIM”)或另一适当粘合剂。例如,TIM及其它粘合剂可包含基于聚硅氧的油脂、凝胶或掺杂有导电材料(例如,碳纳米管、焊锡材料、类钻石碳(DLC)等等)的粘合剂,以及相变材料。在图1中说明的实施例中,第一部分131是至少从第一裸片110的外围区域112延伸到第二裸片120的堆叠122的中间高度处的高度的底座,例如屏障部件。第二部分132是由粘合剂133附接到第一部分131及最上面第二裸片120的罩。第一部分131及第二部分132可一起界定由金属(例如,铜或铝)或其它高热传导材料制成的壳体,且第一部分131及第二部分132可一起界定其中定位有第二裸片120的堆叠122的腔138。
组合件100进一步包含第二裸片120中的每一者之间及第一裸片110与底部第二裸片120之间的底部填充材料160。底部填充材料160可在靠近第一裸片110的区域中形成从第二裸片120的堆叠122向外延伸的填角料162。组合件100预期提供来自第一裸片110及第二裸片120的堆叠122的热量的增强热耗散。例如,TTS 130可由具有高热传导率的材料制成以沿直接从第一裸片110的外围区域112的大部分的第一路径且沿穿过第二裸片120的第二路径有效地传递热量。TTS 130的第一部分131附接到第一裸片110的外围区域112的可用区域的大的百分比,因为第一部分131提供屏障,所述屏障防止底部填充材料160的填角料162覆盖外围区域112的显著百分比。这增强第一热路径的效率,因为与其中在第一部分131附接到第一裸片110的外围区域112之前沉积底部填充材料的装置相比,TTS 130的第一部分131可覆盖外围区域112的更多表面区域。
图1中所示的组合件100的若干实施例可因此提供增强的散热性质,其降低组合件100中的个别裸片110、120的操作温度使得所述裸片保持在其指定最大温度(Tmax)以下。这在组合件100被布置为混合存储器立方体(HMC)时极为有用,因为第一裸片110通常是较大衬底逻辑裸片,且第二裸片120通常是存储器裸片,且逻辑裸片通常是以远高于存储器裸片的功率等级操作(例如,与0.628W相比的5.24W)。逻辑裸片HMC配置通常将大量热量集中在第一裸片110的外围区域112处。逻辑裸片还可在外围区域处具有较大功率密度,从而造成外围区域处进一步集中热量且温度较高。因而,通过将第一裸片110的外围区域112的大的百分比耦合到TTS 130的高度传导第一部分131,热量可有效地从第一裸片的外围区域112消除。
图2A到2F说明制造根据本技术的实施例的组合件100的方法的方面。图2A是制造组合件100的阶段的横截面图且图2B是所述阶段的俯视平面图。参考图2A,封装支撑衬底102经配置以将第一裸片110及第二裸片120连接到较高层级封装(未展示)的外部电组件。例如,封装支撑衬底102可为中介板或印刷电路板,其包含半导体组件(例如,经掺杂硅晶片或砷化镓晶片)、不导电组件(例如,各种陶瓷衬底,例如氧化铝(Al2O3)、氮化铝(AlN)等等),及/或导电部分(例如,互连电路、TSV等等)。在图2A中说明的实施例中,封装支撑衬底102在封装支撑衬底102的第一侧103a处经由第一多个电连接器104a电耦合到第一裸片110,且在封装支撑衬底102的第二侧103b处经由第二多个电连接器104b电耦合到外部电路(未展示)(电连接器104a及电连接器104b统称为“电连接器104”)。电连接器104可为焊球、导电凸块及支柱、导电环氧树脂,及/或其它适当的导电元件。在各个实施例中,封装支撑衬底102可由具有相对较高热传导率的材料制成以增强第一半导体裸片110的背侧处的热耗散。
如图2A及2B中所示,第一裸片110可具有大于堆叠式第二裸片120的占据面积。第一裸片110因此包含安装区域111(图2A)或堆叠区域,在堆叠区域中,第二裸片120附接到第一裸片110且外围区域112向外横向延伸超出安装区域111的至少一侧。外围区域112因此是在第二裸片120外侧(例如,超出第二裸片120的长度及/或宽度)。
第一裸片110及第二裸片120可包含各种类型的半导体组件及功能特征,例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器、其它形式的集成电路存储器、处理电路、成像组件,及/或其它半导体特征。在各个实施例中,例如,组合件100可被配置为HMC,其中堆叠式第二裸片120是DRAM裸片或提供数据存储的其它存储器裸片,且第一裸片110是提供HMC内的存储器控制(例如DRAM控制)的高速逻辑裸片。在其它实施例中,第一裸片110及第二裸片120可包含其它半导体组件,且/或堆叠122中的个别第二裸片120的半导体组件可不同。
第一裸片110及第二裸片120可为矩形、圆形及/或其它适当形状,且可具有各种不同尺寸。例如,个别第二裸片120可各自具有大约10mm到11mm(例如,10.7mm)的长度L1及大约8mm到9mm(例如,8.6mm、8.7mm)的宽度。第一裸片110可具有大约12mm到13mm(例如,12.67mm)的长度L2及大约8mm到9mm(例如,8.5mm、8.6mm等等)的宽度。在其它实施例中,第一裸片110及第二裸片120可具有其它适当尺寸,及/或个别第二裸片120可具有彼此不同的尺寸。
第一裸片110的外围区域112(被所属领域的技术人员称为“门廊”(porch)或“搁板”(shelf))可由第一裸片110及第二裸片120的相对尺寸及第一裸片110的前向表面114上的堆叠122的位置来界定。在图2A及2B中说明的实施例中,堆叠122相对于第一裸片110的长度L2居中,使得外围区域112横向地延伸超出堆叠122的两个相对侧。例如,如果第一裸片110的长度L2比第二裸片120的长度L1大大约1.0mm,那么外围区域112将延伸超出居中第二裸片120的任一侧大约0.5mm。堆叠122还可相对于第一裸片110的宽度居中,且在其中第一裸片110的宽度及长度两者均大于居中堆叠122的实施例中,外围区域112可围绕第二裸片120的整个周长延伸。在其它实施例中,堆叠122可相对于第一裸片110的前向表面114(图2A)偏移,及/或第一裸片110的外围区域112可围绕小于堆叠122的全周长延伸。在进一步实施例中,第一裸片110及第二裸片120可为圆形,且因此第一裸片110及第二裸片120的相对直径界定外围区域112。
如图2A中所示,第二裸片120可在堆叠122中彼此电耦合,且由定位在相邻裸片110、120之间的多个导电元件124电耦合到衬底第一裸片110。虽然图1中所示的堆叠122包含电耦合在一起的8个第二裸片120,但是在其它实施例中,堆叠122可包含多于或少于8个裸片(例如,2到4个裸片,或至少9个裸片等等)。导电元件124可具有各种适当结构,例如支柱、柱、支杆、凸块,且可由铜、镍、焊锡(例如,基于SnAg的焊锡)、填充导体的环氧树脂及/或其它导电材料制成。在选定实施例中,例如,导电元件124可为铜柱,而在其它实施例中,导电元件124可包含更复杂的结构,例如氮化物上凸块(bump-on-nitride)结构。
如图2A中进一步所示,个别第二裸片120可各自包含多个TSV 126,其在一或两侧上与对应导电元件124对准以在第二裸片120的相对侧处提供电连接。每一TSV 126可包含完全行进穿过个别第二裸片120的导电材料(例如,铜)及电绝缘材料,所述电绝缘材料包围导电材料以电隔离TSV 126与第二裸片120的剩余部分。虽然图1中未展示,但是第一裸片110还可包含将第一裸片110电耦合到较高层级电路的多个TSV 126。在电通信之外,TSV126及导电元件124提供散热导管,热量可通过散热导管被传递远离第一裸片110及第二裸片120(例如,通过第一散热路径)。在一些实施例中,导电元件124及/或TSV 126的尺寸可增加以增强垂直通过堆叠122的热传递。例如,个别导电元件124可各自具有大约15μm到30μm的直径或其它适当尺寸以增强穿过裸片110、120的散热通路。在其它实施例中,第二裸片120可彼此电耦合且使用还可提供穿过堆叠122的散热通路的其它类型的电连接器(例如导线结合)电耦合到第一裸片110。
在各个实施例中,组合件100还可包含填隙地定位在导电元件124之间的多个热传导元件128(以虚线展示)。个别热传导元件128在结构及组成方面可至少通常类似于导电元件124(例如铜柱)。然而,热传导元件128并未电耦合到TSV 126或裸片110及120的其它电活性组件,且因此不提供第二裸片120之间的电连接。相反地,热传导元件128是电隔离“哑元件”,其增加通过堆叠122的整体热传导率以增强沿第一散热路径的热传递。例如,在其中组合件100被布置为HMC的实施例中,导电元件124之间添加热传导元件128已被示为将HMC的操作温度降低若干度(例如大约6℃到7℃)。
图2C是说明用于在TTS 130(图1)的第一部分131附接到第一裸片110及封装支撑衬底102之后制造组合件100的方法的后续阶段的横截面图,且图2D是说明所述后续阶段的俯视平面图。参考图2C,第一部分131的此实施例具有经配置以围绕第一裸片110的至少一部分延伸的基座142(例如,基脚)及经配置以定位在第一裸片110的外围区域112上方的凸肩144。第一部分131可进一步包含延伸到相对于第二裸片120的堆叠122的高度(H1)的侧壁146。侧壁146还通过间隙(G)与第二裸片120的堆叠122分隔开,使得凸肩144覆盖外围区域112的显著百分比(例如,覆盖面积(C))。基座142可由粘合剂148附接到封装支撑衬底102,且凸肩144可由热传导粘合剂133附接到第一裸片110的外围区域112。粘合剂133及148可为相同粘合剂,或其可彼此不同。粘合剂133例如可为TIM。如图2D中所示,第一部分131可为包围第一裸片110及第二裸片120的环。
图2E是说明在第二裸片120之间及第一裸片110与底部第二裸片120之间沉积底部填充材料160之后制造组合件100的方法的另一阶段的截面图。底部填充材料160通常是可流动材料,其填充第二裸片120、导电元件124及热传导元件128之间的填隙空间。TTS 130的第一部分131提供屏障部件,其抑制填角料162覆盖第一裸片110的外围区域112的程度。例如,填角料162沿侧壁146的部分向上延伸,而非如同在沉积底部填充材料160之后将热传导部件附接到外围区域112的其它装置中一样,填角料162在外围区域112上方横向地展开。底部填充材料160可为不导电环氧树脂糊状物(例如由日本新泻市的纳美仕公司(NamicsCorporation)制造的XS8448-171)、毛细管底部填充物、不导电膜、模制底部填充物及/或包含其它适当的电绝缘材料。底部填充材料160可替代地为介电底部填充物,例如由德国杜塞尔多夫的汉高公司(Henkel)制造的FP4585。在一些实施例中,底部填充材料160可基于其热传导率选择以增强通过堆叠122的热耗散。底部填充材料160的量经选择以充分填充填隙空间使得底部填充材料160的过量部分进入第一部分131的侧壁146与第二裸片120的堆叠122之间之间隙(G)中而形成填角料162。高度(H1)、间隙(G)及覆盖面积(C)经选择以提供外围区域112的大的覆盖面积(C),同时还提供侧壁146与第二裸片120的堆叠122之间的足够空间以容纳底部填充材料160的填角料162。
图2F是说明TTS 130的第二部分132已附接到第一部分131以完成TTS 130之后图1的组合件100的横截面图。第二部分132可具有由粘合剂133附接到最上面第二裸片120的顶部152、由粘合剂133附接到第一部分131的底部154,及从顶部152下垂的侧壁156。第一部分131及第二部分132一起界定包纳第二裸片120的堆叠122的腔138。图2F中说明的实施例的TTS 130因此是热传导壳体,其提供增强的热传递以消除由第一裸片110及第二裸片120产生的热量。TTS 130的第一部分131及第二部分132中的每一者可由金属(例如铜或铝)制成,使得TTS 130具有金属底座部分及金属罩。
图3是根据本技术的组合件100的另一实施例的横截面图。在此实施例中,TTS 130的第一部分131具有具备延伸到至少与最上面第二裸片120的顶部近似相同的高度的高度(H2)的侧壁146,且TTS 130的第二部分132具有附接到侧壁146的顶部的底部154。第二部分132因此不具有从顶部152下垂的单独侧壁。第二部分132可由粘合剂133附接到第一部分131。
图4A是在根据本技术的制造过程的一个阶段处的半导体裸片组合件400的侧视横截面图,且图4B是所述半导体裸片组合件400的俯视平面图。组合件400的若干特征类似于上文关于组合件100描述的特征,且因此相似参考数字是指图1到4B中的相似组件。图4A展示内部壳体430附接到第一裸片110之后的组合件400。内部壳体430可包含具有第一内表面433的第一支撑件431、具有第二内表面434的第二支撑件432,及在第一支撑件431与第二支撑件432之间延伸的顶部435。内部壳体430具有腔436,其用第一支撑件431及第二支撑件432封闭在侧边上,但是在另外两侧上敞开。第一支撑件431及第二支撑件432可用粘合剂133附接到第一裸片110的外围区域112。内部壳体430的顶部435还可由粘合剂133附接到第二裸片120的顶部。如图4B中所示,内部壳体430可具有类似于第一裸片110的占据面积的占据面积。
图4C是在底部填充材料160已沉积在第二裸片120之间及第一裸片110与底部第二裸片120之间之后的后续制造阶段处的组合件400的侧视横截面图。返回参考图4B,底部填充材料可通过如箭头F所示那样将底部填充材料流过内部壳体430的敞开侧而分布在填隙空间内。为增强底部填充材料的流动,组合件400可倾斜成某个角度使得重力将底部填充材料160拖曳通过腔436内的填隙空间。
图4D是后续制造阶段处的组合件400的侧视横截面图,且图4E是所述组合件400的俯视平面图。参考图4D,组合件400进一步包含外部壳体440,其具有具备内表面444的侧壁442及与侧壁442一起界定腔448的顶部446。如图4E中所示,侧壁442的内表面444具有四侧使得腔448围封第一裸片110、第二裸片120的堆叠及内部壳体430。如图4D中所示,外部壳体440可由粘合剂148附接到封装支撑衬底102且由粘合剂133附接到内部壳体430的顶部435。此实施例提供与如上文解释的第一裸片110的外围区域112且与第二裸片120的侧的良好的散热接口,因为底部填充材料160可具有高于壳体内的空隙的热传导率。
图5A是根据本技术的另一实施例的半导体装置组合件500(“组合件500”)的横截面图,且图5B是所述半导体装置组合件500的俯视平面图。相似参考数字遍及图1到5B指代相似组件。组合件500包含TTS 530,其具有顶部532、与顶部532一体式形成的侧壁534,及由顶部532及侧壁534界定的腔538。TTS 530是由具有高热传导率的材料(例如铜或铝)形成的单件式壳体。侧壁534可具有内表面535。在如图5B中所示的一个实施例中,内表面535可具有四侧,其经配置以与第二裸片120的堆叠122分隔开使得第二裸片120与侧壁534的内表面535之间存在小间隙。返回参考图5A,侧壁534可进一步包含由粘合剂148附接到封装支撑衬底102的基座536及由粘合剂133附接到第一裸片110的外围区域112的凸肩537。基座536可为具有从第一裸片110的外围区域112向外横向地分开的内表面539的基脚。TTS 530可进一步包含入口540a及出口540b。入口540a可为延伸穿过侧壁534的下部部分的第一通道,且出口540b可为延伸穿过侧壁534的上部部分的第二通道。参考图5B,入口540a及出口540b可彼此横向地偏移,或在其它实施例中其可跨腔538彼此对准。在其它实施例中,入口540a及出口540b可以近似相同高度延伸穿过侧壁。在又其它实施例中,入口540a可沿侧壁534定位的高度相对大于出口540b可沿侧壁534定位的高度。
底部填充材料160经由入口540a注入(I)到腔538中,使得底部填充材料160填充第二裸片120之间及第一裸片与底部第二裸片120之间的填隙空间。在一个实施例中,底部填充材料160可被注入到腔538中直到底部填充材料160流出出口540b为止(O)。入口540a及出口540b可通过用底部填充材料160填充这些通道来密封,或在其它实施例中,入口540a及出口540b的外部开口可用另一材料加盖以将腔538密封在TTS 530内。因此,TTS 530提供屏障部件,其有效地含有底部填充材料160,同时还由侧壁534的凸肩537提供第一裸片110的外围区域112的大的表面积覆盖。此外,底部填充材料160还接触第二裸片120的侧,以还增强横向地远离第二裸片120的热传递。
图6是根据本技术的另一实施例的半导体裸片组合件600(“组合件600”)的横截面图。相似参考数字指代图1到6中的相似组件。组合件600可包含TTS 630,其具有顶部632及具有内表面636的侧壁634。顶部632及侧壁634界定经配置以容纳第一裸片110及第二裸片120的堆叠122的腔638。顶部632可由粘合剂133附接到上部第二裸片120,且侧壁634可由粘合剂148附接到封装支撑衬底102。图6中所示的侧壁634的实施例不接触第一裸片110的外围区域112。在其它实施例中,侧壁634可具有粘附到第一裸片110的外围区域112的凸肩,及粘附到封装支撑衬底102的基座,如由图5A中所示的侧壁534的凸肩537及基座536所示。TTS630可进一步包括入口640a及出口640b。在经说明的实施例中,入口640a及出口640b是延伸穿过TTS 630的顶部632的通道。在其它实施例中,入口640a及/或出口640b可为穿过侧壁634的通道。此外,图6中说明的TTS 630的实施例是其中顶部632与侧壁634一体式形成的单件式壳体。在其它实施例中,顶部632可为由粘合剂附接到侧壁634的单独组件,例如上文关于图3展示并描述。
组合件600进一步包含腔638中的热传导电介质液体670。电介质液体670可经由入口640a注入到腔638中(I)。出口640b可因此提供通风孔,空气或其它物质随着注入电介质液体670而可通过所述通风孔从腔638逸出(O)。电介质液体670可作为液体注入且在腔638内保留为液体状态,或其可作为液体注入且部分固化为凝胶状物质或完全固化为固体。适当的热传导电介质液体670包含例如石蜡流体及由陶氏化学公司(Dow Chemical Company)制造的DowthermTM。适当的DowthermTM热传递流体包含Dowtherm ATM、Dowtherm GTM、Dowtherm QTM及Dowtherm TTM,其全部是由陶氏化学公司制造。电介质液体670应具有大于组合件600的最大操作温度的沸点以避免在腔中产生气体。在一些实施例中,电介质液体670可经选择以在周围温度下固化为固态或半固态材料,但是在最大操作温度下或附近经历到液体状态的相变以潜在地增强热传递并当达到最大操作温度时提供稳定状态操作温度。
电介质液体670可填充第二裸片120之间及第一裸片110与底部第二裸片120之间的填隙空间,使得不一定需要单独底部填充材料。在其它实施例中,在用电介质液体670填充腔638之前,底部填充材料可沉积在第二裸片120之间及第一裸片110与底部第二裸片120之间。当电介质液体670保持为液体状态时底部填充材料通常是需要的,以提供对裸片110、120的结构支撑。然而,当电介质液体670固化为充分固态时,可移除底部填充材料。
在操作中,电介质液体670不仅接触第一裸片110的外围区域112,而且接触第二裸片120以有效地传递热量到TTS 630。与使用底部填充材料及/或在壳体与裸片110及120之间具有空隙的装置相比,这在具有高热传导率的材料与裸片110及120之间提供显著更多表面接触。在一些实施例中,腔638经完全填充以防止TTS 630出现空隙,且入口640a及出口640b经加盖以密封腔638。组合件600的实施例预期提供从第一裸片110及第二裸片120的高效率的热量传递。
图7是根据本技术的组合件600的另一实施例的横截面图。在此实施例中,入口640a是延伸穿过侧壁634的下部部分的通道,且出口640b是延伸穿过顶部632的通道。此实施例提供腔638的从下而上的填充,这预期可减少腔638内气穴的可能形成。
图8是根据本技术的组合件600的另一实施例的横截面图。在此实施例中,TTS 630是具有由粘合剂133彼此附接的顶部组件632及单独侧壁634的多件式壳体。侧壁634可由粘合剂148附接到封装支撑衬底102,且接着可用电介质液体670填充侧壁634的内表面636与裸片110及120之间的空间。顶部632接着由粘合剂133附接到侧壁634及上部第二裸片120。在许多实施例中,腔638将具有由粘合剂133的厚度引起的小的空隙。为避免腔638内具有可膨胀气体,TTS 630的顶部632可在真空中附接到侧壁634。
图9是根据本技术的另一实施例的半导体裸片组合件900(“组合件900”)的横截面图。图9中说明的实施例类似于图2F中说明的组合件100的实施例,且因此相似参考数字指代图1到9中的相似组件。在组合件900中,TTS 130可进一步包含TTS 130的第二部分132中的入口910a及出口910b。入口910a及出口910b是暴露于TTS 130内的腔138的通道。组合件900进一步包含腔138中的底部填充材料160及电介质液体670两者。底部填充材料160可如上文参考图2E描述那样沉积。电介质液体670可经由入口910a注入到腔中,且空气或过量的电介质液体670可经由出口910b从腔138中传出。在腔138已用电介质液体670填充之后,入口910a及出口910b可经加盖或以其它方式密封以密封腔138使其与外部环境隔离。
上文参考图1到9描述的堆叠式半导体裸片组合件中的任一者可并入到大量较大系统及/或更复杂系统中的任一者中,所述系统的代表性实例是图10中示意地展示的系统1000。系统1000可包含半导体裸片组合件1010、电源1020、驱动器1030、处理器1040及/或其它子系统或组件1050。半导体裸片组合件1010可包含通常类似于上文描述的堆叠式半导体裸片组合件的特征的特征,且可因此包含具有可良好覆盖第一裸片110的外围区域112且增强热耗散的多个散热路径。所得系统1000可执行多种功能中的任一者,例如存储器存储、数据处理及/或其它适当功能。因此,代表性系统1000可包含但不限于手持式装置(例如,移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机及电器。系统1000的组件可容置在单个单元中或分布在多个互连单元(例如,通过通信网络)中。系统1000的组件还可包含远程装置及多种计算机可读媒体中的任一者。
从前述将明白,本文中已针对说明目的描述本技术的特定实施例,但是可在不脱离本发明的情况下作出各种修改。例如,虽然关于HMC描述半导体裸片组合件的许多实施例,但是在其它实施例中,半导体裸片组合件可被配置为其它存储器装置或其它类型的堆叠式裸片组合件。此外,图1到9中说明的半导体裸片组合件包含在第二半导体裸片上布置成堆叠的多个第一半导体裸片。然而,在其它实施例中,半导体裸片组合件可包含堆叠在第二半导体裸片中的一或多者上的一个第一半导体裸片。特定实施例的背景中描述的新技术的某些方面还可在其它实施例中组合或消除。此外,虽然已在所述实施例的背景中描述与新技术的某些实施例相关联的优点,但是其它实施例还可展现出此类优点且并非所有实施例一定展现出此类优点以落在本技术的范围内。因此,本发明及相关联的技术可涵盖本文中未明确展示或描述的其它实施例。
Claims (35)
1.一种用于封装具有第一裸片及布置成堆叠且附接到所述第一裸片的多个第二裸片的半导体裸片组合件的方法,其中所述第一裸片具有从所述第二裸片堆叠向外横向地延伸的外围区域,所述方法包括:
将热传递结构的至少一部分定位在所述第一裸片的所述外围区域处,其中所述热传递结构包括热传导材料;及
在将所述热传递结构定位在所述第一裸片的所述外围区域上之后,使底部填充材料流入所述第二裸片之间,其中所述底部填充材料具有从所述第二裸片堆叠横向地延伸的填角料,且其中所述底部填充材料的所述横向延伸受所述热传递结构限制。
2.根据权利要求1所述的方法,其中:
所述热传递结构包括第一部分,所述第一部分具有经配置以至少围绕所述第一裸片的部分延伸的基座及经配置定位在所述第一裸片的所述外围区域上方的凸肩;及
将所述热传递结构的至少一部分定位在所述第一裸片的所述外围区域上包括将所述基座附接到封装支撑衬底且用所述凸肩与所述第一裸片的所述外围区域之间的散热接口材料将所述凸肩附接到所述第一裸片的所述外围区域。
3.根据权利要求1所述的方法,其中:
所述热传递结构包括第一部分,所述第一部分具有(a)经配置以至少围绕所述第一裸片的部分延伸且附接到封装支撑衬底的基座,及(b)经配置以附接到所述外围区域的上表面的凸肩;
将所述热传递结构的至少一部分定位在所述第一裸片的所述外围区域上包括将所述基座附接到封装支撑衬底且用所述凸肩与所述第一裸片的所述外围区域之间的散热接口材料将所述凸肩附接到所述第一裸片的所述外围区域;及
所述方法进一步包括在流入所述底部填充材料之后将所述热传递结构的第二部分附接到所述热传递结构的所述第一部分,其中所述热传递结构的第一部分及第二部分形成具有腔的壳体,在所述腔中定位有所述第一裸片及所述第二裸片堆叠。
4.根据权利要求3所述的方法,其中所述热传递结构的所述第一部分包括屏障部件,且所述热传递部件的所述第二部分包括罩。
5.根据权利要求4所述的方法,其中所述罩具有顶部及从所述顶部下垂的侧壁,且所述侧壁附接到所述屏障部件。
6.根据权利要求4的方法,其中所述屏障部件包括包围所述第一裸片的环。
7.根据权利要求3所述的方法,其中所述热传递结构的所述第一部分包括延伸到最上面第二裸片的高度的侧壁,且所述热传递部件的所述第二部分包括顶部。
8.根据权利要求1所述的方法,其中:
所述热传递结构包括侧壁、与所述侧壁一体式形成的顶部、由所述侧壁及所述顶部形成的腔,及入口;
所述侧壁具有经配置以包围所述第一裸片的至少一部分的基座及经配置以定位在所述第一裸片的所述外围区域上方的凸肩;
将所述热传递结构定位在所述第一裸片的所述外围区域上包括将所述基座附接到封装支撑衬底且将所述凸肩附接到所述裸片的所述外围区域,其中所述第二裸片堆叠是在所述腔中;及
使所述底部填充材料流入所述第二裸片之间包括经由所述入口将所述底部填充材料注入到所述腔中。
9.根据权利要求8所述的方法,其中所述入口是穿过所述侧壁的下部区域的第一通道,且出口是穿过所述侧壁的上部区域的第二通道。
10.根据权利要求8所述的方法,其中所述入口是穿过所述顶部的第一通道,且所述出口是穿过所述顶部的第二通道。
11.根据权利要求1所述的方法,其中:
所述热传递结构包括内部壳体,所述内部壳体具有第一支撑件及从所述第一支撑件延伸的顶部;
将所述热传递结构的至少一部分定位在所述第一裸片的所述外围区域上包括将所述第一支撑件附接到所述裸片的所述外围区域,其中所述第二裸片堆叠是在所述壳体的所述顶部下方;及
使所述底部填充材料流入所述第二裸片之间包括使所述底部填充材料流入所述第二裸片堆叠与所述内部壳体之间。
12.根据权利要求11所述的方法,其中所述内部壳体进一步包括第二支撑件,且所述顶部具有附接到所述第一支撑件的一端及附接到所述第二支撑件的另一端,且其中将所述热传递结构定位在所述第一裸片的所述外围区域上包括将所述第一支撑件及所述第二支撑件附接到所述第一裸片的所述外围区域。
13.根据权利要求11所述的方法,其中所述热传递结构进一步包括具有腔的外部壳体,且所述方法进一步包含将所述外部壳体附接到封装支撑衬底及所述内部壳体,使得所述内部壳体是容纳在所述外部壳体的所述腔内。
14.根据权利要求1所述的方法,其中所述热传递结构包括具有腔的金属壳体,且其中将所述热传递结构的至少一部分定位在所述第一裸片的所述外围区域处包括用散热接口材料将所述金属壳体的下部部分附接到所述第一裸片的所述外围区域,使得所述第二裸片堆叠是在所述金属壳体的所述腔中。
15.根据权利要求14所述的方法,其中:
所述金属壳体包括金属环及金属罩;
将所述热传递结构的至少一部分定位在所述第一裸片的所述外围区域处包括将所述环附接到所述外围区域;及
所述方法进一步包括在使所述底部填充材料流入之后将所述金属罩附接到所述环,使得所述第二裸片堆叠被包纳在所述金属环及所述金属罩内。
16.根据权利要求14所述的方法,其中:
所述金属壳体包括金属侧壁、与所述金属侧壁一起形成所述腔的金属顶部,及入口;
将所述热传递结构的至少一部分定位在所述第一裸片的所述外围区域处包括将所述侧壁附接到所述外围区域;及
使底部填充材料流入所述第二裸片之间包括经由所述入口将所述底部填充材料注入到所述腔中。
17.根据权利要求1所述的方法,其进一步包括在流入所述底部填充材料之后将电介质液体灌入在所述壳体内,其中所述电介质液体是热传导的。
18.根据权利要求17所述的方法,其进一步包括至少部分固化所述腔内的所述电介质液体。
19.一种用于封装具有第一裸片及在所述第一裸片上方布置成堆叠的多个第二裸片的半导体裸片组合件的方法,其中所述第一裸片具有从所述第二裸片堆叠向外横向地延伸的外围区域,所述方法包括:
将热传递结构耦合到所述第一裸片的所述外围区域;及
在将所述热传递结构耦合到所述第一裸片的所述外围区域之后,使底部填充材料流入所述第二裸片之间,且其中所述热传递结构限制所述底部填充材料的横向流动。
20.根据权利要求19所述的方法,其中:
所述热传递结构包括具有侧壁及顶部的金属壳体;
将所述热传递结构耦合到所述第一裸片的所述外围区域包括将所述侧壁的下部部分附接到所述第一裸片的所述外围区域且将所述顶部附接到所述第二裸片堆叠的最上面第二裸片;及
流入所述底部填充材料包括在所述壳体的至少所述侧壁与所述第二裸片堆叠之间灌入所述底部填充材料。
21.根据权利要求19所述的方法,其中:
所述热传递结构包括金属壳体,所述金属壳体具有侧壁、与所述侧壁一体式形成的顶部及入口,且所述侧壁进一步包括经配置以至少围绕所述第一裸片的部分延伸的基座及经配置以定位在所述第一裸片的所述外围区域上方的凸肩;
将所述热传递结构耦合到所述第一裸片的所述外围区域包括将所述基座附接到封装支撑衬底且将所述凸肩附接到所述第一裸片的所述外围区域,其中散热接口材料是在所述凸肩与所述第一裸片的所述外围区域之间;及
流入所述底部填充材料包括将所述底部填充材料通过所述入口注入到所述壳体中。
22.根据权利要求21所述的方法,其中所述壳体进一步包括出口,且所述方法进一步包括经由排气孔从所述壳体排放物质且堵塞所述出口。
23.根据权利要求19所述的方法,其中:
所述热传递结构包括具有底座及单独罩的金属壳体,且其中所述底座进一步包括经配置以至少围绕所述第一裸片的部分延伸的基座及经配置以定位在所述第一裸片的所述外围区域上方的凸肩;
将所述热传递结构耦合到所述第一裸片的所述外围区域包括将所述底座的所述基座附接到封装支撑衬底且将所述底座的所述凸肩附接到所述第一裸片的所述外围区域,其中散热接口材料是在所述底座的所述凸肩与所述第一裸片的所述外围区域之间;及
流入所述底部填充材料包括沉积所述底部填充材料使得其流入所述底座与所述第二裸片堆叠之间。
24.根据权利要求23所述的方法,其进一步包括在流入所述底部填充材料之后将所述罩附接到所述底座。
25.根据权利要求19所述的方法,其中:
所述热传递结构包括内部壳体,所述内部壳体具有第一支撑件、第二支撑件及在所述第一支撑件与所述第二支撑件之间延伸的顶部,使得所述内部壳体具有腔;
将所述热传递结构耦合到所述第一裸片的所述外围区域包括用散热接口材料将所述第一支撑件及所述第二支撑件附接到所述第一裸片的所述外围区域使得所述第二裸片堆叠是在所述腔中;及
流入所述底部填充材料包括将所述底部填充材料沉积在至少所述第二裸片堆叠与所述第一支撑件及所述第二支撑件之间。
26.根据权利要求25所述的方法,其中所述热传递结构进一步包括外部壳体,且所述方法进一步包括将所述外部壳体附接到封装支撑衬底及所述内部壳体,其中所述外部壳体具有腔,在所述腔中定位有所述第二裸片堆叠、所述第一裸片及所述内部壳体。
27.根据权利要求19所述的方法,其中:
将所述热传递结构耦合到所述第一裸片的所述外围区域进一步包括将热传导壳体附接到封装支撑衬底,且其中所述壳体具有腔,在所述腔中定位有所述第一裸片及所述第二裸片堆叠;及
所述方法进一步包括在流入所述底部填充材料之后将电介质液体注入到所述壳体的所述腔中,其中所述电介质液体是热传导的。
28.根据权利要求27所述的方法,其进一步包括固化所述腔内的所述电介质液体。
29.一种用于封装具有第一裸片及布置成堆叠且附接到所述第一裸片的多个第二裸片的半导体裸片组合件的方法,其中所述第一裸片具有从所述第二裸片堆叠向外横向地延伸的外围区域,所述方法包括:
将屏障部件定位在所述第一裸片的所述外围区域上,其中所述屏障部件包括热传导材料;及
在将所述屏障部件定位在所述第一裸片的所述外围区域上之后,使底部填充材料流入所述第二裸片之间,其中所述屏障部件具有含有所述底部填充材料的填角料部分的高度。
30.一种用于封装具有第一裸片及布置成堆叠且附接到所述第一裸片的多个第二裸片的半导体裸片组合件的方法,其中所述第一裸片具有从所述第二裸片堆叠向外横向地延伸的外围区域,所述方法包括:
将壳体的部分定位在所述第一裸片的所述外围区域上,其中所述壳体部件包括热传导材料且至少部分围封所述第二裸片堆叠;及
在将所述壳体定位在所述第一裸片的所述外围区域上之后,使底部填充材料流入所述第二裸片之间。
31.一种用于封装具有第一裸片及在所述第一裸片上方布置成堆叠的多个第二裸片的半导体裸片组合件的方法,其中所述第一裸片具有从所述第二裸片堆叠向外横向地延伸的外围区域,所述方法包括:
将热传递结构的至少一部分耦合到封装支撑衬底使得所述第一裸片及所述第二裸片是在所述热传递结构的腔内;及
将电介质液体灌入所述热传递结构的所述腔中,且其中所述电介质液体具有高的热传导性。
32.根据权利要求31所述的方法,其中:
所述热传递结构具有侧壁、顶部、由所述侧壁及所述顶部界定的腔,及入口;
将所述热传递结构的至少一部分耦合到所述封装支撑衬底包括将所述侧壁安装到所述封装支撑衬底;及
将所述电介质液体灌入所述腔中包括将所述电介质液体注入到所述入口中。
33.根据权利要求31所述的方法,其中所述侧壁及所述顶部一体式形成在一起。
34.根据权利要求31所述的方法,其中所述入口包括穿过所述顶部的通道。
35.根据权利要求31所述的方法,其中:
所述热传递结构具有侧壁及顶部,且所述侧壁及所述顶部是分离组件;
将所述热传递结构的至少一部分耦合到所述封装支撑衬底包括将所述侧壁安装到所述封装支撑衬底;
将所述电介质液体灌入所述腔中包括在将所述顶部附接到所述侧壁之前将所述电介质液体流入到所述腔中,及
所述方法进一步包括在灌入所述电介质液体之后将所述顶部附接到所述侧壁。
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Also Published As
Publication number | Publication date |
---|---|
KR101996153B1 (ko) | 2019-07-03 |
EP3170200B1 (en) | 2020-01-15 |
US20230395463A1 (en) | 2023-12-07 |
US20170229439A1 (en) | 2017-08-10 |
US20220013434A1 (en) | 2022-01-13 |
US9691746B2 (en) | 2017-06-27 |
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TWI588915B (zh) | 2017-06-21 |
US20180308785A1 (en) | 2018-10-25 |
JP2017520932A (ja) | 2017-07-27 |
KR20170029575A (ko) | 2017-03-15 |
WO2016010702A1 (en) | 2016-01-21 |
TW201606886A (zh) | 2016-02-16 |
JP6317028B2 (ja) | 2018-04-25 |
EP3170200A4 (en) | 2018-01-24 |
US10163755B2 (en) | 2018-12-25 |
EP3170200A1 (en) | 2017-05-24 |
US11776877B2 (en) | 2023-10-03 |
US20160013173A1 (en) | 2016-01-14 |
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