TW201705395A - 具有底部填充控制腔之半導體裝置總成 - Google Patents

具有底部填充控制腔之半導體裝置總成 Download PDF

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TW201705395A
TW201705395A TW105106361A TW105106361A TW201705395A TW 201705395 A TW201705395 A TW 201705395A TW 105106361 A TW105106361 A TW 105106361A TW 105106361 A TW105106361 A TW 105106361A TW 201705395 A TW201705395 A TW 201705395A
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semiconductor
die
cavity
semiconductor device
device assembly
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TW105106361A
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TWI680543B (zh
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安尼庫瑪 查杜魯
韋恩Ｈ 黃
沙彌爾Ｓ 維哈卡
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美光科技公司
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Abstract

本文揭示具有底部填充控制腔之半導體裝置總成。在一實施例中，一半導體裝置總成可包含一第一半導體晶粒，該第一半導體晶粒具有由一基板材料形成之一基底區域、沿著該基底區域之一凹入表面、由該基板材料形成且自該基底區域突出之一周邊區域及沿著該周邊區域且與該側壁表面在該周邊區域中界定一腔之一側壁表面。該半導體裝置總成進一步包含鄰近該腔而附接至該第一晶粒之該周邊區域之一熱傳遞結構及至少部分填充該腔且包含該周邊區域與第二半導體晶粒堆疊之間之一填角料之一底部填充材料。

Description

具有底部填充控制腔之半導體裝置總成
所揭示實施例係關於半導體裝置總成，且特定言之係關於具有底部填充控制腔之半導體裝置總成。
包含記憶體晶片、微處理器晶片及成像器晶片之封裝半導體晶粒通常包含安裝於一基板上且圍封於一塑膠保殼體中之一半導體晶粒。該晶粒包含功能特徵(諸如記憶體單元、處理器電路及成像器裝置)以及電連接至該等功能特徵之接合墊。接合墊可電連接至殼體外部之終端以允許晶粒連接至較高階電路。
半導體製造商不斷減小晶粒封裝之大小以裝配於電子裝置之空間約束內，同時亦增加各封裝之功能容量以滿足操作參數。用於增加半導體封裝之處理能力而實質上不增加由封裝覆蓋之表面積(亦即，封裝之「佔據面積」)之一方法係在一單一封裝中將多個半導體晶粒垂直堆疊於彼此之頂部上。可藉由使用矽穿孔(TSV)電耦合個別晶粒之接合墊與相鄰晶粒之接合墊而使此垂直堆疊封裝中之晶粒互連。
在垂直堆疊的封裝中，產生的熱難以消散，此增加個別晶粒、晶粒之間之接面及封裝整體之操作溫度。在許多類型之裝置中，此可導致堆疊晶粒達到高於其等最大操作溫度(Tmax)之溫度。
100‧‧‧半導體裝置總成
102‧‧‧封裝支撐基板
104‧‧‧第一半導體晶粒
105‧‧‧基底區域
106‧‧‧第二半導體晶粒
108‧‧‧晶粒堆疊
110‧‧‧凹入表面
112‧‧‧周邊區域
114‧‧‧凹槽
115‧‧‧頂部表面
116‧‧‧側壁表面
118‧‧‧殼體
120‧‧‧第一壁部分
124‧‧‧第二壁部分
128‧‧‧積體電路
130‧‧‧底部填充材料
132‧‧‧填角料
134‧‧‧過量部分/過量底部填充材料
140‧‧‧底部填充控制腔
222‧‧‧第一黏著劑
226‧‧‧第二黏著劑
236‧‧‧部分
250‧‧‧半導體基板
252‧‧‧矽穿孔(TSV)
254‧‧‧前側表面
258‧‧‧表面
260‧‧‧介電材料
262‧‧‧第一接合墊
264‧‧‧導電元件/傳導元件
266‧‧‧矽穿孔(TSV)
268‧‧‧第二接合墊
270‧‧‧內表面
300‧‧‧半導體裝置總成
304‧‧‧第一半導體晶粒
316‧‧‧第一側壁表面
317‧‧‧第二側壁表面/第二側壁
340‧‧‧腔
400‧‧‧半導體裝置總成
480‧‧‧系統
482‧‧‧電源
484‧‧‧驅動器
486‧‧‧處理器
488‧‧‧其他子系統/組件
d1‧‧‧深度
g1‧‧‧間隙
g2‧‧‧間隙
h1‧‧‧高度
t1‧‧‧第一厚度
t2‧‧‧第二厚度
w1‧‧‧寬度
圖1係根據本發明技術之實施例之一半導體裝置總成之一截面圖。
圖2A至圖2D繪示根據本發明技術之實施例製造一半導體裝置總成之一方法之截面圖。
圖2E係繪示根據本發明技術之實施例製造一半導體裝置總成之一方法之一截面圖且圖2F係繪示根據本發明技術之實施例製造一半導體裝置總成之一方法之一俯視平面圖。
圖2G係繪示根據本發明技術之實施例製造一半導體裝置總成之一方法之一截面圖且圖2H係繪示根據本發明技術之實施例製造一半導體裝置總成之一方法之一俯視平面圖。
圖3係根據本發明技術之實施例之一半導體裝置總成之一俯視平面圖。
圖4係根據本發明技術之實施例之包含一半導體裝置之一系統之一示意圖。
下文描述具有一底部填充控制腔或經組態以包含過量底部填充材料之相關壩特徵之堆疊半導體晶粒總成之若干實施例之特定細節。術語「半導體裝置」大體上係指包含半導體材料之一固態裝置。一半導體裝置可包含舉例而言一半導體基板、晶圓或自一晶圓或基板分割之晶粒。貫穿本發明，在半導體晶粒之背景內容中大體上描述半導體裝置，然而，半導體裝置不限於半導體晶粒。
術語「半導體裝置封裝」可係指具有併入至一共同封裝中之一或多個半導體裝置之一配置。一半導體封裝可包含部分或完全囊封至少一半導體裝置之一外殼或殼體。一半導體裝置封裝亦可包含承載一或多個半導體裝置且附接至殼體或以其他方式併入至殼體中之一插入器基板。術語「半導體裝置總成」可係指一或多個半導體裝置、半導 體裝置封裝及/或基板(例如插入器、支撐件或其他適合基板)之一總成。
如本文中使用，鑑於圖中所示之定向，術語「垂直」、「橫向」、「上」及「下」可係指半導體裝置中之特徵之相對方向或位置。舉例而言，「上」或「最上」可係指經定位比另一特徵更靠近頁面頂部之一特徵。然而，此等術語可廣泛地理解以包含具有其他定向(諸如，顛倒或傾斜定向，其中頂部/底部、上方/下方、上面/下面、上/下及左/右可取決於定向而互換)之半導體裝置。
圖1係根據本發明技術之一實施例組態之一半導體裝置總成100(「總成100」)之一截面圖。如展示，總成100包含一封裝支撐基板102、基板102上之一第一半導體晶粒104、附接至第一晶粒104上之一熱傳遞結構或殼體118及安裝至第一晶粒104之複數個第二半導體晶粒106。該第一晶粒104包含具有一凹入表面110之一基底區域105、突出遠離基底區域105且具有一頂部表面115之一周邊區域112(此項技術者稱為「隔屏」或「擱板」)及沿著周邊區域112之內部之一側壁表面116。凹入表面110及側壁表面116在周邊區域112內界定底部填充控制腔140。第二晶粒106以一堆疊108(「晶粒堆疊108」)配置於腔140之凹入表面110上且藉由一間隙g1與側壁表面116分離。在圖1展示之實施例中，殼體118包含附接至周邊區域112之一第一壁部分120及橫向延伸於晶粒堆疊108上方之一第二壁部分124。第一壁部分120及第二壁部分124在腔140上方界定一凹槽114(其包含晶粒堆疊108之一部分)。在其他實施例中，第一半導體晶粒104之周邊區域112可延伸至最上第二晶粒106或高於最上第二晶粒106之一高度，且殼體118可係不具有第一壁部分120之一單一面板。在至少一些實施例中，殼體118經組態以大體上在第一壁部分120處吸收及消散熱能遠離第一晶粒104，且大體上在第二壁部分124處吸收及消散熱能遠離晶粒堆疊 108。
第一晶粒104及第二晶粒106可包含多種類型之半導體組件及功能特徵，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體、其他形式之積體電路記憶體、處理電路、成像組件及/或其他半導體特徵。在各項實施例中，舉例而言，總成100可經組態為一混合記憶體立方體(HMC)，其中堆疊第二晶粒106係DRAM晶粒或提供資料儲存之其他記憶體晶粒，且第一晶粒104係在HMC內提供記憶體控制(例如DRAM控制)之一高速邏輯晶粒。在圖1中繪示之實施例中，第一晶粒104包含至少部分延伸至周邊區域112中之一積體電路128。在一實施例中，延伸至周邊區域112中之積體電路128之部分可包含在操作期間產生相對大量熱之一或多個電路組件，諸如串列/解串列器(SERDES)電路。在其他實施例中，第一晶粒104及第二晶粒106可包含其他半導體組件及/或晶粒堆疊108中之個別第二晶粒106之半導體組件可不同。
總成100進一步包含介於第二晶粒106之各者之間及介於第一晶粒104與底部第二晶粒106之間之一底部填充材料130。該底部填充材料130可包含延伸至晶粒堆疊108與側壁表面116之間之間隙g1中之一過量部分134。過量部分134至少部分覆蓋側壁表面116，且包含一填角料132。如下文中更詳細描述，側壁表面116與晶粒堆疊108之間之間隙g1可經定大小以在沈積底部填充材料130期間防止或抑制過量底部填充材料134擴散至周邊區域112上。在其他裝置(其等將一導熱部件附接至一下伏晶粒之周邊區域或隔屏)中，底部填充材料通常在周邊區域上方橫向擴散。一般言之，與一導熱部件(例如，殼體118或第一半導體晶粒104之基板材料)相比，底部填充材料通常係不良熱導體，且因而，此等裝置中之周邊區域與傳導部件之間之底部填充材料可增加熱阻。此外，此等裝置中之底部填充材料之填角料產生傳導部 件與周邊區域之間之一大間隔，此減小周邊區域上之傳導部件之覆蓋區域。
圖1中展示之總成100之若干實施例可提供增強熱性質，其等降低總成100中之個別晶粒104、106之操作溫度使得該等晶粒保持低於其等指定最大溫度(Tmax)。當總成100配置為HMC時，此可非常有用，因為第一晶粒104通常係一邏輯晶粒且第二晶粒106通常係記憶體晶粒，且邏輯晶粒通常以遠高於記憶體晶粒之功率位準(例如5.24W相較於0.628W)操作。此外，在周邊區域112中之積體電路128(例如SERDES電路)通常具有高於在記憶體晶粒下方之邏輯晶粒之部分中之積體電路組件之功率密度，此導致周邊區域處之較高溫度。因而，藉由在腔140內包含底部填充材料130，可改良周邊區域112與殼體128之第一壁部分120之間之熱傳遞量。
圖2A至2H繪示根據本發明技術之實施例製造總成100之一方法之態樣。圖2A係製造總成100之一階段之一截面圖。如展示，第一晶粒104(圖1)可由一半導體基板250(例如，矽晶圓)形成，該半導體基板250已經由例如背部研磨而自一第一厚度t1薄化為一第二厚度t2。第二厚度t2大體上界定周邊區域112之厚度(圖1)。一厚周邊區域112之一優點在於其可改良第一晶粒104之周邊處之熱消散。此外，一厚周邊區域112可減小晶粒翹曲。在一實施例中，第二厚度t2可係約300μm。在其他實施例中，第二厚度t2可小於300μm(例如，約200μm)或大於300μm(例如，約500μm)。
如圖2A中進一步展示，基板250可包含複數個矽穿孔(TSV)252，其等部分延伸至基底區域105處基板之一前側表面254中。TSV 252可在一先前製造階段藉由在前側表面254中蝕刻複數個孔且接著使用一傳導材料(例如銅或銅合金)填充孔而形成。每一TSV 252可包含一導電材料(例如銅)及包圍導電材料以使TSV 252與周圍基板250隔離 之一電絕緣材料(未展示)。
圖2B係繪示在基板250中已蝕刻一凹陷以形成側壁116及凹入表面110(其等在周邊區域112內且在基底區域105上方界定腔140)之後製造總成100之一方法之一後續階段之一截面圖。可藉由圖案化一光阻材料(未展示)層及使用一濕式或乾式蝕刻程序而形成該凹陷。因此，周邊區域112及基底區域105係基板250之材料之整合區域。舉例而言，周邊區域及基底區域可皆包含矽。在圖2B中展示之實施例中，腔140之一深度d1經選擇使得TSV 252之表面258在腔140之凹入表面110處曝露。在至少一些實施例中，腔深度d1可在約50μm至約200μm(例如100μm)之範圍中。在另一實施例中，腔深度d1可係至少200μm。在又一實施例中，腔深度d1可係至少300μm。
在至少一些實施例中，腔深度d1可基於待定位於腔140內之第二晶粒106(圖1)之數目及/或第二晶粒106之厚度而選擇。在若干實施例中，第二晶粒106具有在約50μm至約200μm(例如約60μm)之範圍中之一厚度。在一實施例中，半導體晶粒之整個堆疊(例如三個、四個、六個、八個、十二個、二十個或更多個晶粒之一堆疊)可定位於腔140中。在另一實施例中，晶粒堆疊108之僅一部分定位於腔140中使得一或多個上半導體晶粒定位在腔140之頂部上方。舉例而言，一半之晶粒堆疊、多於一半之堆疊、少於一半之堆疊或堆疊之僅一單一晶粒可定位於腔140中。此外，腔140之寬度、長度及/或形狀可基於晶粒堆疊108之大小(例如晶粒堆疊108之佔據面積)及/或形狀而選擇。在一實施例中，腔140及晶粒堆疊108具有類似平面形狀(例如正方形或矩形形狀)。
圖2C係繪示在周邊區域112之頂部表面115及基底區域105之凹入表面110上已沈積一介電材料260之後且亦在基底區域105處TSV 252上形成第一接合墊262之後製造總成100之一方法之一後續階段之一截面 圖。介電材料260可包含舉例而言一保形膜(例如氧化矽膜)，其覆蓋在腔140之基底處之凹入表面110。可藉由圖案化介電材料260以曝露TSV 252且接著將一傳導材料(例如銅)電鍍於經曝露TSV 252上而形成第一接合墊262。
圖2D繪示在將晶粒堆疊108定位在凹入表面110處接合墊262上之後製造總成100之一方法之後續階段之一截面圖。如圖2D中展示，底部第二晶粒106包含第二接合墊268及將第二接合墊268連接至第一晶粒104之對應第一接合墊262之複數個導電元件264。第二接合墊268繼而可耦合至TSV 266(其等延伸穿過底部第二晶粒106)，且TSV 266可在晶粒堆疊108之每一層級耦合至額外傳導元件264、接合墊268及TSV 266。導電元件264可具有多種適合結構(諸如支柱、柱、支桿、凸塊)且可由銅、鎳、焊料(例如基於SnAg之焊料)製成。除電通信之外，導電元件264及TSV 252、266可提供熱導管，可透過熱導管將熱傳遞遠離第一晶粒104及第二晶粒106。
圖2E係繪示已在第二晶粒106之間及第一晶粒104與底部第二晶粒106之間沈積底部填充材料130之後製造總成100之方法之另一階段一截面圖，且圖2F係繪示該另一階段之一俯視圖。一起參考圖2E及圖2F，底部填充材料130通常係填充第二晶粒106與導電元件264之間之空隙空間之一可流動材料。在一實施例中，可藉由將底部填充材料130微噴射於個別第二晶粒106之間而將底部填充材料注入至空隙空間中。底部填充材料130之體積經選擇以充分填充空隙空間使得過量底部填充材料134進入側壁表面116與晶粒堆疊108之間之間隙g1中以形成填角料132。間隙g1之大小及/或腔深度d1可經選擇以防止或抑制過量底部填充材料134流動至周邊區域112之頂部表面115上且容納底部填充材料130之填角料132。在某些實施例中，在底部填充材料130未完全填充間隙g1之情況中，可曝露側壁表面116之一部分236。在至少 一些實施例中，底部填充材料130可係一非傳導環氧膏(例如由日本，新瀉縣，Namics Corporation Japan製造之XS8448-171)、一毛細底部填充物、一非傳導膜、一模製底部填充物及/或包含其他適合電絕緣材料。底部填充材料130可替代性地係一介電底部填充物(諸如由杜塞爾多夫，德國，Henkel製造之FP4585)。在一些實施例中，底部填充材料130可基於其導熱性而選擇以增強透過晶粒堆疊108之熱消散。
圖2G係繪示在已將殼體118附接至第一晶粒104之周邊區域112之後製造總成100之方法之另一階段之一截面圖，且圖2H係繪示該另一階段之一俯視圖。首先參考圖2G，殼體118之第一壁部分120藉由一第一黏著劑222附接至周邊區域112之頂部表面115，且殼體118之第二壁部分124藉由一第二黏著劑226附接至頂部第二晶粒106。黏著劑222及226可係相同黏著劑，或其等可彼此不同。舉例而言，第一黏著劑222及第二黏著劑226可係熱介面材料(「TIM」)或另一適合黏著劑。舉例而言，TIM及其他黏著劑可包含基於聚矽氧之油脂、凝膠或摻雜有傳導材料(例如碳奈米管、焊料材料、類鑽石碳(DLC)等)以及相變材料之黏著劑。在若干實施例中，殼體118由一導熱材料(諸如鎳、銅、鋁、具有高熱導性之陶瓷材料(例如氮化鋁))及/或其他適合的導熱材料製成。
在經繪示實施例中，殼體118之凹槽114具有符合晶粒堆疊108之形狀之一形狀。在此情況下，凹槽114具有一高度h1(其基於待定位於殼體118中之第二晶粒106之數目而選擇)，且第一壁部分120藉由一間隙g2與晶粒堆疊108隔開，間隙g2經組態以在晶粒堆疊108與第一壁部分120之內表面270之間提供足夠空間以容納填角料132。在一實施例中，殼體118不與底部填充材料130接觸。在至少一些實施例中，第一壁部分120之一寬度w1可經選擇使得第一壁部分覆蓋顯著百分比之周邊區域112。在此等及其他實施例中，第一壁部分120之內表面270可 實質上與側壁表面116共面。參考圖2H，第一壁部分120可經組態以圍繞晶粒堆疊108之至少一部分延伸。在其他實施例中，殼體118並未經組態以符合晶粒堆疊108之形狀。
圖3係根據本發明技術之實施例之一半導體裝置總成300(「總成300」)之另一實施例之截面俯視圖。總成300之若干特徵與上文關於總成100描述之特徵類似。舉例而言，總成300可包含定位於一第一半導體晶粒304之一腔340中之第二半導體晶粒之晶粒堆疊108。然而，在圖3中繪示之實施例中，第一晶粒304包含面向晶粒堆疊108之一第一側壁表面316及成角度遠離第一側壁表面316之一第二側壁表面317。過量底部填充材料134至少部分覆蓋第一側壁表面316及第二側壁表面317。在圖3中繪示之實施例之一態樣中，第二側壁317可增加腔340之體積以包含多於圖1中展示之腔140之過量底部填充材料134。在一相關實施例中，可使用第二側壁317以增加腔340之體積而不增加腔深度d1(圖2B)。
可將上文參考圖1至圖3描述之堆疊半導體裝置總成之任一者併入無數個更大及/或更複雜系統之任一者中，其之一代表性實例係圖4中示意性展示之系統480。系統480可包含一半導體裝置總成400、一電源482、一驅動器484、一處理器486及/或其他子系統或組件488。半導體裝置總成400可包含大體上與上文參考圖1至圖3描述之半導體裝置總成之特徵類似之特徵，且因此可包含增強熱消散之多種特徵。所得系統480可執行任何廣泛多種功能，諸如記憶體儲存、資料處理及/或其他適合功能。相應地，代表性系統480可包含(不限於)手持式裝置(例如行動電話、平板電腦、數位讀取器及數位音訊播放器)、電腦、車輛、家電及其他產品。可將系統480之組件容置於一單一單元中或分佈於多個互連單元(例如透過一通信網路)上。系統480之組件亦可包含遠端裝置及任何廣泛多種電腦可讀媒體。
自前述，應瞭解，為圖解目的已在本文中描述本發明技術之特定實施例，但在不偏離本發明之情況下可作出多種修改。舉例而言，在一實施例中，可將底部填充控制腔140定位成偏離中心，且該腔之一側上之周邊區域112可大於另一側上之周邊區域。此外，雖然關於HMC描述半導體晶粒總成之許多實施例，但在其他實施例中，半導體晶粒總成可經組態為其他記憶體裝置或其他類型之堆疊晶粒總成。另外，亦可在其他實施例中組合或消除在特定實施例之背景內容中描述之新技術之一些態樣。此外，雖然已在該等實施例之背景內容中描述與新技術之特定實施例相關聯之優點，但其他實施例亦可展現此等優點且並非所有實施例需要展現此等優點以落在本發明技術之範疇內。因此，本發明及相關聯技術可涵蓋本文中未明確展示或描述之其他實施例。
100‧‧‧半導體裝置總成
102‧‧‧封裝支撐基板
104‧‧‧第一半導體晶粒
105‧‧‧基底區域
106‧‧‧第二半導體晶粒
108‧‧‧晶粒堆疊
110‧‧‧凹入表面
112‧‧‧周邊區域
114‧‧‧凹槽
115‧‧‧頂部表面
116‧‧‧側壁表面
118‧‧‧殼體
120‧‧‧第一壁部分
124‧‧‧第二壁部分
128‧‧‧積體電路
130‧‧‧底部填充材料
132‧‧‧填角料
134‧‧‧過量部分/過量底部填充材料
140‧‧‧底部填充控制腔
g1‧‧‧間隙

Claims (36)

  1. 一種半導體裝置總成，其包括：一第一半導體晶粒，其具有由一基板材料形成之一基底區域、沿著該基底區域之一凹入表面、由該基板材料形成且自該基底區域突出之一周邊區域及沿著該周邊區域之一側壁表面，且其中該凹入表面及該側壁表面在該周邊區域內界定一腔；一第二半導體晶粒堆疊，其至少部分在該腔中；一熱傳遞結構，其附接至第一半導體晶粒之周邊區域上；及一底部填充材料，其至少部分填充該腔且包含該周邊區域與該第二半導體晶粒堆疊之間之一填角料。
  2. 如請求項1之半導體裝置總成，其中：該側壁表面向內面向該第二半導體晶粒堆疊；且該側壁表面包含曝露之一部分。
  3. 如請求項2之半導體裝置總成，其中該填角料包含介於該側壁表面與該第二半導體晶粒堆疊之間之一第一部分，及介於該熱傳遞結構與該第二半導體晶粒堆疊之間之一第二部分。
  4. 如請求項1之半導體裝置總成，其中：該側壁表面向內面向該第二半導體晶粒堆疊；且該熱傳遞結構包含大體上與該側壁表面共面之一內表面。
  5. 如請求項1之半導體裝置總成，其中：該側壁表面界定面向該第二半導體晶粒堆疊之一第一側壁表面且該第一半導體晶粒進一步包含以一非零角度延伸遠離該第一側壁表面之一第二側壁表面；及該底部填充材料，其至少部分覆蓋該第一側壁表面及該第二側壁表面。
  6. 如請求項1之半導體裝置總成，其中：該熱結構包含界定一凹槽之一第一壁部分及一第二壁部分；及該等第二半導體晶粒之至少一者定位於該凹槽內。
  7. 如請求項1之半導體裝置總成，其中該第一半導體晶粒包含延伸穿過基底部分之複數個矽穿孔，且該等矽穿孔電耦合至該第二半導體晶粒堆疊。
  8. 如請求項1之半導體裝置總成，其中該第一半導體晶粒包含一積體電路。
  9. 如請求項8之半導體裝置總成，其中該積體電路至少部分定位於該周邊區域中。
  10. 如請求項8之半導體裝置總成，其中：該積體電路係一邏輯電路；且該等第二半導體晶粒係記憶體晶粒。
  11. 如請求項1之半導體裝置總成，其中該腔具有至少200μm之一深度。
  12. 如請求項11之半導體裝置總成，其中該第二半導體晶粒各具有在約50μm至約200μm之範圍中之一厚度。
  13. 如請求項1之半導體裝置總成，其中該腔具有至少300μm之一深度。
  14. 如請求項1之半導體裝置總成，其中該第二半導體晶粒堆疊包含該腔中之至少兩個半導體晶粒。
  15. 一種半導體裝置總成，其包括：一邏輯晶粒，其具有一腔；一第一記憶體晶粒，其在該腔中；一熱傳遞結構，其附接至該邏輯晶粒； 一第二記憶體晶粒，其在該第一記憶體中；及一底部填充材料，其介於該第一記憶體晶粒與該第二記憶體晶粒之間且至少部分填充該腔。
  16. 如請求項15之半導體裝置總成，其進一步包括在該第一記憶體晶粒下方且延伸穿過該邏輯晶粒之複數個矽穿孔。
  17. 如請求項15之半導體裝置總成，其中：該邏輯晶粒包含鄰近該熱傳遞結構且藉由一間隙與該第一記憶體晶粒分離之一側壁表面；且該底部填充材料包含至少在該間隙中之一填角料。
  18. 如請求項15之半導體裝置總成，其中該熱傳遞結構附接至該第二記憶體晶粒。
  19. 如請求項15之半導體裝置總成，其中該熱傳遞結構不接觸該底部填充材料。
  20. 如請求項15之半導體裝置總成，其中該邏輯晶粒包含：一周邊區域，其鄰近該腔且附接至該熱傳遞結構；及一積體電路組件，其至少部分定位於該周邊區域中。
  21. 如請求項20之半導體裝置總成，其中該積體電路組件包含一串列/解串列器電路。
  22. 一種形成一半導體裝置總成之方法，其包括：在一半導體基板中形成一腔；將一半導體晶粒堆疊附接至該腔中之一凹入表面；將一底部填充材料沈積於該半導體晶粒堆疊之個別半導體晶粒之間；在該半導體晶粒堆疊與鄰近該腔之該基板之一周邊區域之間累積過量底部填充材料；及將一熱傳遞結構附接至該周邊區域。
  23. 如請求項22之方法，其中沈積該底部填充材料包含：在該等個別半導體晶粒之間注入該底部填充材料。
  24. 如請求項22之方法，其進一步包括：將該熱傳遞結構附接至該半導體晶粒堆疊。
  25. 如請求項22之方法，其中形成該腔包含：將一孔蝕刻至該基板中達至少200μm之一深度。
  26. 如請求項25之方法，其進一步包括：使該基板薄化至300μm或更小之一厚度。
  27. 如請求項22之方法，其中形成該腔包含：將一孔蝕刻至該基板中達至少300μm之一深度。
  28. 如請求項22之方法，其中：形成該腔包含在該基板中蝕刻一孔以在該腔之基底處曝露複數個矽穿孔(TSV)；及附接該半導體晶粒堆疊包含將該堆疊中之該等半導體晶粒之一最底部半導體晶粒之接合墊接合至該等TSV。
  29. 如請求項22之方法，其中該半導體基板包含一積體電路。
  30. 如請求項22之方法，其中附接該熱傳遞結構包含：將該等半導體晶粒之至少一者定位於該熱傳遞結構之一凹槽中。
  31. 一種形成一半導體裝置總成之方法，其包括：將一記憶體晶粒堆疊至少部分定位於一邏輯晶粒之一腔中；用一底部填充材料至少部分填充該腔；將該等記憶體晶粒之至少一者定位於一熱傳遞結構之一凹槽中；及將該熱傳遞結構附接至該邏輯晶粒鄰近該腔之一周邊區域。
  32. 如請求項31之方法，其中用該底部填充材料至少部分填充該腔包含：使過量底部填充材料流動至該記憶體晶粒堆疊與該周邊 區域之間之一間隙中。
  33. 如請求項31之方法，其進一步包括：將該記憶體晶粒堆疊電耦合至該腔之一基底處之複數個矽穿孔。
  34. 如請求項31之方法，其進一步包括：將該熱傳遞結構附接至該等記憶體晶粒之該至少一者。
  35. 如請求項31之方法，其中該邏輯晶粒包含至少部分定位於該周邊區域中之一積體電路組件。
  36. 如請求項35之方法，其中該積體電路組件包含一串列/解串列器電路。
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US9397078B1 (en) 2016-07-19
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CN107408546A (zh) 2017-11-28
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EP3266042A1 (en) 2018-01-10

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