TWI553785B - 具有改良式熱性能之堆疊式半導體晶粒組件及相關之系統及方法 - Google Patents

具有改良式熱性能之堆疊式半導體晶粒組件及相關之系統及方法 Download PDF

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TWI553785B
TWI553785B TW104110528A TW104110528A TWI553785B TW I553785 B TWI553785 B TW I553785B TW 104110528 A TW104110528 A TW 104110528A TW 104110528 A TW104110528 A TW 104110528A TW I553785 B TWI553785 B TW I553785B
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semiconductor die
interposer
die stack
package substrate
stack
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TW104110528A
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TW201601259A (zh
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米契 克普曼斯
羅時劍
大衛Ｒ 亨布里
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美光科技公司
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Description

具有改良式熱性能之堆疊式半導體晶粒組件及相關之系統及方法
所揭示之實施例係關於半導體晶粒組件及管理此等組件內之熱量。特定言之，本發明技術係關於具有一導熱外殼及直接附接至外殼之一插入器之堆疊式半導體裝置組件。
封裝式半導體晶粒(包含記憶體晶片、微處理器晶片及成像器晶片)通常包含安裝於一基板上且圍封於一塑膠保護罩中之一半導體晶粒。晶粒包含功能特徵(諸如記憶體單元、處理器電路及成像器裝置)，以及電連接至功能特徵之焊墊。焊墊可經電連接至保護罩外側之端子以容許晶粒連接至更高階之電路。
半導體製造者不斷減小晶粒封裝之大小以裝配於電子裝置之空間約束內，同時亦增大各封裝之功能能力以滿足操作參數。一種用於增大一半導體封裝之處理能力而實質上不增大由封裝覆蓋之表面積(即，封裝之「佔用面積」)之方法係在一單個封裝中在彼此頂部上垂直堆疊多個半導體晶粒。在此等垂直堆疊式封裝中之晶粒可藉由使用矽穿孔(TSV)將個別晶粒之焊墊與相鄰晶粒之焊墊電耦合而互連。
在垂直堆疊式封裝中，所產生之熱量難以消散，其增大個別晶 粒、其間之接面及封裝整體之操作溫度。在許多類型之裝置中，此可使堆疊式晶粒達到超過其等之最大操作溫度(Tmax)之溫度。
102‧‧‧半導體晶粒
104‧‧‧最外晶粒
105‧‧‧晶粒堆疊/堆疊
106‧‧‧互連件
108‧‧‧貫穿基板互連件
110‧‧‧導熱外殼/外殼/晶粒堆疊
112‧‧‧蓋部分
113‧‧‧壁部分
115a‧‧‧第一介面材料
115b‧‧‧第二介面材料
115c‧‧‧第三介面材料
117‧‧‧底膠充填材料
120‧‧‧插入器
121‧‧‧背側表面
122‧‧‧周邊部分
123‧‧‧焊墊
124‧‧‧活性表面
125‧‧‧焊墊
130‧‧‧封裝基板
132‧‧‧焊墊
133‧‧‧電連接器
135‧‧‧周邊/上表面
140‧‧‧焊料凸塊
200‧‧‧半導體晶粒組件/組件
201‧‧‧外部分
202a‧‧‧邏輯晶粒
202b‧‧‧記憶體晶粒
205‧‧‧半導體晶粒堆疊/晶粒堆疊
209‧‧‧接面
300‧‧‧半導體晶粒組件/組件
323‧‧‧焊墊
327‧‧‧再分佈網路
329‧‧‧電路元件
332‧‧‧焊墊
400‧‧‧半導體晶粒組件/組件
440‧‧‧焊料凸塊/傳導結構
442a‧‧‧第一焊料凸塊
442b‧‧‧第二焊料凸塊
444‧‧‧焊墊
445‧‧‧中間支撐件
446‧‧‧焊墊
448‧‧‧貫穿基板互連件
500‧‧‧半導體晶粒組件/組件
523‧‧‧焊墊
530‧‧‧封裝基板
532‧‧‧焊墊
537‧‧‧腔室
539‧‧‧凹入表面
540‧‧‧焊料凸塊
600‧‧‧半導體晶粒組件
670‧‧‧系統
672‧‧‧電源
674‧‧‧驅動器
676‧‧‧處理器
678‧‧‧其他子系統或組件
圖1至圖5係根據本發明技術之選定實施例組態之半導體晶粒組件之橫截面視圖。
圖6係包含根據本發明技術之實施例組態之一半導體晶粒組件之一系統之一示意性視圖。
下文描述具有改良式熱性能之堆疊式半導體晶粒組件及相關之系統及方法之若干實施例之特定細節。術語「半導體晶粒」大體指稱具有積體電路或組件、資料儲存元件、處理組件及/或在半導體基板上製造之其他特徵之一晶粒。舉例而言，半導體晶粒可包含積體電路記憶體及/或邏輯電路。熟習相關技術者之亦將理解，本技術可具有額外實施例，且可在無下文參考圖1至圖6描述之實施例之若干細節的情況下實踐本技術。
如本文使用，有鑒於圖中展示之定向，術語「垂直」、「側向」、「上部」及「下部」可指稱半導體晶粒組件中之特徵之相對方向或位置。舉例而言，「上部」或「最上部」可指稱經定位比另一特徵更靠近一頁之頂部之一特徵。然而，此等術語應廣泛地理解為包含具有其他定向之半導體裝置。
圖1係根據本發明技術之一實施例組態之一半導體晶粒組件100(「組件100」)之一橫截面視圖。組件100包含經配置於一堆疊105(「晶粒堆疊105」)中之複數個半導體晶粒102及一導熱外殼(「外殼110」)，該外殼經附接至插入於外殼110與晶粒堆疊105之間的一插入器120。插入器120包含一周邊部分122，周邊部分122沿至少一個軸側向延伸超越晶粒堆疊105之外周邊或佔用面積。周邊部分122包含複數 個焊墊123，其等藉由經插入於周邊部分122與封裝基板130之間的個別傳導部件(諸如焊料凸塊140)耦合至一封裝基板130之對應焊墊132。封裝基板130可包含(例如)一插入器、印刷電路板或具有將組件100連接至外部電路(未展示)之電連接器133(例如，焊料凸塊)之其他適當基板。
在圖1之繪示實施例中，焊料凸塊140可包含金屬焊料球。在若干實施例中，焊料凸塊140可具有等於或大於晶粒堆疊105之垂直高度之一垂直高度。舉例而言，取決於晶粒堆疊105之垂直高度，焊料凸塊140可具有在自約200μm至約1mm或更多之範圍中之一垂直高度。焊料凸塊之間距亦可基於焊料凸塊之垂直高度而變化。此外，雖然焊料凸塊140在所繪示之實施例中展示為具有小於其等垂直高度之一間距，但在其他實施例中，間距可係等於或大於垂直高度。
外殼110包含一蓋部分112及附接至蓋部分112或與之一體形成之壁部分113。蓋部分112可藉由一第一介面材料115a(例如，一黏合劑)附接至插入器120之一背側表面121。壁部分113垂直延伸遠離蓋部分112，且藉由一第二介面材料115b(例如，一黏合劑)附接至封裝基板130之一周邊或上表面135。在所繪示之實施例中，外殼110至少部分將晶粒堆疊105封圍於一殼體(例如，一腔室)內。在其他實施例中，外殼110可以不同方式組態或省略。舉例而言，在一項實施例中，壁部分113可自外殼110省略。除提供一保護罩外，外殼110亦可作為吸收熱能且將其消散遠離晶粒堆疊105之一散熱器。因此，外殼110可由一導熱材料製成，諸如具有高導熱率之鎳、銅、鋁、陶瓷材料(例如，氮化鋁)及/或其他適當導熱材料。
在一些實施例中，第一介面材料115a及/或第二介面材料115b可由此項技術中稱為「熱介面材料(thermal interface materials，TIM)」之材料製成，「熱介面材料」經設計以增大表面接面處(例如，在一晶粒表面與一散熱器之 間)之熱傳導。TIM可包含用傳導材料(例如奈米碳管、焊料材料、類鑽碳(DLC)等等)、以及相變材料摻雜之矽基脂、凝膠或黏合劑。在一些實施例中，舉例而言，熱介面材料可由亞利桑那州菲尼克斯市之Shin-Etsu MicroSi公司所製造之X-23-7772-4 TIM製成，X-23-7772-4 TIM具有約3W/m°K至4W/m°K之一導熱率。在其他實施例中，第一介面材料115a及/或第二介面材料115b可包含其他適當材料，諸如金屬(例如，銅)及/或其他適當導熱材料。
在若干實施例中，晶粒堆疊105可藉由一第三介面材料115c(諸如一黏合劑、一晶粒附接材料(例如，一晶粒附接膜或膏)、一介電間隔件或其他適當材料)附接至封裝基板130。在一項實施例中，第三介面材料115c係將晶粒堆疊105與堆疊105下方之封裝基板130電隔離之一介電材料。在另一實施例中，第三介面材料115c可包含用於第一介面材料115a及/或第二介面材料115b之一介面材料(例如，一TIM)。在其他實施例中，可省略第三介面材料115c。舉例而言，在一項實施例中，插入器120可將晶粒堆疊105承載至封裝基板130上方，使得晶粒堆疊105與封裝基板130由一間隙(例如，一空氣間隙)分離。
晶粒堆疊105可經電耦合至插入器120，且藉由複數個互連件106(例如，銅柱、焊料凸塊及/或其他傳導特徵)與彼此電耦合。舉例而言，互連件106之一部分可附接至定位於插入器120之一活性表面124處之對應焊墊125。半導體晶粒102之各者可包含在互連件106之相對側上耦合之複數個貫穿基板互連件108(例如，貫穿基板通孔、TSV等等)。互連件106及貫穿基板互連件108可由各種類型之傳導材料(例如，金屬材料)形成，諸如銅、鎳、鋁等等。在一些實施例中，傳導材料可包含焊料(例如，基於SnAg之焊料)、充填導體之環氧樹脂及/或其他傳導材料。在選定實施例中，舉例而言，互連件106可為銅柱，而在其他實施例中，互連件106可包含更複雜之結構，諸如氮化 物上凸塊結構。在其他實施例中，互連件106可用其他類型之材料或結構替換，諸如一傳導性膏。
除電連通外，互連件106及貫穿基板互連件108亦將熱量遠離晶粒堆疊105且朝向外殼110轉移。在一些實施例中，晶粒堆疊105之一最外晶粒104之貫穿基板互連件108亦可將熱量自晶粒堆疊105轉移至封裝基板130。舉例而言，貫穿基板互連件108可與第三介面材料115c直接接觸。在若干實施例中，組件100亦可包含在半導體晶粒102之間以填隙方式定位以進一步促進穿過晶粒堆疊105之熱轉移之複數個導熱元件或「虛設元件」(未展示)。此等虛設元件可至少大體具有與互連件106及/或貫穿基板互連件108相似之結構及組成，除該等虛設元件並不電耦合至半導體晶粒102之其他電路外。
一底膠充填材料117可經沈積(或以其他方式形成)於晶粒堆疊105之半導體晶粒102中之一些或全部晶粒周圍及/或之間以將互連件106與彼此電隔離及/或增強半導體晶粒102之間的機械連接。底膠充填材料117可為一非傳導性環氧樹脂膏(例如，由日本Niigata之Namics公司製造之XS8448-171)、一毛細管底膠充填物、一非傳導性膜、一經模製底膠充填物及/或包含其他適當電絕緣材料。在一些實施例中，可基於底膠充填材料117之導熱率來選擇底膠充填材料117以增強貫穿晶粒堆疊105之熱消散。
半導體晶粒102之各者可由一半導體基板形成，諸如矽、絕緣體上矽、複合半導體(例如，氮化鎵)或其他適當基板。半導體基板可經切割或單粒化為具有各種電路組件或功能特徵(諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、閃存記憶體、其他形式之積體電路裝置(包含記憶體、處理電路、成像組件)及/或其他半導體裝置)中之任一者之半導體晶粒。在選定實施例中，組件100可經組態為一混合記憶體立方體(HMC)，其中一些半導體晶粒102提供資料儲 存(例如，DRAM晶粒)且半導體晶粒102中之至少一者提供HMC內之記憶體控制(例如，DRAM控制)。在一些實施例中，半導體晶粒102可包含除資料儲存及/或記憶體控制組件外及/或不同於該等組件之其他電路組件。此外，儘管在圖1中展示之晶粒堆疊105包含五個晶粒，但在其他實施例中，堆疊105可包含少於五個晶粒(例如，三個晶粒)或五個以上晶粒(例如，八個晶粒、十個晶粒、十二個晶粒等等)。舉例而言，在一項實施例中，晶粒堆疊105可包含九個晶粒而非五個晶粒。
插入器120可包含一印刷電路板、一半導體基板或經形成不具有積體電路組件之其他適當基板。舉例而言，插入器120可包含由結晶、半結晶及/或陶瓷基板材料(諸如矽、多晶矽、氧化鋁(Al2O3)、藍寶石及/或其他適當材料)形成之一「空白」基板。在此實施例之一項態樣中，插入器120可在不具有貫穿基板互連件之情況下形成，此係因為朝向組件100之頂部而非朝向組件之底部安置插入器120。舉例而言，習知半導體晶粒封裝具有安置於封裝基板與半導體晶粒堆疊之間的插入器。此配置需要插入器具有貫穿基板互連件以將封裝基板與半導體晶粒堆疊電連接。此配置亦需要插入器係薄的以減少貫穿基板互連件之垂直高度及縱橫比。舉例而言，習知插入器(或用來形成插入器之基板)可藉由背面研磨、蝕刻及/或化學機械拋光(CMP)薄化至適當大小。因此，插入器120經定位朝向組件之頂部之一個優點在於插入器120可係相對厚的，且因此消除數個製造步驟。舉例而言，可消除用於形成貫穿基板互連件之基板薄化、穿孔蝕刻及金屬沈積程序。另一優點在於插入器120所增大之厚度可促進熱遠離晶粒堆疊105且朝向插入器之周邊部分122側向轉移。
圖2係根據本發明技術之另一實施例組態之一半導體晶粒組件200(「組件200」)之一橫截面視圖。組件200可包含大體類似於組件 100之彼等特徵之特徵。舉例而言，組件200包含封圍於外殼110內且附接至一半導體晶粒堆疊205(「晶粒堆疊205」)之插入器120。在圖2之所繪示實施例中，晶粒堆疊205包含插入於複數個記憶體晶粒202b之間的一邏輯晶粒202a。邏輯晶粒202a可包含(例如)一記憶體控制器、一串列化器/解串列化器電路及/或其他積體電路組件。個別記憶體晶粒202b可包含(例如)經由互連件106及貫穿基板互連件108可操作地耦合至邏輯晶粒202a之積體電路組件之記憶體單元之陣列或區塊。
在此實施例之一項態樣中，在邏輯晶粒202a與外殼110之間的插入器120之配置可減小操作期間由晶粒堆疊205產生之熱量之數量。一般言之，由一邏輯晶粒(例如，邏輯晶粒202a)產生之熱量可明顯大於由記憶體晶粒(例如，記憶體晶粒202b)共同產生之熱量。舉例而言，一HMC組件中之一邏輯晶粒可消耗操作期間之總電力之80%。在習知半導體晶粒組件中，在插入器朝向組件之底部之情況下定位邏輯晶粒。如此，來自邏輯晶粒之熱量在至組件之外殼途中轉移穿過記憶體晶粒，此增大組件之總體溫度。隨著溫度接近或增大超過最大操作溫度(Tmax)，組件之操作性能下降。舉例而言，常需要降低(例如，邏輯晶粒之)處理速度以將操作維持於一可接受溫度。在一些例項中，舉例而言，需要將資料輸送量減少至最大輸送量位準之四分之一，使得組件停留於Tmax或低於Tmax。相比而言，根據本發明技術之若干實施例組態之HMC及其他晶粒組件可減小穿過記憶體晶粒202b之熱量流。特定言之，插入器120將邏輯晶粒202a定位靠近外殼110以引導熱量流遠離記憶體晶粒202b。此繼而可使邏輯晶粒202a及記憶體晶粒202b能夠在低於Tmax溫度下操作，且因此按更快速度且以更多資料輸送量操作。
在圖2之所繪示實施例中，沿至少一個軸，邏輯晶粒202a之佔用面積大於個別記憶體晶粒202b。在此實施例之一項態樣中，邏輯晶粒 202a之特定積體電路組件可經形成朝向邏輯晶粒202a之一外部分201，外部分201在邏輯晶粒202a與記憶體晶粒202b之間的一接面209周邊。舉例而言，具有較高操作溫度之電路(例如，串列化器/解串列化器電路)可經形成為朝向外部分201。在此等電路經定位朝向外部分201之情況下，接面209轉移更少熱量且因此，晶粒堆疊205可以更低操作溫度操作。
圖3係根據本發明技術之另一實施例組態之一半導體晶粒組件300(「組件300」)之一橫截面視圖。組件300可包含大體類似於組件100之彼等特徵之特徵。舉例而言，組件300包含封圍於外殼110內且附接至晶粒堆疊105之插入器120。在圖3之所繪示實施例中，組件300包含安置於凸起焊墊323與332之間的傳導部件(或焊料凸塊440)。在若干實施例中，焊墊323及/或焊墊332之高度可經組態以容納具有各種大小及/或間距之焊料凸塊。另外或替代地，焊墊323及/或332之高度可經選擇以容納各種高度之晶粒堆疊105。此外，在一些實施例中，可僅凸起一組焊墊323及332。
如在圖3中進一步展示，插入器120包含(例如)傳導跡線、焊墊及/或在焊墊323與125之間電耦合之其他適當傳導結構之一再分佈網路327。如所展示，再分佈網路327可包含在焊墊323與125之間耦合之一或多個電路元件329(示意性展示)。在若干實施例中，電路元件329可包含電容器、電阻器及/或其他適當電路元件。舉例而言，電路元件329可包含經組態以調節藉由一電力供應器(未展示)提供至晶粒堆疊105之電壓或電力之大面積金屬電容器及/或電感器。
圖4係根據本發明技術之另一實施例組態之一半導體晶粒組件400(「組件400」)之一橫截面視圖。組件400可包含大體類似於圖1之組件100之彼等特徵之特徵。舉例而言，組件400包含封圍於外殼110內之插入器120，插入器120經耦合至插入於周邊部分122與封裝基板 130之間的傳導結構440。在圖4之所繪示實施例中，傳導結構440之各者可包含在封裝基板130之焊墊132與一中間支撐件445上之對應焊墊444之間耦合之第一焊料凸塊442a。中間支撐件445可包含將焊墊444電耦合至中間支撐件445之一相對側上之對應焊墊446之貫穿基板互連件448。焊墊446可繼而藉由第二焊料凸塊442b耦合至插入器120之焊墊123。
在此實施例之一項態樣中，中間支撐件445可減小相對於焊料凸塊140(圖1)之高度之第一焊料凸塊442a及第二焊料凸塊442b之高度。在一些實施例中，第一焊料凸塊442a及第二焊料凸塊442b可更小，且傳導結構440可包含額外位準之中間支撐件及焊料凸塊以進一步減小焊料凸塊之高度。舉例而言，在一些實施例中，傳導結構可包含兩個或兩個以上中間支撐件，其中焊料凸塊經安置於中間支撐件之各者之間。在若干實施例中，中間支撐件445可包含至少部分圍繞晶粒堆疊105之周邊之一單一結構。舉例而言，中間支撐件445可包含具有接納晶粒堆疊105之一開口之一圖案化插入器。在另一實施例中，中間支撐件445可包含一金屬框。在其他實施例中，中間支撐件445可包含在一對焊料凸塊之間或在多對焊料凸塊之間的離散元件。
圖5係根據本發明技術之另一實施例組態之一半導體晶粒組件500(「組件500」)之一橫截面視圖。組件500可包含大體類似於圖1之組件100之彼等特徵之特徵。舉例而言，組件500包含封圍於外殼110內且附接至一封裝基板530之插入器120。在圖5之所繪示實施例中，封裝基板530包含一腔室537，腔室537具有凹入於封裝基板530之上表面135下方且藉由第三介面材料115c附接至晶粒堆疊105之一凹入表面539。插入器120經耦合至定位於腔室537外側在插入器120之焊墊523與封裝基板530之對應焊墊532之間的複數個焊料凸塊540。在若干實施例中，焊料凸塊540可類似於圖1之焊料凸塊140，但具有一更小之 垂直高度及/或間距。
在若干實施例中，組件500之垂直輪廓(例如，高度)小於上文參考圖1至圖4分別詳細描述之組件100至400之垂直輪廓。在各種實施例中，組件500之垂直輪廓可部分由腔室537之深度及/或腔室537內之晶粒堆疊105之垂直高度決定。儘管在圖5中展示之晶粒堆疊105完全安置於腔室537內，但在其他實施例中，晶粒堆疊105之一部分可至少部分延伸於腔室537外側(例如，當晶粒堆疊105具有大於腔室537之深度之一高度時)。在一項實施例中，一邏輯晶粒(未展示)可經承載於腔室537外側，而記憶體晶粒(未展示)可保持於腔室537內。此外，在一些實施例中，腔室外側之焊料凸塊540可具有與互連件106之在插入器120與晶粒堆疊105之間的部分相同之高度，而在其他實施例中，焊料凸塊540可具有不同於互連件106之此部分之一高度(例如，一更大之高度)。
上文參考圖1至圖5描述之堆疊式半導體晶粒組件中之任一者可經併入至大量更大及/或更複雜系統中之任一者中，該等系統之一代表性實例係在圖6中示意性展示之系統670。系統670可包含一半導體晶粒組件600、一電源672、一驅動器674、一處理器676及/或其他子系統或組件678。半導體晶粒組件600可包含大體類似於上文描述之堆疊式半導體晶粒組件之彼等特徵之特徵，且因此可包含增強熱量消散之各種特徵。所得系統670可執行許多各種功能(諸如記憶體儲存、資料處理及/或其他適當功能)中之任一者。因此，代表性系統670可包含但不限於手持式裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦及電子設備。系統670之組件可經裝納於一單個單元中或經分佈於多個互連之單元上(例如，透過一通信網路)。系統670之組件亦可包含遠端裝置及許多各種電腦可讀媒體中之任一者。
根據前文將瞭解，在本文中已出於繪示之目的描述本技術之特定實施例，但可在不脫離本發明的情況下做出各種修改。舉例而言，儘管關於HMC描述半導體晶粒組件之許多實施例，但在其他實施例中，半導體晶粒組件可經組態為其他記憶體裝置或其他類型之堆疊式晶粒組件。另外，雖然在所繪示之實施例中，特定特徵或組件已展示為具有特定配置或組態，但其他配置及組態係可能的。舉例而言，圖1之焊料凸塊140可經安置於晶粒堆疊105之一單個側處而非安置於兩個側或多個側處。焊料凸塊140亦可包含比在所繪示實施例中展示之更大或更小數目個焊料凸塊。此外，在特定實施例中，圖2之邏輯晶粒202a可經安置於記憶體晶粒202b與封裝基板130之間而非記憶體晶粒202b與插入器120之間。另外，在特定實施例之內容脈絡中描述之新技術之特定態樣亦可在其他實施例中組合或消除。舉例而言，圖5之組件500可包含圖3之再分佈網路327之電路元件329。再者，儘管與新技術之特定實施例相關之優點已在彼等實施例之內容脈絡中描述，但其他實施例亦可展現此等優點，且並非所有實施例需要必要地展現此等優點來落入本技術之範疇內。因此，本發明及相關技術可涵蓋在本文中未清楚展示或描述之其他實施例。
102‧‧‧半導體晶粒
104‧‧‧最外晶粒
105‧‧‧晶粒堆疊/堆疊
106‧‧‧互連件
108‧‧‧貫穿基板互連件
110‧‧‧導熱外殼/外殼/晶粒堆疊
112‧‧‧蓋部分
113‧‧‧壁部分
115a‧‧‧第一介面材料
115b‧‧‧第二介面材料
115c‧‧‧第三介面材料
117‧‧‧底膠充填材料
120‧‧‧插入器
121‧‧‧背側表面
122‧‧‧周邊部分
123‧‧‧焊墊
124‧‧‧活性表面
125‧‧‧焊墊
130‧‧‧封裝基板
132‧‧‧焊墊
133‧‧‧電連接器
135‧‧‧周邊/上表面
140‧‧‧焊料凸塊

Claims (35)

  1. 一種半導體晶粒組件，其包括：一半導體晶粒堆疊；一導熱外殼；一插入器，其在該導熱外殼與該半導體晶粒堆疊之間，其中該插入器之一周邊部分側向延伸超過該半導體晶粒堆疊；一封裝基板，其承載該導熱外殼；及複數個傳導部件，其等經安置於該封裝基板與該插入器之該周邊部分之間。
  2. 如請求項1之半導體晶粒組件，其中該導熱外殼包含：一蓋部分，其經附接至該插入器之一背側表面；及一壁部分，其在該蓋部分與該封裝基板之間垂直延伸；其中該壁部分經附接至該封裝基板之一外表面。
  3. 如請求項2之半導體晶粒組件，其中該半導體晶粒堆疊包含：一記憶體晶粒堆疊；及一邏輯晶粒，其經安置於該記憶體晶粒堆疊與該插入器之間。
  4. 如請求項1之半導體晶粒組件，其中該晶粒組件進一步包括經插入於該封裝基板與該半導體晶粒堆疊之間的一介面材料。
  5. 如請求項4之半導體晶粒組件，其中：該介面材料係電絕緣的；該半導體晶粒堆疊包含具有延伸穿過其之複數個貫穿基板互連件之一最外晶粒；且該複數個貫穿基板互連件接觸該介面材料。
  6. 如請求項1之半導體晶粒組件，其中該半導體晶粒堆疊進一步包 括：一記憶體晶粒堆疊，其具有一第一佔用面積；及一邏輯晶粒，其具有沿該記憶體晶粒堆疊之至少一個軸大於該第一佔用面積之一第二佔用面積。
  7. 如請求項6之半導體晶粒組件，其中該插入器具有沿該邏輯晶粒之至少一個軸大於該第二佔用面積之一第三佔用面積。
  8. 如請求項6之半導體晶粒組件，其中該等個別傳導部件包含一焊料凸塊。
  9. 如請求項1之半導體晶粒組件，其中該插入器包含將該等傳導部件電耦合至該半導體晶粒堆疊之一再分佈網路，且其中該再分佈網路包含在該等傳導部件之至少一者與該半導體晶粒堆疊之間耦合之一電路元件。
  10. 如請求項9之半導體晶粒組件，其中該電路元件包含一電容器。
  11. 如請求項1之半導體晶粒組件，其中該封裝基板包含：一外表面，其經附接至該導熱外殼；及一凹入表面，其相對於該外表面凹入，其中該半導體晶粒堆疊經附接至該凹入表面。
  12. 一種半導體晶粒組件，其包括：一導熱外殼；一封裝基板，其中該封裝基板及該導熱外殼一起界定一殼體；一插入器，其經附接至該殼體內之該導熱外殼；及一半導體晶粒堆疊，其經安置於該插入器與該殼體內之該封裝基板之間。
  13. 如請求項12之半導體晶粒組件，其中：該插入器包含複數個第一焊墊； 該封裝基板包含複數個第二焊墊；且該半導體晶粒組件進一步包括複數個傳導部件，其中個別傳導部件經安置於個別第一焊墊與個別第二焊墊之間。
  14. 如請求項13之半導體晶粒組件，其中該等個別傳導部件包含一焊料凸塊。
  15. 如請求項13之半導體晶粒組件，其中該複數個傳導部件包含：個別第一焊料凸塊，其等經耦合至該等個別第一焊墊，個別第二焊料凸塊，其等經耦合至該等個別第二焊墊，及一中間支撐件，其經安置於該等個別第一焊料凸塊與該等個別第二焊料凸塊之間。
  16. 如請求項15之半導體晶粒組件，其中該中間支撐件包含一半導體材料。
  17. 一種半導體晶粒組件，其包括：一封裝基板，其具有一腔室；一半導體晶粒堆疊，其至少部分經安置於該腔室內；一插入器，其經附接至該半導體晶粒堆疊，其中該插入器係在該腔室外側；及一導熱外殼，其在該腔室上方側向延伸，其中該導熱外殼包含附接至該封裝基板之一第一部分及附接至該插入器之一第二部分。
  18. 如請求項17之半導體晶粒組件，其中該插入器之一周邊部分側向延伸超過該半導體晶粒堆疊，且其中該半導體晶粒組件進一步包括經插入於該封裝基板與該插入器之該周邊部分之間的複數個焊料凸塊。
  19. 如請求項17之半導體晶粒組件，其中該半導體晶粒堆疊包含一記憶體晶粒堆疊及插入於該記憶體晶粒堆疊與該插入器之間的 一邏輯晶粒。
  20. 如請求項19之半導體晶粒組件，其中該邏輯晶粒在該腔室外側經附接至該封裝基板。
  21. 一種形成一半導體晶粒組件之方法，其包括：將半導體晶粒堆疊附接至一插入器；在一封裝基板與在該插入器之一周邊部分處之一活性表面之間形成焊料凸塊；及將一導熱外殼附接至該插入器之與該活性表面相對之一背側表面以至少部分將該插入器及該半導體晶粒堆疊封圍於一殼體內。
  22. 如請求項21之方法，其中該方法進一步包含：將該導熱外殼附接至該封裝基板。
  23. 如請求項21之方法，其中該方法進一步包含：將該半導體晶粒堆疊附接至該封裝基板，使得該等焊料凸塊在該半導體晶粒堆疊與該導熱外殼之間垂直延伸。
  24. 如請求項23之方法，其中形成該等焊料凸塊包含：形成具有約等於或大於該半導體晶粒堆疊之一垂直高度之一垂直高度之焊料凸塊。
  25. 如請求項21之方法，其中形成該等焊料凸塊包含：將該等焊料凸塊之各者附接至該插入器上之一焊墊且附接至該封裝基板上之一對應焊墊。
  26. 如請求項21之方法，其中形成該等焊料凸塊包含：將第一焊料凸塊附接至該插入器上之第一焊墊，且其中該方法進一步包括：將第二焊料凸塊附接至該封裝基板上之第二焊墊；及將一中間支撐件安置於個別第一焊料凸塊與個別第二焊料凸 塊之間。
  27. 如請求項21之方法，其中該半導體晶粒堆疊包含附接至一邏輯晶粒之一記憶體晶粒堆疊，且其中將該半導體晶粒堆疊附接至該插入器進一步包含將該邏輯晶粒附接至該插入器在該插入器與該記憶體晶粒堆疊之間。
  28. 如請求項27之方法，其進一步包括：在該插入器上形成一再分佈網路，該再分佈網路將該等焊料凸塊電耦合至該半導體晶粒堆疊。
  29. 如請求項28之方法，其中形成該再分佈網路包含：形成在該記憶體晶粒堆疊與該插入器之間電耦合之一電路元件。
  30. 如請求項29之方法，其中該電路元件包含一電容器。
  31. 一種形成一半導體晶粒組件之方法，其包括：將一半導體晶粒堆疊至少部分安置於一封裝基板之一腔室內；將一插入器附接至該半導體晶粒堆疊及該封裝基板之鄰近於該腔室之一周邊表面；及將該插入器至少部分封圍於一導熱外殼內。
  32. 如請求項31之方法，其進一步包括在該封裝基板與在該腔室外側之該插入器之一部分之間形成焊料凸塊。
  33. 如請求項31之方法，其進一步包括將該導熱外殼附接至該封裝基板。
  34. 如請求項31之方法，其進一步包括：將一邏輯晶粒附接至一記憶體晶粒堆疊以形成該半導體晶粒堆疊；及將該記憶體晶粒堆疊在該腔室內附接至該封裝基板。
  35. 一種半導體系統，其包括： 一混合記憶體立方體(HMC)，其包含一封裝基板，一導熱外殼，其界定一殼體，一插入器，其經附接至該殼體內之該導熱外殼，一半導體晶粒堆疊，其在該殼體內，其中該晶粒堆疊包含一記憶體晶粒堆疊及經附接至該記憶體晶粒堆疊之至少一個邏輯晶粒，及複數個焊料凸塊，其等在該插入器與該封裝基板之間耦合，其中該複數個焊料凸塊鄰近於該半導體晶粒堆疊；及一驅動器，其經由該封裝基板電耦合至該HMC。
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