TWI649815B - 用於接合的多重撞擊過程 - Google Patents

用於接合的多重撞擊過程 Download PDF

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TWI649815B
TWI649815B TW105120727A TW105120727A TWI649815B TW I649815 B TWI649815 B TW I649815B TW 105120727 A TW105120727 A TW 105120727A TW 105120727 A TW105120727 A TW 105120727A TW I649815 B TWI649815 B TW I649815B
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Taiwan
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metal
impact
package component
bump
pad
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TW105120727A
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TW201724296A (zh
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邵棟樑
陳筱芸
志航 董
余振華
施玟伶
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台灣積體電路製造股份有限公司
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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
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    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/06—Soldering, e.g. brazing, or unsoldering making use of vibrations, e.g. supersonic vibrations
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Abstract

本揭露提供一方法，包括進行第一撞擊過程以使第一封裝組件的金屬凸塊撞擊第二封裝組件的金屬墊。金屬凸塊與該金屬墊中的一者包括銅，並且該金屬凸塊與該金屬墊中的另一者包括鋁。該方法還包括進行第二撞擊過程以使該金屬凸塊撞擊該金屬墊。進行退火，以使該金屬凸塊接合在該金屬墊上。

Description

用於接合的多重撞擊過程
本揭露涉及一種半導體裝置及其製造方法，特別是涉及用於接合的多重敲擊製程。
由於積體電路的發明，半導體工業已經持續快速增長，此增長歸功於各種電子元元件(即，電晶體，二極體，電阻器，電容器等)整合密度的不斷改進。在大多數情況下，此整合密度的改進是由最小特徵尺寸不斷縮減得來，這使得可以有更多的元件被整合在一個給定的面積裡。
這些整合的改進本質上是以二維(2D)進行，亦即整合元件佔據的體積基本上位於半導體晶片的表面上。儘管光微影技術的明顯改良導致2D積體電路相當大的進步，二維所達到的密度亦有物理上的限制。這些限制之一是這些元件所需的最小尺寸。此外，當一個晶片置入更多的裝置，則需要更複雜的設計。
其他限制則來自於裝置數量增加時，裝置之間互連結構的數量和長度都顯著增加。當互連結構的數量和長度增加，RC延遲和功率消耗都會增加。
因此，三維(3D)積體電路(IC)被研討以解決以上所討論的限制。在一個典型3DIC的形成過程中，兩個晶圓或晶粒(其中每一者都包括一些積體電路)被形成然後被接合在一起。接合通常包括使用 焊料以接合形成在銅凸塊上的鎳層。
根據本揭露的一個實施例，一個方法包括：進行第一撞擊過程以使第一封裝組件的金屬凸塊撞擊第二封裝組件的金屬墊，其中該金屬凸塊中與該金屬墊中的一者包括銅，並且該金屬凸塊與該金屬墊中的另一者包括鋁；進行第二撞擊過程以使該金屬凸塊撞擊該金屬墊；以及進行退火，以使該金屬凸塊接合在該金屬墊上。
根據一些實施例，還包括在該第一撞擊過程之後並在該第二撞擊過程之前的第三撞擊過程，其中該第三撞擊過程包括將該金屬凸塊撞擊該金屬墊。
根據一些實施例，其中在該第一撞擊過程之前，在該金屬凸塊表面上的第一氧化物層以及在該金屬墊表面上的第二氧化物層，兩者都是連續分布的氧化物層，而在該第一撞擊過程中該第一氧化物層撞擊該第二氧化物層。
根據一些實施例，其中在該第一撞擊過程和該第二撞擊過程中，該第一氧化物層和該第二氧化物層破成碎片。
根據一些實施例，其中進行該第一撞擊過程使得該第一封裝組件從與該第二封裝組件分開的位置移動以碰撞該第二封裝組件。
根據一些實施例，其中在該第一撞擊過程和該第二撞擊過程中之每一者之後，該金屬凸塊延伸到該金屬墊。
根據一些實施例，其中在該退火過程中，該金屬凸塊持續延伸到該金屬墊。
根據一些實施例，其中在該第二撞擊過程之後，該金屬凸塊與該金屬墊保持接觸，直到該退火過程完成。
根據本揭露的另一個實施例，一個方法包括：舉起第一封裝組件至第二封裝組件上方並與該第二封裝組件分開；進行第一撞擊過 程以將該第一封裝組件撞擊該第二封裝組件；在該第一撞擊過程之後，舉起該第一封裝組至該第二封裝組件並與該第二封裝組件分開；進行第二撞擊過程以將該第一封裝組件撞擊該第二封裝組件；以及對該第一封裝組件和該第二封裝組件進行退火以將該第一封裝組件接合至該第二封裝組件。
根據一些實施例，其中該第一封裝組件和該第二封裝組件中的一者具有突出的金屬凸塊，並且該第一封裝組件和該第二封裝組件中的另一者具有凹陷的金屬墊，並且在該第一撞擊過程和該第二撞擊過程中，該突出金屬凸塊撞擊該凹陷金屬墊。
根據一些實施例，其中該突出金屬凸塊的表面上的第一氧化物層和該凹陷金屬墊的表面上的第二氧化物層藉由該第一撞擊過程和該第二撞擊過程破裂成碎片，並且在該第二撞擊過程之後，該突出金屬凸塊的未氧化表面與該凹陷金屬墊的未氧化表面實質接觸。
根據一些實施例，其中該第二撞擊過程導致該突出金屬凸塊伸入該凹陷金屬墊，並且在該第二撞擊過程和該退火之間的整個期間，該突出金屬凸塊仍伸入該凹陷金屬墊。
根據一些實施例，其中該凹陷金屬墊的邊緣部分被鈍化層覆蓋，並且在該第一撞擊過程中，該突出金屬凸塊伸入該鈍化層中的開口。
根據一些實施例，其中在該第一撞擊過程和該第二撞擊過程中，該第一封裝組件碰撞該第二封裝組件的速度大於約100微米/秒。
根據本揭露的另一個實施例，一種結構包括：第一封裝組件，其包括含銅凸塊；以及第二封裝組件，其包括含鋁墊，其中該含銅凸塊接合至該含鋁墊，並且該含銅凸塊伸入該含鋁墊。該結構還包含金屬間化合物(IMC)連接該含銅凸塊和該含鋁墊，該金屬間化 合物包含銅和鋁。
根據一些實施例，該結構還包括多個分開並且接觸該金屬間化合物的氧化鋁物件以及多個分開並且接觸該金屬間化合物的氧化銅物件。
根據一些實施例，其中該些多個分開的氧化鋁件和該些多個分開的氧化銅件中的一者被該金屬間化合物包圍。
根據一些實施例，其中該第二封裝組件還包括鈍化層，其覆蓋該含鋁墊的邊緣部分，並且該含銅凸塊伸入該鈍化層的開口。
根據一些實施例，還包括位於第一封裝組件和第二封裝組件之間的底部填充膠，其中該底部填充膠包圍該含銅凸塊。
根據一些實施例，其中該含銅凸塊伸入該含鋁墊達深度大於約0.1微米。
20、120‧‧‧半導體基板
22‧‧‧積體電路元件
24、124‧‧‧層間介電質(ILD)
26、38、48、58‧‧‧蝕刻停止層
28、128‧‧‧接點插塞
30、40、46、50、54‧‧‧金屬間介電(IMD)層
32‧‧‧金屬線
34、71‧‧‧擴散阻障層
36、73‧‧‧含銅材料
42、52、64‧‧‧通路
44‧‧‧導電線
54‧‧‧導電部件
56、60、62‧‧‧介電層
63‧‧‧溝槽
65‧‧‧通路開口
66、66'‧‧‧金屬凸塊
67、167‧‧‧氧化物層
68、70、168、170‧‧‧鈍化層
69‧‧‧介電層60頂面
72‧‧‧金屬墊
74、78‧‧‧聚合物層
76‧‧‧鈍化後互連結構(PPI)
80‧‧‧底部填充膠
82‧‧‧金屬間化合物(IMC)
100‧‧‧晶片、封裝組件
122‧‧‧主動元件
130、140、146、150‧‧‧介電層
132、144、154‧‧‧金屬線
142、152‧‧‧通路
172、172'‧‧‧金屬墊
200‧‧‧晶片、封裝組件
202、204‧‧‧貫穿通路
206‧‧‧封裝材料
300‧‧‧方法
302、304、 306、308‧‧‧步驟
D1、D1'‧‧‧距離
當閱讀隨附的附圖時，從以下詳細的描述可以最清楚地理解本發明的各個方面。需要強調的是，根據本行業的標準做法，各個特徵並非按比例繪製。事實上，各個特徵的尺寸可以任意增大或減小以便進行清楚的討論。
圖1至14顯示根據一些實施例的晶粒/晶圓的形成以及用於形成封裝的接合製程的中間階段截面圖。
圖15至圖17顯示了根據一些實施例的一些已接合封裝的截面圖。
圖18顯示根據一些實施例的通過接合以形成封裝的製程流程。
如下揭露提供了很多不同的實施例或示例，用於實施所提供的主題的不同特徵。如下描述了器件和設置的具體示例，以簡化本發 明。當然，它們僅僅是示例，並不是旨在限制本發明。例如，以下描述中在第二特徵之上或在第二特徵上形成第一特徵可以包括形成直接接觸的第一特徵和第二特徵的實施例，還可以包括在第一特徵和第二特徵之間可以形成附加特徵從而使得第一特徵和第二特徵可以不直接接觸的實施例。此外，本揭露可以在各個示例中重複使用符號和/或字母。這種重複使用用於簡化和清楚的目的，其本身並不表明該的各個實施例和/或配置之間的關係。
而且，空間關係術語，例如“之下”、“下方”、“下麵”、“之上”、“上方”等，在此用於簡化描述附圖所示的一個單元或特徵對另一個單元或特徵的關係。除了附圖中描寫的方向，空間關係術語旨在包含使用或步驟的裝置的不同方向。裝置可以以其他方式定向(旋轉90度或者在其他方向)，並可以據此同樣地解釋本文所使用的空間關係描述語。
本揭露根據各種示例性實施例，提供一種封裝及其形成方法。本揭露亦顯示形成該封裝結構的中間階段。本揭露也針對一些實施例的變化進行討論。在各個視圖和示例性實施例中，類似的參考數字用於表示相同的元件。
圖1至14顯示了根據一些實施例的形成封裝的中間階段截面圖。在圖1至14所示的步驟中還在圖18所顯示的製程流程中顯示。
圖1顯示封裝組件100的截面圖。根據本揭露的一些實施方案，封裝組件100是元件晶圓，其包括主動元件(例如電晶體和/或二極體)，以及可能的被動元件(諸如電容器、電感器、電阻器)，或類似物。根據本揭露的替代實施例中，封裝組件100是一個中介晶片，其可包括或可不包括主動元件和/或被動元件。按照本揭露的又另一種實施方案，封裝組件100是封裝基板條，其可以是有核心封裝基板或無核心封裝基板。在隨後的討論中，元件晶片被用作為示例性封裝組 件100。本揭露的概念也可應用到中介晶片、封裝基板等。
根據本揭露的一些實施方案，示例性的晶片100包括半導體基板20，並在半導體基板20的頂表面上形成的部件。半導體基板20的材料可以是結晶矽、結晶鍺、矽鍺、和/或III-V族化合物半導體，如磷砷化鎵、砷化銦鋁、鋁鎵砷、砷化銦鎵、磷化銦鎵、砷磷化鎵銦，和類似物。半導體基板20也可以是塊狀矽基板或絕緣體上矽(SOI)基板。在半導體基板20中可以形成淺溝槽隔離(STI)區(未顯示)，以隔離半導體基板20中的有源區。雖然沒有顯示在圖中，貫穿通路也可以形成而延伸至半導體基板20中，其中該貫穿通路用於電性耦接晶片100相對兩側上的的導電部件。
根據本揭露的一些實施方案，晶片100包括積體電路元件22，其形成於半導體基板20的的頂部表面上。示例性的積體電路元件22包括互補金屬氧化物半導體(CMOS)電晶體，電阻器，電容器，二極體，和類似物。積體電路元件22中的細節未顯示於本文中。根據替代實施方式，晶片100被用於形成中介組件，而不帶有主動元件，其中基板20可以是半導體基板或介電質基板。
層間介電質(ILD)24形成在半導體基板20上方，並且填充於電路元件22中電晶體(未顯示)的柵極堆疊之間的空間中。根據一些示範實施例，ILD 24包括磷矽酸鹽玻璃(PSG)、硼矽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、摻氟矽酸鹽玻璃(FSG)、原矽酸四乙酯(TEOS)、或類似物。ILD 24可以使用旋塗、可流動化學氣相沉積(FCVD)、或類似物形成。根據本揭露內容的替代實施例，ILD 24係使用沉積方法，如電漿輔助化學氣相沉積(PECVD)、低壓化學氣相沉積(LPCVD)等方式形成。
接點插塞28形成在ILD 24中，並且用於電性連接積體電路元件22與位於上方的金屬線和通路。根據本揭露的一些實施方案，接點插塞 28由導電材料形成，例如鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、上述元素的合金、和/或其複層。接點插塞28的形成可包括：形成在ILD 24中的開口，填充導電材料於接點開口，並進行平面化(例如化學機械拋光(CMP))以使接點插塞28的頂面與ILD 24的頂面齊平。
圖1還顯示，蝕刻停止層26形成在ILD 24和積體電路元件22(如果有的話)上方。蝕刻停止層26可以碳化矽、氮化矽、氧氮化矽、矽碳氮化物、或類似物形成。蝕刻停止層26也可以具有相對於上覆的介電層30高蝕刻選擇比的材料形成，因此蝕刻停止層26可被用於停止對介電層30的蝕刻。
在圖1中進一步顯示介電層30，其在本揭露以下亦可另稱為金屬間介電(IMD)層30。根據本揭露的一些實施例中，IMD層30由具有介電常數(k值)大於約3.0以下、約2.5以下、或甚至更低的低k介電材料形成。IMD層30可以黑鑽石(應用材料公司的註冊商標)，含碳的低k介電材料、氫倍半矽氧烷(HSQ)、甲基倍半矽氧烷(MSQ)、或類似物形成。IMD層30也可具有低k值，其可以是比約3.0、2.5或2.0更小。根據本揭露的一些實施例中，IMD層30的形成方式包括沉積含有成孔劑的介電材料，然後進行固化處理以驅除成孔劑，因此剩餘的IMD層30是多孔的。按照替代實施例，IMD層30以非低k介電材料形成，例如氧化矽、氮化矽、碳化矽、氮氧化矽或類似物。
導電線32形成在IMD層30中。根據一些實施方案，金屬線32包括擴散阻障層34和位於擴散阻障層34上方的含銅材料36。擴散阻障層34可包括鈦、氮化鈦、鉭、鉭氮化物或類似物，並具有防止含銅材料36的銅擴散到IMD層30的功能。本揭露以下也稱導電線32為金屬線32。導電線32的形成可以包括單鑲嵌製程。
蝕刻停止層38和IMD層40形成在IMD層30和導電線32上方。根據本揭露的一些實施方案，蝕刻停止層38可由碳化矽、氮化矽、氮氧化 矽，矽碳氮化物或類似物中所選擇的介電材料形成。IMD層40可以低k介電材料或非低k介電材料形成，並且IMD層40的材料可以選擇用於形成IMD層30同一組的候選材料中來形成。
導電通路42和導電線路44經形成以電性耦接到導電線32。根據本揭露的一些實施方案，通路42的形成和導電線44包括形成通路開口和溝槽，進行毯式沉積到形成導電襯墊，沉積具有銅或銅合金的薄種晶層(未顯示)，並藉由例如電鍍、無電鍍、沉積、或類似方法以導電性材料填充開口其餘部分以及溝槽。導電襯墊可以鈦、氮化鈦、鉭、氮化鉭或其他替代物形成。該導電材料可包括銅、銅合金、銀、金、鎢、鋁或類似物。進行平坦化(例如CMP)製程以平坦化導電襯層和上述導電材料的表面，並從IMD層40的頂部表面上除去多餘的材料。
圖1還示意地顯示了多個介電(IMD)層46以及介電層46中相應的導電線和通路(未顯示)。介電層46的數目是由封裝組件100的走線需求而決定，並且根據一些示範性實施例，可以有從0到7或更大數目的範圍。IMD層46的數目等於0，即表示隨後形成的蝕刻停止層48和介電層56直接形成在IMD層40上方，中間沒有額外的介電層和在其間的導電線。IMD層46中的導電線路和通路(未顯示)電耦接到積體電路裝置22。
蝕刻停止層48和IMD層50形成在介電層46上方。根據本揭露的一些實施方案，蝕刻阻擋層48是由選擇用於形成蝕刻停止層26的相同群組的候選介電材料而形成，其中該候選材料可包括碳化矽、氮化矽、氧氮化矽、矽碳氮化物或類似物。IMD層50也可以由低k介電材料或非低k介電材料形成，並且IMD層50的材料可由用於形成IMD層30和40同一群組的候選材料中選擇。
參照圖1，通路52和導電部件54在IMD層50中形成。通路52和導 電部件54的材料可以從用於形成通路42和導電線44的同樣候選材料中選擇。形成製程也類似於通路42和導電線44，因此在此不再重複。導電部件54包括導電墊和可能會有的導電線。
參照圖2，IMD層50形成在介電層62中。根據本揭露的一些實施方案，介電層62由非低k介電材料形成。例如在圖2中，介電層62包括IMD層50上的層56，位於層56上方的蝕刻停止層58和蝕刻停止層58上的層60。根據本揭露的一些示例性實施例，介電層56和60由非摻雜矽酸鹽玻璃(USG)形成，並且蝕刻停止層58的材料(如氮化矽)不同於介電層56和60的材料。根據替代實施例，介電層62整體是由同質的介電材料，例如USG，所形成。
參照圖3，形成溝槽63和通路開口65，並且金屬部件54的墊部露出。根據一些實施方案，通路開口65的橫向尺寸比溝槽63的橫向尺寸更小，如圖3所示。根據替代實施方式，通路開口65的橫向尺寸與溝槽63的橫向尺寸基本上相同。因此，溝槽63和通路開口65一起組成開口，其具有直線邊緣，一路從介電層62的頂面延伸至底面。當介電層62以相同的材料製成，則以單一蝕刻製程來形成開口。
圖4顯示形成通路64和金屬凸塊66。根據一些實施方案，如圖4所示，通路64和金屬凸塊66包括擴散阻障層71和含銅材料73。根據替代的實施例(參照圖6)，通路64和金屬凸塊66包括含銅材料，而不形成擴散阻障層。如圖4所示，含銅材料73的含銅比例可大於約70%或90%的原子百分比。含銅材料73基本上也可以由純銅製成(例如銅原子百分比大於約99%)。
在形成金屬凸塊66後，執行回蝕以使金屬凸塊66至少一部份突出於剩餘介電層62的頂面。舉例而言，如圖5所示，介電層60被蝕刻，其中蝕刻停止層58阻擋其蝕刻，並且在蝕刻之後露出。根據替代實施方式，蝕刻在蝕刻介電層60的底部被蝕刻之前停止。例如，時間 模式可用於中止刻蝕。相應地，虛線69是用來說明產生的介電層60的頂面。圖6顯示一結構，其中在金屬凸塊66中不形成擴散阻障層。在圖1-6中所示的製程步驟顯示於圖18中步驟302中所示的製程流程。
圖7顯示了根據替代實施例的封裝組件100的橫截面圖。在這些實施方案中，鈍化層68形成在頂部低k介電層上方。金屬墊72形成在鈍化層68上方，並且藉由金屬線和通路電性耦合到積體電路元件22。金屬墊72可以是鋁墊或鋁-銅墊，並可使用其它金屬材料。
鈍化層70被形成以覆蓋金屬墊72的邊緣部分，並且金屬墊72的中央部分經由鈍化層70中的開口暴露。鈍化層68和70的每一者可以是單層或複合層，並且可以非低k介電材料形成。按照本揭露一些實施方案，鈍化層68和70其中一者或兩者是組合層，包括氧化矽層(未顯示)以及在氧化矽層上方的氮化矽層(未顯示)。
聚合物層74形成在鈍化層70上方。聚合物層74可以由聚合物形成，例如聚醯亞胺、聚苯並噁唑(PBO)、苯並環丁烯(BCB)或類似物。聚合物層74經圖案化，而且鈍化後互連結構(PPI)76被形成，其包括覆蓋聚合物層74的第一部分以及延伸到聚合物層74中的第二部分，以電耦接金屬墊72。聚合物層78被形成在聚合物層74上方。聚合物層78可包括聚醯亞胺或其它聚合物基材料，如PBO或BCB。金屬凸塊66延伸到聚合物層78並接觸PPI 76。金屬凸塊66可包括凸塊下金屬(UBM)和在該UBM上方的含銅材料，如圖所示。
圖8顯示了根據一些實施方案的封裝組件200的截面圖。封裝組件200可以包括半導體基板120、主動元件122、ILD 124、接點插塞128、金屬線132、144和154、和通路142和152。此外，封裝組件200可包括低k介電層130、140、146和150。金屬墊172以及鈍化層168、170也被形成。鈍化層170的一些部分可覆蓋金屬墊172的邊緣部分。根據一些實施例，金屬墊172具有鋁，含量大於約70%或約90%原子 百分比，或者可以形成實質上的純鋁(例如，鋁的原子百分比大於約99%)。
圖9至圖14顯示了根據一些實施方案的接合封裝組件100和200的橫截面圖中間階段，其中的多重撞擊方法是在接合時進行。封裝組件100和200在圖9到13已經過簡化，而封裝組件100和200的詳細結構可以藉由參照圖1-8中得到。
圖9顯示了初始階段，其中封裝組件100和200彼此隔開。封裝組件100和200可以是單獨的晶粒或未切割的晶圓。因此，圖9-13所顯示的接合製程，可以是晶粒(die)對晶粒接合、晶圓對晶圓(wafer)接合或晶粒對晶圓的接合製程。封裝組件100中的金屬凸塊66包括在其表面氧化層67。氧化層67也可位於金屬凸塊66的側壁，如在圖13所示意性表示。氧化物層67可以是天然的氧化物層。例如，當金屬凸塊66是銅凸塊，氧化物層67是氧化銅層。封裝組件200中的金屬墊172包括在表面上的氧化物層167。氧化物層167也可以是天然的氧化物層。例如，當金屬墊172是鋁墊，氧化物層167是鋁氧化物層。氧化物層67和167是連續的氧化物層而完全覆蓋金屬凸塊66和金屬墊172。
封裝組件100以例如使用真空吸頭拿起，使得金屬凸塊66與金屬墊172分開。接著，將封裝組件100朝向封裝組件200移動，使金屬凸塊66撞擊金屬墊172。相對應的製程步驟顯示在圖18中的步驟304。撞擊的結果是，連續分布的氧化物層67和167被分解成較小的碎片。此外，金屬凸塊66和金屬墊172一些原來被覆蓋未氧化的表面藉由目前非連續分布的氧化物層67和167而露出。
封裝組件100的速度(在碰撞的當時)可大到足以破壞氧化層67和167達到顯著的百分比。例如，受碰撞的金屬凸塊66和金屬墊172中未氧化的表面有超過10%，20%，30%，40%，或50%或更高比例露出，其取決於撞擊次數。如果要進行較少次的撞擊，在每次撞擊中， 金屬凸塊66和金屬墊172中未氧化的表面有更高比例藉由每次撞擊而露出。要破壞氧化物層67和167，封裝組件100和200之間的相對速度要夠高。例如，在產生碰撞的時刻，金屬凸塊66和金屬墊172的相對速度可大於約100微米/秒。
圖10顯示封裝組件100和200發生碰撞時的截面圖，其中氧化物層67和167顯示破碎成小塊，並且金屬凸塊66和172的一些表面經由更小的碎片間的間隙而露出。可以理解，縱使圖10至12所顯示的碎片樣式較為規則，氧化物層67和167的碎片樣式是任意的形狀。
參照圖11，封裝組件100被再次拿起，直到它與封裝組件200分開。進行第二撞擊過程，如圖12所顯示。相對應的製程步驟顯示於圖18中步驟306所示的製程流程中。第二撞擊導致已經破碎的氧化物層67和167的碎片進行進一步破碎成更小的碎片。此外，作為第二撞擊過程的結果，金屬凸塊66和金屬墊172中更多未氧化的表面經由氧化物層67和167的碎片而露出。第二撞擊可能導致金屬凸塊66暴露的表面百分比增加(相比於第一擊)超過約10%。就在第二撞擊過程產生碰撞的當時，金屬凸塊66和金屬墊172的相對速度可大於約100微米/秒。
在第二撞擊過程之後，金屬凸塊66未氧化的的一些暴露表面與未氧化的金屬墊172的暴露表面直接接觸。根據一些實施例，在第二撞擊過程之後進行更多次撞擊過程，每一次都造成氧化層67和167破碎成更小塊，並可能導致更多未氧化的表面被暴露。撞擊過程的數目係在控制中以防止封裝組件100和200的其他部分被破壞。例如，撞擊過程的總數小於10。根據替代實施例，在第二撞擊之後不再進行更多的撞擊過程，並對封裝組件100和200進行退火。
按照替代性實施方案，進行撞擊過程使得氧化層67和對應的氧化物層167在整個撞擊過程中一直保持接觸。例如，氧化物層67首先 被置於與相應的氧化物層167接觸(不撞擊)。接著，一種工具(類似錘子，未顯示)被用來撞擊與封裝組件200接觸的封裝組件100。每次撞擊期間以及撞擊與撞擊中間，封裝組件100與封裝組件200保持接觸。
在撞擊過程完成時，金屬凸塊66所有直接接觸所對應金屬墊172的未氧化部分的未氧化表面具有一個總面積。該總面積與金屬凸塊66的總底面面積之比可以大於約30%，這比例最好能提高，以增加接合可靠度。
在撞擊過程期間和不同撞擊過程之間，封裝組件100和200可以不加熱，並且可以是在室溫(例如約17℃和約23℃之間)下。在最後撞擊過程(可以是第二或更多次撞擊過程)之後，金屬凸塊66與相應的金屬墊172保持接觸而不再分開。然後進行退火，在此期間，金屬凸塊66也與相應的金屬墊172保持接觸。相對應的製程步驟顯示為圖18中步驟308所示的處理流程。退火可以在溫度範圍約150℃至約250℃之間進行。退火的持續時間可以在約1.5小時與約2.5小時之間。
在進行退火時，直接接觸的銅和鋁是進行相互擴散(銅比鋁具有較高擴散率)。在氧化物件67和167存在的地方，基本上不發生相互擴散。擴散的結果是，形成金屬間化合物(IMC)82，如圖13示意性顯示，並且因此金屬凸塊66與金屬墊172接合。IMC 82包括銅和鋁的合金，以及金屬凸塊66和金屬墊172中其他可能的元素(如果有的話)。在封裝組件100和200接合後，可將底部填充膠80填入封裝組件100和200之間的間隙。底部填充膠80可與金屬凸塊66側壁上的氧化層67接觸，並與氧化物層167接觸。
由於金屬凸塊66的底部轉換成IMC 82，其餘未轉換的金屬凸塊66部分被稱為金屬凸塊66'。同樣，本文以下金屬墊172未轉換的剩餘部分稱為金屬墊172'。圖14顯示金屬凸塊66'和金屬墊172'的部分放大 圖。如在圖14中示意性所示，金屬凸塊66和金屬襯墊172的介面，存在氧化物部分67，氧化物部分167和IMC 82，其將(未氧化的和未合金化的)金屬凸塊66'與(未氧化和非合金的)金屬墊172'分開。某些氧化物部分67(或167)可具有金屬凸塊66'接觸的頂面及與金屬墊172'接觸的底面。一些其他氧化物部分67(或167)可能完全位於IMC 82中(並且被其包圍)。因此，IMC 82的某些部分氧化物67和167可以形成被IMC 82完全包圍(或環繞)的島狀結構，有些IMC 82部分可能被氧化物部分67和/或167包圍。另外，金屬凸塊66'可以延伸到金屬墊172'達深度D1(亦即氧化物層167(未改變部分)的底面和金屬凸塊66'最低點之間的垂直距離)，其根據一些實施例大於約0.1微米。值得注意的是，原來的金屬凸塊66被撞擊至金屬墊172'達距離D1'，該距離為氧化物層167的底面和IMC 82的中間點(假設轉換成IMC 82的金屬凸塊66部分和金屬墊172部分具有相同的厚度)之間的垂直距離。
根據一些示例性實施例，金屬凸塊66是銅凸塊，並且金屬墊172是鋁墊。根據其它實施方案，金屬凸塊66是鋁凸塊，並且金屬墊172是銅墊。
圖15至圖17顯示根據一些實施例的一些應用。在圖15和17中封裝組件100和200的接合結構和接合製程，與圖1-14所顯示的大致上相同，因此在此這些應用不重複製程細節和材料。圖15顯示一晶圓上晶片(Chip-on-Wafer，CoW)的結構，其中晶片100接合到晶圓200。晶圓200可以是其中包括主動元件的元件晶圓，或是沒有主動元件的中介晶片。貫穿通路202穿過晶片200的基板(例如半導體基板)。
圖16顯示了整合的扇出(InFO)結構，其包括通過貫穿通路204穿過封裝材料(如模塑物)206。晶片100接合到晶片(或晶片)200中，其中封裝材料206也封裝在其中的晶片100。圖17顯示與圖16的結 構類似的結構，其中兩個晶片100接合到同一晶片200。
本揭露的實施例具有一些有利的特性。通過直接接合銅與鋁，在習知接合結構中會用到的銲料區域、鎳層、或類似者，將不再需要。可以進行多重撞擊過程，因此沒有必要使用化學溶液以去除氧化物層。因此，可節省接合製程的成本，並提高接合製程的產量。銅凸塊可直接形成為各對應的晶圓/晶粒的頂部金屬層，因此相應的晶片結構和形成製程中可以簡化，並降低成本。
根據本揭露的一些實施方案，一種方法包括：進行第一撞擊過程以使第一封裝組件的金屬凸塊撞擊第二封裝組件的金屬墊，其中該金屬凸塊中與該金屬墊中的一者包括銅，並且該金屬凸塊與該金屬墊中的另一者包括鋁；進行第二撞擊過程以使該金屬凸塊撞擊該金屬墊；以及進行退火，以使該金屬凸塊接合在該金屬墊上。
根據本揭露的一些實施方案，一種方法包含：舉起第一封裝組件至第二封裝組件上方並與該第二封裝組件分開；進行第一撞擊過程以將該第一封裝組件撞擊該第二封裝組件；在該第一撞擊過程之後，舉起該第一封裝組至該第二封裝組件並與該第二封裝組件分開；進行第二撞擊過程以將該第一封裝組件撞擊該第二封裝組件；以及對該第一封裝組件和該第二封裝組件進行退火以將該第一封裝組件接合至該第二封裝組件。
根據本揭露的一些實施方式，一種結構包括第一封裝組件，其包括含銅凸塊。該結構還包括第二封裝組件，其包括含鋁墊，其中該含銅凸塊接合至該含鋁墊，並且其中該含銅凸塊伸入該含鋁墊。該結構另包含金屬間化合物(IMC)連接該含銅凸塊和該含鋁墊，該金屬間化合物包含銅和鋁。
前面概括了幾個實施例的特徵，使得本領域技術人員可更好地理解本揭露的各個方面。本領域技術人員應該明白他們可以將本揭露 當作基礎，用來設計或修改用於執行相同目的和/或獲得在此介紹的實施例的相同好處的其他過程和結構。本領域技術人員也可意識到這樣等同的構造並不脫離本揭露的精神和保護範圍，並且在不脫離本揭露的精神和保護範圍的情況下，他們可以在此做各種改變、替換和修改。

Claims (10)

  1. 一種接合方法，包括：進行第一撞擊過程以使第一封裝組件的金屬凸塊撞擊第二封裝組件的金屬墊，其中該金屬凸塊中與該金屬墊中的一者包括銅，並且該金屬凸塊與該金屬墊中的另一者包括鋁；進行第二撞擊過程以使該金屬凸塊撞擊該金屬墊；以及進行退火，以使該金屬凸塊接合在該金屬墊上。
  2. 根據請求項1所述的方法，還包括在該第一撞擊過程之後並在該第二撞擊過程之前的第三撞擊過程，其中該第三撞擊過程包括將該金屬凸塊撞擊該金屬墊。
  3. 根據請求項1所述的方法，其中在該第一撞擊過程之前，在該金屬凸塊表面上的第一氧化物層以及在該金屬墊表面上的第二氧化物層，兩者都是連續分布的氧化物層，而在該第一撞擊過程中該第一氧化物層撞擊該第二氧化物層。
  4. 根據請求項3所述的方法，其中在該第一撞擊過程和該第二撞擊過程中，該第一氧化物層和該第二氧化物層破成碎片。
  5. 根據請求項1所述的方法，其中進行該第一撞擊過程使得該第一封裝組件從與該第二封裝組件分開的位置移動以碰撞該第二封裝組件。
  6. 根據請求項1所述的方法，其中在該第一撞擊過程和該第二撞擊過程中之每一者之後，該金屬凸塊延伸到該金屬墊。
  7. 根據請求項1所述的方法，其中在該退火過程中，該金屬凸塊持續延伸到該金屬墊。
  8. 根據請求項1所述的方法，其中在該第二撞擊過程之後，該金屬凸塊與該金屬墊保持接觸，直到該退火過程完成。
  9. 一種接合方法，包括：舉起第一封裝組件至第二封裝組件上方並與該第二封裝組件分開；進行第一撞擊過程以將該第一封裝組件撞擊該第二封裝組件；在該第一撞擊過程之後，舉起該第一封裝組至該第二封裝組件並與該第二封裝組件分開；進行第二撞擊過程以將該第一封裝組件撞擊該第二封裝組件；以及對該第一封裝組件和該第二封裝組件進行退火以將該第一封裝組件接合至該第二封裝組件。
  10. 一種接合結構，包括：第一封裝組件，其包括含銅凸塊；第二封裝組件，其包括含鋁墊，其中該含銅凸塊接合至該含鋁墊，並且其中該含銅凸塊伸入該含鋁墊；以及金屬間化合物(IMC)連接該含銅凸塊和該含鋁墊，該金屬間化合物包含銅和鋁。
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CN107017175B (zh) 2019-05-21
CN107017175A (zh) 2017-08-04

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