I23674々64i— 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路載板，且特別是有關於一 種線路載板，其表面所配置之接合塾的内部分佈有多數 個阻障粒子（barrier particle) ’其可提高接合墊之電移阻 抗（electromigration resistance ) 〇 【先前技術】 覆晶接合技術（flip chip interconnect technology)係 為一種將晶片（die)連接到承載器（carrier)的封裝技 術’其主要係將晶片之多個輝墊（pa(j)，利用面陣列（area array)的排列方式，配置於晶片之主動表面（acdve surface)上，並在各個銲墊上分別依序形成球底金屬層 (Under Bump Metallurgy，UBM)及凸塊（bump)，其例 如為銲料凸塊（solder bump)，接著將晶片翻面（flip) 之後，再利用這些凸塊來將晶片之主動表面上的這些銲 墊分別電性及結構性地連接至一承載器（例如^板 (substrate)或印刷電路板（printed circuit board， 之表面的多個接點。值得注意的是，由於覆晶接合技貧 可適用於向接腳數（high pin count)之晶片封裝、社構L 並具有縮小封裝面積及縮短訊號傳輸路徑等優點， 覆晶接合技術已廣泛地應用在晶片封裝結構，且牲侍 具有高腳位之晶片封裝結構。 狩別是 請參考第1圖，其繪示為習知之一種線路 面示意圖。線路載板100包含一基板110、多個接g 1236746 12641twf.doc (bonding pad) 120 (圖僅繪示其一）、一銲罩層（s〇lder mask layer) 130及一保護層14〇，其中基板包含多 個線層夕個絕緣層及多個導電孔（concjuctiVe via)(圖 均未繪不），而每一絕緣層係配置於相鄰兩導線層之間， 且每一導電孔係穿過絕緣層而與至少兩導線層相互連 接。此外’這些接合墊12〇係配置於基板11()之表面U2 上’用以分別連接多個銲料塊（s〇lder bump) 1〇‘（圖僅 繪示其一），例如為覆晶接合用之凸塊（flipchipbump)， 其中接合墊120係可由基板11〇之最外層的導線層所構 成。此外，由於基板110之導線層的材質通常為銅，所 以接合墊120之材質亦為銅。另外，銲料塊1〇則是作為 基板110與晶片20相連接之接點，而銲料塊1〇之材質 例如為含錯銲料或無錯鮮料。 請同樣參考第1目，銲罩層13〇係覆蓋於基板11〇 的表面112，且銲罩層13〇具有多個開口 132 (圖僅繪示 其一）’開口 132係分別暴露出局部的接合墊12〇，其中 銲罩層130可限制住銲料塊1〇之底部的流動，以避免相 鄰兩銲料塊10於迴銲（refl〇w)時彼此溶接，而造成相 鄰兩接合墊120之間的短路。此外，為了防止銅材質之接 合墊120的表面發生氧化，通常會在接合墊12〇之局部暴 露的表面上配置一保護層14〇,其例如為一鎳/金層 layer)。值得注意的是，當使用保護層14〇而無法有效地 避免銅材質之接合墊120的表面發生氧化時，亦可在 保濩層140之後，在保護層14〇之表面更額外地覆蓋一有 1236746 12641twf.doc (Orgamc Solderability Preservatives, OSP) 或是-銲料層（圖均未示），用以更有效地將接合塾⑽ 之^面隔絕於外界之空氣，進而降低接合塾12〇之表面發 生乳化的機率，同時額外增加之輝料層亦有助於鮮料塊^ 及接合塾⑽之間的接合作業。請_參考第i圖 塊10之材質無論是含錯銲料或是無鱗料，銲料塊⑺之 it均ί包括錫。在銲料塊1G長期處於高溫及高電流密 度，情況下，銲料塊10之内部的電子 (electromigration)將趨於明顯，因而導致銲料塊10之 與接合墊120之銅結合生成介金屬化合物(1晰_ =all，mpound，IMC)於銲料塊10及接合塾120之間。 值侍注意的是，由於錫及銅之介金屬化合 弱，導致銲料塊H)及接合墊12〇之間的接合強m =且故當剪應力長期作用於銲料塊1Q及接合塾i2^地 很合易知料塊10及接合墊^ ^ 銲料塊10與接合墊W因而導致 【發明内容】 之間的電性連接不良甚至中斷。 ，：：本發明之目的就是在提供一 ;==Γ糧之接合塾，且這些接合墊具 化合物的生^速奉:ν以減緩接合塾及銲料塊之間介金屬 、此外，本發明之再一目的是提供一種接合塾， 於連接一銲料塊，並具有較高 、 塾與㈣塊之心域的'以減緩接合 1236746 12641tw f' (j〇c =本發明之上述目的，本發明又提出—種線路載 、適於連接-銲料塊，此線路載板包含—基板应至 墊’其中接合塾係配置在基板之-表面，用以 且接合墊具有多數個阻障粒子，其佈設於 接5墊之内部，用以增加接合墊之電移阻抗。 人墊的較佳實施例所述之線路载板，其中接 “子=銅’且銲料塊之組成成分包含錫，而阻 自於由絡、銘、辞、錫、把、鎮等 孟屬及其合金所組成之族群的一種材質等。 依照本發日㈣較佳纽騎叙線 一銲罩層，其覆蓋基板之表面，謂罩層具有 口以=全暴露出接合墊，或者是暴露出局部的接合塾。 :'、達本發明之上述目的，本發明提出—種接合塾， :適於配置在一線路載板之-基板的表面，用以連接一 ==其中接合塾具有多個阻障粒子，其佈設於接合 。卩用以增加接合墊之電移阻抗。 墊之的較佳實施例所述之接合塾，其中接合 料狀組錢純讀，而阻障 c糸可選自於由鉻、銘、辞、 = 屬及其合金所組成之族群的一種材質等。 力寺金 部二合墊之内 rr接，薛料“介金屬二=速 率，進而糾__銲缝與接合墊之_接合強ΐ 1236746 12641twf.doc 為讓本發明之上述和其他目的、特徵和優點能更明 顯易丨董’下文特舉較佳貫施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 請參考第2A圖，其繪示為本發明較佳實施例之一 種線路載板的剖面示意圖。線路載板2〇1包含一基板 210、多個接合墊220 (圖僅繪示其一）、一銲罩層23〇 及一保護層240，其中基板21〇係包含多數個導線層、 多數個絕緣層及多數個導電孔（圖均未示），而每一絕緣 層係配置於相鄰兩導線層之㈤，且每_導電孔係穿過絕 ，層而與至少兩導線層相互連接。此外，接合塾220 =配，於基板210之表面212上，用以連接多個銲料塊 :例如為覆晶接合用之凸塊，其中接合墊細係可 導的2二最，導線層所構成，由於基板210之 另外、料作=合塾22G之材質亦為銅。 接點，而銲料塊10乍=基板210與晶片2〇相連接之 銲罩層230係承箸^如為含鉛銲料或無錯銲料。 層23〇具有多數個^口 =板210的表面212，且銲罩 係暴露出局部的接合 （圖僅綠不其—）’開口 232 接合墊220為_銲罩t 亦就是說，在第2A圖中， 類型之接合墊22〇，苴定義曰（Solder Mask Define，SMD) 之底部的流動，以避、中銲罩層230係可限制住銲料塊10 造成相鄰兩接合墊 目鄰兩銲料塊10之間彼此連接而 之間的短路。為了防止銅材質之 9 1236746 12641twf.doc 接5赞的表面發生氧化，保護層24〇係配置於接合 墊220之暴露出的表面，其例如為一鎳/金層。值得注意 的是’當使用保護層240而無法有效地避免銅材質之接 合墊22Θ的表面發生氧化時，亦可在形成保護層24〇之 後，在保護層240之表面更額外地覆蓋一有機表面保護 層（OSP)或者是一銲料層（圖均未示），用以更有效地 將接合墊220隔絕於外界之空氣，進而降低接合墊22〇 二m氧化的機率，同時額外增加之銲料層亦有助 於知科塊10及接合墊220之間的接合作業。 :於含鉛銲料（例如錫鉛合金）具有較佳之焊接特 ，，所以銲料塊1G之材f通 鉛銲料或無鉛銲料，銲料塊仁不_疋含 因此，在r祖抬I 成成分均會包含錫。 _ ^ 、干枓鬼0長期處於高溫及高電流密产 鮮料塊10之錫朽將趨於明顯’因而導致 兄U之錫極易與接合墊22Q之人 合物於銲料塊10及接合墊220之間。、° σ成"金屬化 值得注意的是，為了減緩銅及 生成於銲料塊1〇及接合塾22 二”屬化合物層 持鮮料塊U)及接合墊細1^率’以長期地維 施例乃是藉由將多個阻障粒子222接；強度，故本較佳實 220之内部’其中置人 人或摻雜於接合塾 (plating)或驅入（drive)等方式入（卿細）、電鍍 之材質係可選自於由路、銘、^、°此外，阻障粒子222 其合金所組叙族群的_種材質，用，^等金屬及 以提高接合墊220 1236746 12641twf.doc 之電移阻抗。由於這些佈設在接合墊22〇之内部的阻障 粒子222可增加接合墊22〇之電移阻抗，當銲料塊〗〇長 期處於咼溫及高電流密度的情況時，這些摻雜有阻障粒 子222之接合墊220將可減緩錫及銅之介金屬化合物的 生成速率，故可長時間地保持銲料塊1〇與接合墊22〇之 間的接合強度。 上請同時參考第2A、2B圖，其中第2B圖繪示為本發 ，較佳實施例之另一種線路载板的剖面示意圖。相較於 第2A圖之線路载板2〇1的銲罩定義（s〇lderMaskDefine， SMD/)類型之接合墊22〇，第2B圖之銲罩層23〇的開口 232係暴露出全部的接合墊22〇，故第2B圖之接合墊 係為一非銲罩定義（N〇n-Solder Mask Define，NSMD )類 型之接合墊220。 任何熟知本發明之技藝者皆可知悉，本發明之線路 載板可以應用於晶片與封裝載板（paekage ean4e〇之間 的連接型態（例如覆晶接合型態），使得線路載板之接^ 墊可作為凸塊藝（bump pad)。此外，本發明之線路載板 亦可應用於封裝載板與電路板（circuit b〇ard)之間的連 接，例如球格陣列（Ball Grid Array，BGA)接合型態， 使得線路載板之接合墊還可作為銲球墊（baU :另 外，本發明之線路載板的接合墊更可應用來連接一般 面黏著型（SMT)之電子元件的接點（例如接腳或電極又 故本發明之線路載板亦可應用於一般之印刷電路板 I236746 12641 twf.doc 标上所述 π 4知泉路載板的接合墊其内部係佈 1夕數個阻障粒子，用以增加接合塾之電移阻抗，因 ^咸緩銲料塊與接合墊之間的介金屬化合物之生成速 可有效地減緩接合細之銅的、;肖耗，進而長時間 銲料塊與接合墊之間的接合強度。因此，當本發 路載板的接合墊以表面黏著技術（SMT)來連接 接點門點時’線路載板之接合墊及電子元件之 持較長的_。 接（特別疋電性連接）將可維 雖然本發明已以一較袢 用以限定本發明，任何孰‘此二:】路：上’ i並非 之精神和範圍内，4二: 在不脫離本發明 田了作些許之更動與潤飾，因此本發 【圖式簡附之申請專利範圍所界定者為準。 ^1會不為習知之—種線路載板的剖面示意圖。 的剖面示意圖為本發明較佳實施例之—種線路載板 板的=面示Hr為本發日她佳實施例之另—種線路載 【主要元件符號說明】 10 :銲料塊 20 ： 晶片 10():線路载板 110 ·基板 1236746 12641 twf.doe 112 :表面 120 :接合墊 130 :銲罩層 132 :開口 140 :保護層 201、202 :線路載板 210 :基板 212 ··表面 220 :接合墊 222 :阻障粒子 230 :銲罩層 232 :開口 240 :保護層I23674々64i— IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a circuit carrier board, and more particularly to a circuit carrier board. Barrier particle 'It can increase the electromigration resistance of the bonding pad 〇 [prior art] Flip chip interconnect technology is a kind of chip (die) connected to a carrier The packaging technology 'is mainly based on the arrangement of a plurality of luminous pads (pa (j) of the wafer using an area array) on the acdve surface of the wafer, and on each pad, Under-bump metallurgy (UBM) and bumps are sequentially formed, such as solder bumps, and after the wafer is flipped, these bumps are used to attach the wafer to the wafer. These pads on the active surface are electrically and structurally connected to a carrier (such as a substrate or a printed circuit board, respectively). It is worth noting that because the flip-chip bonding technology is applicable to chip packages with high pin counts, social structure, and has the advantages of reducing the package area and shortening the signal transmission path, etc. The flip-chip bonding technology has been widely used in chip packaging structures, and high-level chip packaging structures are available. Please refer to Figure 1 for a schematic diagram of a conventional circuit surface. The circuit board 100 includes A substrate 110, multiple connections 1236746 12641twf.doc (bonding pad) 120 (only one is shown in the figure), a solder mask layer 130 and a protective layer 14, wherein the substrate includes a plurality of The wire layer has an insulating layer and a plurality of conductive holes (not shown in the figure), and each insulating layer is disposed between two adjacent wire layers, and each conductive hole passes through the insulating layer and It is connected to at least two wire layers. In addition, 'these bonding pads 12 are arranged on the surface U2 of the substrate 11 ()' for connecting a plurality of solder bumps 10 '(the figure only shows them) A), such as flip-chip bonding (flipc hipbump), wherein the bonding pad 120 is composed of the outermost conductive layer of the substrate 110. In addition, since the material of the conductive layer of the substrate 110 is usually copper, the material of the bonding pad 120 is also copper. In addition, the solder bump 1 〇 is used as a connection point between the substrate 110 and the wafer 20, and the material of the solder bump 10 is, for example, an error-containing solder or an error-free raw material. Please also refer to the first item. The solder mask layer 130 covers the surface 112 of the substrate 110, and the solder mask layer 130 has a plurality of openings 132 (only one of which is shown in the figure). The openings 132 respectively expose local The bonding pads 120, in which the solder mask layer 130 can restrict the flow of the bottom of the solder bumps 10, so as to avoid the two adjacent solder bumps 10 from melting to each other during reflow (refl0w), resulting in two adjacent bonding pads 120. Short circuit. In addition, in order to prevent the surface of the bonding pad 120 made of copper from being oxidized, a protective layer 14 (such as a nickel / gold layer) is usually disposed on the partially exposed surface of the bonding pad 120. It is worth noting that when the protective layer 14 is used to effectively prevent the surface of the copper-made bonding pad 120 from oxidizing, the surface of the protective layer 14 can be additionally covered after the protective layer 140. 1236746 12641twf.doc (Orgamc Solderability Preservatives, OSP) or-solder layer (not shown in the figure) is used to more effectively isolate the surface of the bonding joint from the outside air, thereby reducing the occurrence of the surface of the bonding joint 12 The probability of emulsification, and the extra bright material layer also helps the bonding operation between the fresh material block and the bonding pad. Please refer to Figure i. The material of block 10 includes tin, whether it contains the wrong solder or non-scale materials. In the case where the solder bump 1G is at a high temperature and high current density for a long period of time, the electrons inside the solder bump 10 will tend to be obvious, thus causing the solder bump 10 to combine with the copper of the bonding pad 120 to generate a metal compound (1 clear _ = all, mpound, IMC) between the solder bump 10 and the bonding pad 120. The attendant noticed that due to the weak intermetallic combination of tin and copper, the bonding strength m between the solder bump H) and the bonding pad 120 was m =. Therefore, when the shear stress acts on the solder bump 1Q and the bonding 长期 i2 ^ ground for a long time It is easy to know that the material block 10 and the bonding pad ^ ^ The solder block 10 and the bonding pad W thus lead to a poor or even interrupted electrical connection between the invention. :: The purpose of the present invention is to provide a joint 塾 of =; Γ food, and the production of these bonding pad compounds ^ speed: ν to slow down the metal between the joint 塾 and the solder block. In addition, the present invention A further object is to provide a joint 塾, which is used to connect a solder bump and has a high, 塾 and ㈣ block heart region of 'to slow the joint 1236746 12641tw f' (j〇c = the above purpose of the present invention, the present invention also Proposed-a kind of circuit carrier, suitable for connection-soldering block, this circuit carrier board includes-the substrate should be connected to the pad, where the bonding pad is arranged on the surface of the substrate, and the bonding pad has a plurality of barrier particles, which is arranged on It is connected to the inside of 5 pads to increase the electrical resistance of the bonding pads. The circuit carrier board described in the preferred embodiment of the human pad, wherein "sub = copper" is connected and the composition of the solder block contains tin, and the resistance is A material of the group consisting of Mon, and other alloys such as Luo, Ming, Ci, tin, bar, and town, etc. According to the hairpin of this publication, a welding shield layer covering the surface of the substrate is said, The cover layer has a mouth to fully expose the bonding pad, or is exposed Partial bonding 塾: ', to achieve the above-mentioned object of the present invention, the present invention proposes a bonding:, which is suitable for being arranged on the surface of a substrate of a circuit carrier board for connecting a == wherein the bonding 塾 has multiple The barrier particles are arranged at the joint. 卩 is used to increase the electrical resistance of the bonding pad. The bonding 所述 described in the preferred embodiment of the pad, wherein the bonding material is purely read, and the barrier c 糸 can be selected from It is a material of the group consisting of chrome, inscription, word, genus and its alloys, etc. It is connected to the inner part of the Lisi Jinbu two-in-pad, and the material "Metal two = speed, and then __weld and Bonding pads_Jogging strength 1236746 12641twf.doc In order to make the above and other objects, features, and advantages of the present invention more obvious and easier, Dong's detailed examples are given below in conjunction with the accompanying drawings for detailed description. [Embodiment] Please refer to FIG. 2A, which is a schematic cross-sectional view of a circuit carrier board according to a preferred embodiment of the present invention. The circuit carrier board 201 includes a substrate 210 and a plurality of bonding pads 220 (the figure only One is shown), a solder mask layer 23 and a protective layer 240, wherein The board 210 includes a plurality of conductive layers, a plurality of insulating layers, and a plurality of conductive holes (not shown in the figure), and each insulating layer is disposed at the edge of two adjacent conductive layers, and each conductive hole passes through And at least two wire layers are connected to each other. In addition, the bonding pad 220 is matched on the surface 212 of the substrate 210 to connect a plurality of solder bumps: for example, bumps for flip-chip bonding, in which the bonding pads are thin It is a conductive 22 layer, which is composed of a wire layer. Because of the substrate 210, the material of the material = 22G is also copper. Contacts, and the solder bump 10 = the substrate 210 is connected to the wafer 20 The cover layer 230 is a bearing layer such as lead-containing solder or error-free solder. The layer 23 has a plurality of surfaces = 212 of the surface of the board 210, and the welding cover system exposes a local joint (the picture is only green but not-) ' The opening 232 bonding pad 220 is a solder mask t. That is to say, in FIG. 2A, the type of bonding pad 22, the bottom of the Solder Mask Define (SMD), flows in order to avoid or middle the solder mask layer 230. It can restrain the solder bump 10 from causing the two adjacent solder pads to be connected to each other and adjacent to each other. Short circuit. In order to prevent oxidation of the surface of the copper material 9 1236746 12641twf.doc, the protective layer 240 is disposed on the exposed surface of the bonding pad 220, which is, for example, a nickel / gold layer. It is worth noting that when the protective layer 240 cannot be used to effectively prevent the surface of the copper bonding pad 22Θ from oxidizing, an organic surface can be additionally covered on the surface of the protective layer 240 after the protective layer 240 is formed. A protective layer (OSP) or a solder layer (not shown in the figure) is used to more effectively isolate the bonding pad 220 from the outside air, thereby reducing the probability of oxidizing the bonding pad 2220 m, and adding an additional solder layer. It also helps to know the bonding operation between the section 10 and the bonding pad 220. : It has better soldering characteristics for lead-containing solder (such as tin-lead alloy), so the material of the solder block 1G is lead-free solder or lead-free solder. The solder lump does not contain any contamination. Therefore, all the components in the RZ will be Contains tin. _ ^, Dry ghosts 0 long-term high temperature and high current dense production of fresh block 10 tin will tend to be obvious', so that the brother U of the tin and the bonding pad 22Q human composition on the solder block 10 and the bonding pad Between 220. It is worth noting that, in order to slow down copper and its formation in solder bumps 10 and 22, it is a "metallic compound layer holding fresh material block U) and the bonding pads are thinned for a long time. The example is by connecting a plurality of barrier particles 222; the strength, so the inside of this preferred embodiment 220, which is placed in the person or doped in bonding or driving or other means (Qing (Fine), the material of electroplating can be selected from the road, Ming, ^, ° In addition, the barrier particles 222 and its alloy group _ kinds of materials, used, ^ and other metals and to improve the bonding pad 220 1236746 12641twf. doc's electromigration resistance. Because these barrier particles 222 arranged inside the bonding pad 22 can increase the electromigration resistance of the bonding pad 22o, when the solder bump is exposed to high temperature and high current density for a long time, these The bonding pad 220 doped with the barrier particles 222 can slow down the generation rate of the intermetallic compounds of tin and copper, so the bonding strength between the solder bump 10 and the bonding pad 22 can be maintained for a long time. Please also refer to the above Figures 2A and 2B, Figure 2B shows the present invention, a preferred embodiment Another schematic cross-sectional view of a circuit carrier board. Compared to the solder mask definition (solderMaskDefine (SMD /)) of the circuit carrier board 201 of FIG. 2A, the bonding pad 22 of the solder mask type 23 and the solder mask layer 23 of FIG. 2B The opening 232 of 〇 exposes all the bonding pads 22, so the bonding pad in FIG. 2B is a Non-Solder Mask Define (NSMD) type bonding pad 220. Anyone who is familiar with the present invention Those skilled in the art can know that the circuit carrier board of the present invention can be applied to a connection type (such as a flip-chip bonding mode) between a chip and a package carrier board (such as a flip-chip bonding mode), so that the connection pad of the circuit carrier board can be used as a bump Bump pad. In addition, the circuit carrier board of the present invention can also be applied to the connection between a package carrier board and a circuit board, such as a Ball Grid Array (BGA) junction type. So that the bonding pads of the circuit carrier board can also be used as solder ball pads (baU: In addition, the bonding pads of the circuit carrier board of the present invention can also be used to connect contacts (such as pins) of electronic components of general surface adhesion type (SMT) Or the electrodes can be applied to the circuit carrier board of the present invention. The general printed circuit board I236746 12641 twf.doc is marked with the π 4 Zhiquan Road carrier board. The interior of the bonding pad is lined with a number of barrier particles to increase the electrical resistance of the bonding pad. The generation rate of the intermetallic compound between the block and the bonding pad can effectively slow down the bonding of fine copper, and thus reduce the bonding strength between the solder block and the bonding pad for a long time. Therefore, when the The bonding pad uses surface mount technology (SMT) to connect the contact door points. The connection (especially electrical connection) will be able to maintain the invention. Although the present invention has been used to define the present invention, any one of these two: the road: on the i is not within the spirit and scope, not two: The invention has made some changes and retouching. Therefore, the scope of the patent application attached to the present document [which is attached to the figure shall prevail. ^ 1 will not be known—a cross-sectional schematic diagram of a circuit carrier board. The schematic cross-sectional view is a preferred embodiment of the present invention-a circuit carrier board = the surface shows that Hr is another preferred embodiment of the present day-a circuit carrier [Description of the main component symbols] 10: solder block 20: wafer 10 (): Circuit board 110 · Substrate 1236746 12641 twf.doe 112: Surface 120: Bonding pad 130: Solder mask layer 132: Opening 140: Protective layer 201, 202: Circuit carrier 210: Substrate 212 · Surface 220: Bonding Pad 222: Barrier particles 230: Solder mask layer 232: Opening 240: Protective layer
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