CN101552247B - 集成电路结构 - Google Patents
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Abstract
本发明涉及一种集成电路结构,包括:半导体基底、第一低介电系数材料层、第二低介电系数材料层、第一反射金属垫以及焊垫。第一低介电系数材料层位于半导体基底之上,其中第一低介电系数材料层是一种上方低介电系数材料层。低介电系数材料层直接位于第一低介电系数材料层下方。第一反射金属垫位于第二低介电系数材料层之中,且第一反射金属垫具有浮动电性。焊垫位于第一反射金属垫上方,其中焊垫以及第一反射金属垫是垂直地相互对准。
Description
技术领域
本发明是有关于一种集成电路,且特别是有关于一种在后段工艺(Back-End-of-the-Line)中经由紫外光烘烤,而具有优良机械强度的低介电系数介电材料结构。
背景技术
随着半导体工业引进具有较高效力及较强功能的新一代集成电路,当个别元件的体积、尺寸或多个元件之间的空间减少时,形成集成电路的元件密度也跟着增加。在过去,减少元件尺寸与元件间空间的技术,只受限于光刻结构的定义能力,而今具有较小尺寸的元件布局则又创造出新的限制条件。例如任两条相邻的导电线路之间,当导体的距离缩小,会造成用来区隔这两条导电线路,使其保持一定距离的低介电系数材料的电容值(Capacitance)增加。而电容值的增加,会增进导体之间造成的电容耦合,因而增加电力的消耗,并造成电阻电容(Resistive-Capacitive;RC)迟延。因此若半导体集成电路效力及功能持续发展,则需仰赖发展出较已知技术所经常使用的氧化硅材料的介电系数更低的介电材料,来降低电容量。
低介电系数材料在沉积之后,一般都需要经过一道烘烤工艺,借以增加其多孔性(Porosity),因而降低其介电系数,并增加其机械强度。典型的烘烤方法包括热烘烤、等离子烘烤以及紫外光烘烤。而这三种烘烤工艺,以等离子烘烤方法和紫外光烘烤方法耗时较短,且可在较低温度条件下进行,并且可排除已知所使用的烤炉烘烤方式,而降低总热预算(Total Thermal Budget)。
然而,多孔性薄膜通常具有机械强度不高的特性。在芯片工艺中,脆弱的薄膜,可能在用来平坦化晶片表面的化学机械研磨工艺中失效。再者,脆弱的低介电系数材料在封装工艺中也会发生工艺困难。例如,当晶片在进行裁切(Saw)时,在晶片切割道(Scribed-Line)附近的低介电系数材料可能剥落。再加上打线工艺中,施加于外接导线的力量,也会造成位于焊垫下方的低介电系数材料剥落。而上述两种状况都有可能造成集成电路失效。因此进行一个有效的烘烤工艺,借以极大化低介电系数材料的机械强度就显得相当的重要。
请参照图1,图1是根据已知技术,示出一种正在进行烘烤工艺中的集成电路结构的剖面示意图。其中包括超低介电系数层2、蚀刻终止层4以及超低介电系数层6。在超低介电系数层6沉积之后,使用紫外光,如箭头8所示,对集成电路结构进行紫外光烘烤工艺。为了有效地烘烤超低介电系数层6,也就是要让紫外光的能量,尽可能地被超低介电系数层6吸收。然而,还是有一大部分的紫外光能量穿过超低介电系数层6,到达蚀刻终止层4以及位于其下方,包含超低介电系数层2的集成电路。也就是说紫外光烘烤的效率相当的低,因此有需要提供一种有效利用紫外光能量以增加介电材料的机械强度的集成电路结构,以及其形成方法。
发明内容
本发明所要解决的技术问题在于提供一种有效利用紫外光能量以增加介电材料的机械强度的集成电路结构。
为了实现上述目的,依据本发明的一个实施例,本发明提供一种半导体集成电路结构。此半导体集成电路结构包括:半导体基底、第一低介电系数材料层、第二低介电系数材料层、第一反射金属垫及焊垫。第一低介电系数材料层位于半导体基底上。第二低介电系数材料层直接位于第一低介电系数材料层下方,因此第一介电系数材料层可以视为是一上方低介电系数材料层。第一反射金属垫位于第二低介电系数材料层之中,焊垫位于第一反射金属垫上方,且焊垫以及第一反射金属垫实质上是垂直地相互对准。
为了实现上述目的,依据本发明的另一个实施例,本发明还提供一种半导体集成电路结构。此半导体集成电路结构包括:半导体基底、焊垫、第一介电系数材料层、反射金属垫。焊垫位于半导体基底上,具有第一长度和第一宽度。第一介电系数材料层位于焊垫下方。反射金属垫位于第一低介电系数材料层下方。其中焊垫以及反射金属垫实质上是垂直地相互对准。且反射金属垫具有第二长度和第二宽度,分别大于焊垫的第一长度和第一宽度。
为了实现上述目的,依据本发明的又一个实施例,本发明又提供一种半导体集成电路结构。此半导体集成电路结构包括:第一半导体芯片、第二半导体芯片以及邻接第一半导体芯片和第二半导体芯片的切割道。此切割道包括:基底、第一低介电系数材料层、第二低介电系数材料层以及反射金属垫。第一低介电系数材料层位于基底上方。第二低介电系数材料层直接位于第一低介电系数材料层下方。反射金属垫位于第二低介电系数材料层之中。
根据以上所述的实施例,本发明的技术优势在于通过上述实施例所提供的半导体集成电路结构,在不需要增加额外的掩膜(mask)或工艺,即可使半导体集成电路的内联机结构具有较优良的机械强度。
附图说明
为让本发明的所述和其它目的、特征、优点与实施例能更明显易懂,所附附图的详细说明如下:
图1是根据已知技术,示出一种正在进行烘烤工艺中的集成电路结构的剖面示意图;
图2是根据本发明的一较佳实施例所示的一种半导体晶片结构的俯视图;
图3和图4是分别根据图2所示的集成电路的部份结构剖面图;
图5是根据图3和图4所示的半导体芯片的局部结构俯视图;
图6A和图6B是分别根据图2所示的晶片的部分结构俯视图;
图7是根据图6A或图6B所示的晶片部分结构剖面图;
图8至图10示出形成图3的集成电路结构的一系列工艺结构剖面图。
【主要元件符号说明】
2:超低介电系数层 4:蚀刻终止层
6:超低介电系数层 8:箭头
20:半导体晶片 28:第一切割道
30:第二切割道 26:半导体芯片
40:半导体基底 42:晶体管
44:插塞 46:内层介电层
48:焊垫 50:钝化层
52:低介电系数材料层
521:低介电系数材料层位于反射金属垫上方的部位
522:低介电系数材料层下方未设置有反射金属垫的部位54:金属线 56:插塞低
60:低介电系数材料层
601:低介电系数材料层位于反射金属垫上方之部位
602:低介电系数材料层下方未设置有反射金属垫的部位
62:金属垫 66:低介电系数材料层
661:低介电系数材料层位于反射金属垫上方的部位
68:金属垫 70:金属垫
74:密封环 A-A’:切线
B-B’:切线 L1:焊垫的长度
W1:焊垫的宽度 L2:金属垫的长度
W2:金属垫的宽度 M1:金属化层
TM:金属化层 TM-1:金属化层
TM-2:金属化层 TM-3:金属化层
具体实施方式
以下以较佳实施例详述如何制造并使用本发明的技术特征。然而值得注意的是,本发明是在提供许多可以在不同特定环境背景中合适地体现其发明概念的实施例。而这些特定的实施例,只是使用来说明如何制造并使用本发明的技术特征,而非用来限制本发明的权利范围。
本发明提供一种新颖的集成电路结构以及其制作方法。其中该集成电路结构包括一种可以反射紫外光的图案。在以下的实施例之中,相同的附图符号可以代表相似的元件,但并不代表每一个附图之间具有交互的关连性。
请参照图2,图2是根据本发明的一较佳实施例所示的一种半导体晶片20(semiconductor wafer)结构的俯视图。半导体晶片20包括多个由第一切割道28和第二切割道30所区隔的半导体芯片26(semiconductor chips)(一般也称作晶粒(dies))。第一切割道28沿着第一方向延伸,第二切割道30延着第二方向延伸,其中第二方向垂直第一方向。焊垫48形成在半导体芯片26的表面。
图3是根据图2所示的一部份集成电路结构的剖面示意图。其中剖面图是沿着图2的切线A-A’所绘示。图2中所示的局部的集成电路结构,则由图5放大成局部结构俯视图。其中图5示出半导体芯片26的局部结构的俯视图。
请参照图3,半导体基底40较佳由硅材料所形成,但也可以由周期表中的第三族、第四族或第五族元素,例如硅锗镓砷或上述元素的任意组合所构成。半导体基底40也可以是块体基底(Bulk Substrate)或绝缘层中有硅(Silicon-on-Insulator;SOI)基底。集成电路元件,例如晶体管、电容器、电阻或类似元件,则可形成在半导体基底40的表面上。在本实施例之中,则以晶体管42来作为集成电路元件的代表。
这些集成电路元件,则是由金属线来进行内部连接,而这些金属线可以分别形成于不同层,并通过内层介电(Inter-Layer Dielectrics;ILD)或内部金属介电材料(Inter-Metal Dielectrics;IMD)来分隔。半导体芯片26包括高达八层或更多的金属化层(Metallization Layer)。在以下的所有实施例之中所提及,并用来使接触插塞44形成于其中的介电层,都是由内层介电材料所构成的内层介电层46。至于位于内层介电层46上方的则是内部金属介电层。直接位于内层介电层46上方的金属化层,称为底部金属化层M1;而其中形成有焊垫的金属化层,称为上方金属化层TM。因此金属化层由上而下的排列顺序为TM、TM-1、TM-2、TM-3...及M1。
焊垫48位于半导体芯片26的上表面,并且通过钝化层50暴露于外。焊垫48和钝化层50的组合即是上述所称的上方金属化层TM。钝化层50较佳包含介电材料,例如掺杂的硅玻璃(Un-doped Silicate Glass;USG)、氧化硅、氮化硅或其它类似材料。较佳的材料则是,具有实质小于位于其下方的低介电系数材料层的介电系数的材料。在本发明的较佳实施例之中,钝化层50具有实质大于3的介电系数。焊垫48分别透过金属线、过孔(vias)以及重分配轨迹(Redistribution Trace)(未示)与集成电路的其它点电性连接。
金属化层TM-1形成于上方金属化层TM之下。金属化层TM-1包括一层具有低介电系数材料的低介电系数材料层52,来作为其最上层。因此低介电系数材料层52可以作为上方低介电系数材料层。低介电系数材料层52较佳具有实质小于3.9的介电系数,更佳的介电系数则是小于2.5,因此可以视为是一种超低介电系数材料层。实际上的案例中,低介电系数材料层52包括氟硅玻璃、含碳的介电材料,以及其它类似材料。且上述材料可能还包括有氮、氢、氧以及上述元素的任意组合。在图3所示的实施例之中,并未示出有任何金属特征,例如铜质金属线或金属插塞直接形成于焊垫48下方以及上方低介电系数材料层52之中。不过,金属线(未示)可能会形成在上方低介电系数材料层52之中,未直接位于焊垫48下方区域。在其它的实施例之中,如图4所示,金属线54形成在上方低介电系数材料层52之中,并经由插塞56与焊垫48连接。
另外,半导体芯片26可选择性地包含一个额外的钝化层(未示),位于钝化层50与上方低介电系数材料层52之间。而形成这一个额外钝化层的材料,本质上可以与形成钝化层50的材料相同。
请再参照图3,金属化层TM-2形成于金属化层TM-1之下。金属化层TM-2也包括一层低介电系数材料层60,且形成低介电系数材料层60的材料,本质上可以与形成低介电系数材料层52的材料相同(或是选自于形成低介电系数材料层52的各种材料)。蚀刻终止层58形成在金属化层TM-2与金属化层TM-1之间。在本发明的较佳实施之中,金属垫62形成在金属化层TM-2之中,并实质且垂直地与焊垫48重叠。在本说明书所举的实施例之中,金属垫62(以及其它相似的金属垫,例如金属垫68),都可因为其具有反射紫外光的功能而称为反射金属垫。至于反射功能将详述以下段落之中。反射金属垫62用于烘烤位于上方的低介电系数材料层52时,可有效(益)地反射紫外光,因此紫外光不会穿透而进入下方的介电材料。可增进直接位于金属垫62上方的低介电系数材料层的部位521的硬化效果。由于位于焊垫48下方低介电系数材料,在打线工艺中很容易受损,这个部分需要具备更佳的机械强度。因此如图5所示,当反射金属垫62的长度L2和宽度W2至少分别实质近似焊垫48的长度L1和宽度W1时,这一个部分的硬化会更有效率。在本发明的一些实施例之中,长度L2实质大于80%的长度L1,且/或宽度W2实质大于80%的宽度W1。在较佳的实施例中,长度L2实质大于长度L1,且宽度W2实质大于宽度W1。在更佳的实施例中,反射金属垫62不仅完全地与焊垫48垂直地重叠,且至少一个方向,较佳为全部的方向,延伸超过焊垫48的边缘(请参照图5)。
金属化层TM-2的结构可以在金属化层TM-3至M1中重复。在图3所示的实施例之中,金属化层TM-3包括一层低介电系数材料层66以及反射金属垫68。形成低介电系数材料层66以及位于其下方的低介电系数材料,本质上可以与形成低介电系数材料层52及/或60的材料相同(或是选自于形成低介电系数材料层52及/或60的各种材料)。反射金属垫68的形成,改善低介电系数材料层60位于反射金属垫68上方的部位601的烘烤效果。同理,反射金属垫62、反射金属垫68以及每一个位于下方的其它反射金属垫,其尺寸都实质近似于或大于焊垫48的尺寸,且较佳是垂直地与焊垫48对准。
在本发明的一些实施例之中,反射金属垫62、反射金属垫68以及位于下方的其它反射金属垫,较佳是彼此分离,且具有浮动电性(Electrically Floating)。在本发明的另一些实施例之中,反射金属垫62、反射金属垫68以及位于下方的其它反射金属垫,较佳是彼此内连接。请参照图4,图4中示出有用来连接反射金属垫62和反射金属垫68的过孔69。然而在这种情形下的反射金属垫,较佳仍具有浮动电性。值得注意的是,本发明实施例中的反射金属垫62和反射金属垫68,并非已知的虚拟空置图案(Dummy Pattern)。传统的虚拟空置图案,以功能而言,是用来使图案密度达到不平均的状态,一般来说尺寸较小,例如其长/宽通常小于数微米(Micrometer)。而反射金属垫62和反射金属垫68的长/宽必须实质近似于焊垫48的尺寸,通常为数十微米或数百微米,或更大的尺寸。相对的,包括有反射金属垫的区域当然比周遭区域具有较大的图案密度。
较佳的情形下,反射金属垫是实质地形成在半导体芯片26所有焊垫的下方。对于每一个半导体芯片26的焊垫来说,反射金属垫形成于所有的金属化层中。但在其它实施例之中,只有上方金属化层(例如,金属化层TM-2及或TM-3)才具有反射金属垫,而下方金属化层则不具有反射金属垫。而之所以会如此安排,一部分原因在于,上方金属化层中的低介电系数材料,较容易因为打线而受损。
图6A至图7是本发明的另一些较佳实施例,其中反射金属垫形成于切割道之中。请参照图6A是图2中晶片20的一部分结构俯视图。在本实施例的中,反射金属垫70的外形像一条金属线,且从晶片20的一端延伸至另一端。在另外一个实施例之中,请参照图6B,反射金属垫70的外形像多个线性排列的方形,形成在切割道28和30之中,而方形反射金属垫70所形成的线,也从晶片20的一端延伸至另一端。
请参照图7,图7是根据图6A所示的晶片20的部分结构剖面图,其中剖面图是沿着图6A中的切线B-B’所绘示而成。密封环74属于位于左边的半导体芯片26,密封环76属于位于右边的半导体芯片26。和图3所示的实施例相似,反射金属垫/线70较佳形成在金属化层TM-2、TM-3、……及M1之中。因此直接位于反射金属垫/线70下方的低介电系数材料部位521、601和661,可以有效的硬化,并且改善其机械强度。当晶片20被沿着切割道28和30进行裁切时,由于低介电系数材料部位521、601和661具有较佳的机械强度,因此较不易剥落。
请参照图8至图10,图8至图10是形成图3的集成电路结构的一系列工艺结构剖面图。请参照图8,集成电路结构已由下往上形成至金属化层TM-3。其中金属化层TM-3包括低介电系数材料层66以及反射金属垫68。更多的反射金属垫(未示)可选择地形成在反射金属垫68下方,并对准反射金属垫68。反射金属垫68与用来连接集成电路元件的金属线(未示)同时地形成于低介电系数材料层66之中。反射金属垫68的形成方法,包含已知的双层内联机结构工艺。
接着,请参照图9,形成蚀刻终止层58以及低介电系数材料层60,再进行低介电系数材料层60的紫外光烘烤工艺。在本实施例之中,紫外光烘烤工艺采用波长实质介于500nm至150nm之间的紫外光。由于反射金属垫68可以反射紫外光,使得紫外光的能源能被低介电系数材料层60充分吸收,因此低介电系数材料层60直接位于反射金属垫68下方的部位601可以被更有效率的烘烤,也因此更改善其机械强度。与下方未设置有反射金属垫的部位602比较,紫外光会直接穿透而进入低介电系数材料层66,因此低介电系数材料层60的部位602的机械强度小于低介电系数材料层60的部位601的机械强度。
请再参照图10,反射金属垫62形成在低介电系数材料层60之中。形成蚀刻终止层51以及低介电系数材料层52,再进行低介电系数材料层52的紫外光烘烤工艺。同样的,低介电系数材料层52直接位于反射金属垫62下方的部位521可以被更有效率的烘烤,也因此,低介电系数材料层52的部位521,比下方未设置有反射金属垫的低介电系数材料层52的部位522具有更大的机械强度。请在参照图3,再于低介电系数材料层52上方形成钝化层50及焊垫48。由于形成钝化层50及焊垫48业已为公知常识,因此不在此加以赘述。
根据以上所述的实施例,本发明的技术特征是在低介垫系数材料层下方形成反射金属垫,以改善此低介电系数材料层直接位于反射金属垫下方部位的机械强度。由于工艺中并没有增加其它额外的步骤或掩膜,因此并不会额外地增加制造成本。
虽然本发明已以一较佳实施例揭露如上,然其并非用以限定本发明,任何熟悉此技术的人员,在不脱离本发明的精神和范围内,当可作各种的更动与润饰,因此本发明的保护范围当以权利要求书所界定的范围为准。
Claims (9)
1.一种集成电路结构,其特征在于,包括:
一半导体基底;
一第一低介电系数材料层,位于该半导体基底之上,其中该第一低介电系数材料层是一上方低介电系数材料层;
一第二低介电系数材料层,直接位于该第一低介电系数材料层下方;
一第一反射金属垫,位于该第二低介电系数材料层之中,且该第一反射金属垫具有浮动电性,其中该第一反射金属垫用以反射波长介于500nm至150nm之间的紫外光;以及
一焊垫,位于该第一反射金属垫上方,其中该焊垫以及该第一反射金属垫垂直地相互对准。
2.根据权利要求1所述的集成电路结构,其特征在于,还包括:
一第一半导体芯片;
一第二半导体芯片;
一切割道邻接于该第一半导体芯片和该第二半导体芯片;以及
一第二反射金属垫,位于该切割道之中,其中该第二反射金属垫具有浮动电性。
3.根据权利要求1所述的集成电路结构,其特征在于,还包括一第三低介电系数材料层,位于该第二低介电系数材料层之下,其中该第三低介电系数材料层包括多条金属线,且该第三低介电系数材料层不包括任何与该第一反射金属垫垂直对准的反射金属垫。
4.一种集成电路结构,其特征在于,包括:
一半导体基底;
至少一焊垫位于该半导体基底之上;
一第一低介电系数材料层,位于该焊垫之下;以及
一第一反射金属垫,位于该第一低介电系数材料层之下,且该第一反射金属垫垂直地相互对准该焊垫,该第一反射金属垫具有浮动电性,其中该第一反射金属垫用以反射波长介于500nm至150nm之间的紫外光。
5.根据权利要求4所述的集成电路结构,其特征在于,该第一低介电系数材料层是一上方低介电系数材料层,该第一反射金属垫位于一第二低介电系数材料层之中,且该第二低介电系数材料层直接位于该第一低介电系数材料层下方,且该第一低介电系数材料层不包括任何反射金属垫,直接位于该焊垫下方。
6.根据权利要求5所述的集成电路结构,其特征在于,还包括:
一第三低介电系数材料层,直接位于该第二低介电系数材料层之下;以及
一第二反射金属垫,位于该第三低介电系数材料层之中,其中该第二反射金属垫垂直地对准该第一反射金属垫。
7.根据权利要求6所述的集成电路结构,其特征在于,该第一反射金属垫和第二反射金属垫电性连接,并且彼此电性浮动。
8.根据权利要求4所述的集成电路结构,其特征在于,还包括一半导体芯片,其中该半导体芯片上具有多个该焊垫,且每一所述焊垫具有至少一反射金属垫位于其下方,而每一所述至少一反射金属垫,垂直地对准位于其上方的该焊垫。
9.一种集成电路结构,其特征在于,包括:
一第一半导体芯片;
一第二半导体芯片;以及
一切割道邻接于该第一半导体芯片和该第二半导体芯片,其中该切割道包括:
一第一低介电系数材料层,位于一半导体基底之上,其中该第一低介电系数材料层是一上方低介电系数材料层;
一第二低介电系数材料层,直接位于该第一低介电系数材料层下方;以及
一反射金属垫,位于该第二低介电系数材料层之中,该反射金属垫具有浮动电性,其中该反射金属垫用以反射波长介于500nm至150nm之间的紫外光。
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US9128123B2 (en) * | 2011-06-03 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposer test structures and methods |
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US9918683B2 (en) * | 2014-07-25 | 2018-03-20 | Teledyne Dalsa, Inc. | Bonding method with curing by reflected actinic rays |
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