CN100405593C - 焊垫结构与半导体装置 - Google Patents

焊垫结构与半导体装置 Download PDF

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CN100405593C
CN100405593C CNB2006100727685A CN200610072768A CN100405593C CN 100405593 C CN100405593 C CN 100405593C CN B2006100727685 A CNB2006100727685 A CN B2006100727685A CN 200610072768 A CN200610072768 A CN 200610072768A CN 100405593 C CN100405593 C CN 100405593C
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metal
semiconductor device
welding pad
dielectric layer
pad structure
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CN1855468A (zh
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郑道
涂兆均
林明杰
毛政智
彭秀珍
周达玺
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MediaTek Inc
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Abstract

本发明公开了一种焊垫结构以及半导体装置，本发明的半导体装置，包括：一基底；一中间结构，位于该基底上；一焊垫结构，位于该中间结构上，其中该中间结构包括一第一金属层，邻近并支撑该焊垫结构，该第一金属层为一中空金属层且被该焊垫结构所覆盖，其中空部分具有介电物质；以及多个位于该焊垫结构下方的第二金属层，其中这些第二金属层之一作为一电源线。本发明改善了现有技术的缺陷，其焊垫结构可设置于电路区之中且不会对其下方的电路元件造成损害，有助于缩减半导体芯片的尺寸。

Description

焊垫结构与半导体装置
技术领域
本发明涉及半导体装置，且特别是有关于一种具有形成于电路区内的焊垫(bond pad)结构的半导体装置。
背景技术
一般而言，半导体装置的表现可通过因元件尺寸的缩减所增加的元件密度与元件封装密度而得到改善。元件密度的增加造成了半导体装置内的内连结构数量需求，其与半导体装置的封装要求息息相关。而封装设计的主要考虑因素之一在于当一或多个装置安装于封装物内后，其内半导体装置或者是封装物的输出/输入能力或存取能力。
一般的半导体装置封装物中，半导体芯片是安装或设置于封装物中，且该封装物更进一步地通过焊线(wire)或锡球(solder bump)等导电连结物而连结于一基板的内连线路。基于此目的，于半导体芯片上便形成有焊垫(bond pad)，其通常沿着芯片的周边设置且不形成于包含有有源或无源元件的区域上。图1为一示意图，显示了于一半导体芯片上的公知焊垫布局的俯视情形。
请参照图1，半导体芯片10大体区分为第一区域12与一第二区域14。于第一区域12内设置有有源以及/或无源元件(未图示)。第一区域12与第二区域14相互分隔，于第二区域内14则设置有多个焊垫16。
在此，于第一区域12未设置有焊垫16的原因之一是为了避免在形成导电连线(bonding)的工艺时的热及/或机械应力影响了形成于第一区域12内的有源或无源元件。在形成导电连结物时，于焊垫上形成焊线或凸块的导电连线，并通过导电连线连接至支撑电路板或其他的连结装置。
因此，设置于半导体芯片10内连接结构中的金属间介电层(internalmetal dielectrics)(未图式)，其通常邻近及/或位于焊垫16下方，其机械强度可能不足以抵抗导电连结物形成时的连结应力，因而可能形成毁损。因此，焊垫是沿着芯片的周围形成，以避免对于金属层间介电层下方的有源与无源元件的直接毁损。然而，由于焊垫16占据了半导体芯片10的大部分表面，上述布局设计无法有效地降低整体芯片的尺寸，如此不利于制造费用的降低。
发明内容
本发明要解决的技术问题是：提供一种焊垫结构以及应用此焊垫的半导体装置，以利于于缩减当今半导体芯片的尺寸。
本发明的技术解决方案是：一种焊垫结构，适用于电源分配，包括：一第一介电层，其内设置有一电源导线；一第二介电层，位于该第一介电层之上，其内设置有一中空金属部；以及一第三介电层位于该第二介电层上，其内设置有一焊垫，其中该焊垫覆盖该金属部分以及该电源导线，并电性连结于该金属部分与该电源导线。
本发明还提出一种半导体装置，包括：一基底；一中间结构，位于该基底上；一焊垫结构，位于该中间结构上。其中该中间结构包括一第一金属层，邻近并用以支撑该焊垫结构，该第一金属层为一中空金属层且被该焊垫结构所覆盖，其中空部分具有介电物质；以及多个位于该焊垫结构下方的第二金属层，其中这些第二金属层之一是作为一电源线之用。
依据另一实施例，本发明还提出另一种半导体装置，包括：一基底；多个第一介电层，位于该基底上，其中该些第一介电层间插(interleave)有多个第一金属层，且这些第一金属层之一是作为电源导线；一第二介电层位于该些第一介电层上，其内设置有多个导电连接物；以及一金属焊垫，位于该第二介电层上，且为该些导电连接物所支撑，其中该些导电连接物是沿着该焊垫的周边所设置。
本发明的特点和优点是：本发明的金属焊垫形成于具有下方内连接导线与元件的电路区内。因此，中间结构中的最上层金属层可提供上方金属焊垫的一机械性支撑，并可抵抗于后续连结工艺中所造成的应力。金属焊垫与金属层间的介电层形成额外的导电连接物，以加强向上的机械性支撑能力，而位于下方的中间结构中的其它金属层的其中之一可用作电源导线(power line)并可设置于金属焊垫下方，以此增进半导体装置的集成度。本发明改善了现有技术的缺陷，其焊垫结构可设置于电路区之中且不会对其下方的电路元件造成损害，有助于缩减半导体芯片的尺寸。
附图说明
图1为一俯视图，用以说明公知半导体芯片上的焊垫布局；
图2为一俯视图，用以说明依据本发明的一实施例的半导体芯片上的焊垫布局；
图3为一剖面图，用以显示沿图2中线段3-3的半导体装置的结构；
图4、图5为一系列俯视图，分别说明图3中区域230内的不同布局情形；
图6为一剖面图，用以说明依据本发明的一实施例的半导体装置，其具有用于电源分布的一焊垫结构；
图7为一剖面图，用以说明依据本发明的另一实施例的半导体装置，其具有位于内连接线结构上的焊垫结构。
相关符号说明：
10、半导体芯片；           12、第一区域；
14、第二区域；             16、焊垫；
100、半导体芯片；          102、电路区；
104、周边区；              106、焊垫；
200、基板；                202、焊垫结构；
204、中间结构；               206、元件；
208、介电层；
210a、210b、210c、210d、金属层；
212a、212b、212c、212d、介电层；
214、金属焊垫；               216、保护层；
218、连结区；                 220、222、导电连接物；
230、区域。
具体实施方式
为了让本发明的上述技术方案、特征和优点能更明显易懂，下文特举本发明的具体实施例，并配合附图，详细解说本发明的焊垫结构与半导体装置。通过下述示范实施例的解说可了解本发明有助于减少半导体芯片的整体尺寸。于部份实施例中，上述目的是通过在具有下方电子装置以及内连导线的电路区的上方形成焊垫所达成。
本发明的实施例将配合图2至图7作一详细叙述如下。首先如图2图所示，显示了依据本发明一实施例的半导体芯片100的俯视情形。半导体芯片100上形成有被周边区104所环绕的电路区102，周边区104可作为保护环(seal ring)之用，周边区104可在芯片分割时防止电路区102免于受到损害。如图2所示，此时焊垫106形成于电路区102的周边与中心处，而半导体芯片100上的焊垫布局并不以图2的情形为限，熟悉此技艺者可依实际线路布局而进一步更改。
图3则显示了图2中线段3-3的剖面情形，以说明具有形成于基板200上的焊垫结构202的半导体装置。请参照图3，在基底200上设置有元件206。元件206例如为金属氧化物半导体(MOS)晶体管的有源元件或为如电容、电感或电阻的无源元件。这些元件206并非限定于形成在基底200上，元件206亦可形成基底200内，以进一步缩小芯片尺寸。元件206可通过公知元件制作方法所形成，在此不限定其形成方法。
介电层208覆盖于上述元件206之上与之间区域，而于介电层208之上则有中间结构204。在此，中间结构204包括介电层212a、212b、212c、212d及分别形成于该介电层之内的多个金属层210a、210b、210c、210d，以作为电性连结下方的元件206以及上方的焊垫结构202的一连接结构。在某些情形中，电性耦接于上方的焊垫结构202的中间结构204可电性连结于位于半导体芯片中任何区域的电子元件，其电性连结可通过在介电层208内相对于元件206的一位置形成导电接触物(contact)(未显示)所达成。
金属层210a、210b、210c、210d可大体沿着图2中的x方向与y方向设置并经由形成于介电层212a、212b、212c、212d内适当位置的导电接触物形成电性连结。金属层210a、210b、210c、210d可单独地或混合地作为绕线、信号线或电源导线等。中间结构204的制作则可通过如单/双镶嵌工艺或其他导线制作方法的内连工艺所达成。金属层210a、210b、210c、210d的材料可包括如铜、铝或上述材料的合金。介电层212a、212b、212c、212d则包括如经掺杂或未经掺杂的氧化物，或为当今商业应用的低介电常数介电材料，其可通过如等离子体增强型化学气相沉积(PECVD)的方法所形成。
请参照图3，中间结构204的最上层的介电层212d上形成有焊垫结构202，其包括被保护层216所部份覆盖之一金属焊垫214，并露出用于后续导电连线(bonding)用的一连结区218。金属焊垫214与保护层216可通过公知的焊垫制造技术形成，在此并不限定其形成方法。金属焊垫214则例如为包括铝、铜或其合金材料的焊垫。保护层216的材料可包括氮化硅或氧化硅，且较佳地为氮化硅。
如图3所示，金属焊垫214形成于具有下方内连接导线(即金属层210a、210b、210c、210d)与元件206的电路区内。因此，中间结构204中的最上层金属层210d可为与下方金属层210a、210b、210c相绝缘的一金属形式(pattern)。金属层210d可提供上方金属焊垫214的一机械性支撑，并可抵抗于后续连结工艺中所造成的应力。基于上述目的，于金属焊垫214与金属层210d间的介电层212d内便需要形成额外的导电连接物220，以加强向上的机械性支撑能力。在一实施例中，金属层210d为一中空金属结构，而其中空部分仍为介电层212d结构(或具有其它介电物质)。
图4至图5为一系列示意图，分别说明图3内区域230的俯视情形。如图4所示，导电连接物220是以环绕金属焊垫214的周边的多个导电插拴(via)型态设置。图4中所示的这些导电连接物220是大体以一定的顺序排列，例如为沿着金属焊垫214的周围两两排列设置的型态，且其间为介电层212d(未图式)所电性绝缘。而位于下方的中间结构204中的金属层210a、210b、210c，在此以金属层210c为例，可更设置于金属焊垫214的下方，可作为一电源导线(power line)，以此更增进半导体装置的集成度。请参照图5，在此导电插拴220则于介电层212d中形成两独立的连续导电沟槽。上述导电沟槽环绕金属焊垫的周围，而位于下方的中间结构204中的金属层210a、210b、210c的其中之一，例如金属层210c，可用作电源导线(power line)并可设置于金属焊垫214的下方，以此增进半导体装置的集成度。
图6显示了另一具有焊垫结构的半导体装置的俯视情形，其中相似标号显示了相同的构件。于本实施例中，焊垫结构202是作为电源分布用的一焊垫。如图6所示，形成于最上层介电层212d上的焊垫结构202包括被保护层216所部份覆盖的一金属焊垫214，其露出有一连结区218，以用于后续作导电连线(bonding)之用。金属焊垫214与保护层216可通过公知的焊垫制造技术形成，在此并不限定其形成方法。金属焊垫214则例如为包括铝、铜或其合金材料的焊垫。保护层216的材料可包括氮化硅或氧化硅，且较佳地为氮化硅。
如图6所示，金属焊垫214形成于电路区内，其下方具有内连接导线(即金属层210a、210b、210c、210d)与元件206。因此，中间结构204中的最上层金属层210d不仅提供上方金属焊垫214的一机械性支撑并抵抗于后续连结工艺中所造成的应力，而且电性连结于下方介电层212c内的金属层210c。此时，于金属焊垫214与金属层210d间的介电层212d及金属层210d与210c间的介电层212c内便需要形成额外的导电连接物220、222，以加强向上的机械性支撑能力。如此，电源(来图式)可直接通过后续形成于连结区218内的一导电连线(bonding)并经过中间结构204而输入至下方元件206处。在此，金属焊垫214便作为电源分配之用，因而可称之为一电源焊垫(power pad)。
接着，图7显示了另一半导体装置的实施例的剖面情形，一焊垫结构仅位于内连接线路(interconnect lines)之上，其中相似标号代表相同的构件。而于本实施中，焊垫结构亦图式为用于电源分配的一焊垫。
请参照图7，连结区218仅位于下方中间结构204之上，其下方并无元件206的设置。元件206主要形成于连结区218之外的一区域内，并分别通过一导电接触物(contact)230与导电插拴(via)220、222、224、226而电性连结于中间结构204与焊垫结构202。
上述焊垫结构202、中间结构204以及元件206间的连接情形并非以图3、图6、图7的实施情形而加以限制。熟悉此技艺者当能理解而可依实际情形而进一步更改其内连结构的设置情形。
虽然本发明已以具体实施例揭示，但其并非用以限定本发明，任何本领域的技术人员，在不脱离本发明的构思和范围的前提下所作出的等同组件的置换，或依本发明专利保护范围所作的等同变化与修饰，皆应仍属本专利涵盖的范畴。

Claims (24)

1.一种半导体装置，其特征在于，包括：
一基底；
一中间结构，位于该基底上；
一焊垫结构，位于该中间结构上；
其中该中间结构包括：
一第一金属层，邻近并用以支撑该焊垫结构，该第一金属层为一中空金属层且被该焊垫结构所覆盖，其中空部分具有介电物质；以及
多个第二金属层，位于该焊垫结构下方，其中这些第二金属层之一是作为一电源线。
2.如权利要求1所述的半导体装置，其特征在于，该第二金属层电性绝缘于该第一金属层。
3.如权利要求1所述的半导体装置，其特征在于，更包括多个导电连接物，以电性连接该第一金属层与该焊垫结构。
4.如权利要求1所述的半导体装置，其特征在于，该第一金属层形成于一氧化物层内。
5.如权利要求1所述的半导体装置，其特征在于，更包括至少一元件，位于该基底之上，其中该元件位于该焊垫结构的下方。
6.如权利要求5所述的半导体装置，其特征在于，该元件为一晶体管、电容、电感与电阻的其中之一。
7.如权利要求1所述的半导体装置，其特征在于，该第一金属层包括铝、铜与其合金的其中之一。
8.如权利要求1所述的半导体装置，其特征在于，该第二金属层包括铝、铜与其合金的其中之一。
9.如权利要求1所述的半导体装置，其特征在于，该焊垫结构包括铝、铜与其合金的其中之一。
10.如权利要求3所述的半导体装置，其特征在于，所述导电连接物连续设置，以形成一环绕该焊垫结构的沟槽。
11.如权利要求3所述的半导体装置，其特征在于，所述导电连接物为环绕该焊垫结构且彼此电性绝缘的导孔。
12.一种焊垫结构，适用于电源分布，其特征在于，包括：
一第一介电层，其内设置有一电源导线；
一第二介电层，位于该第一介电层之上，其内设置有一金属部分，该金属部分为一中空金属层；以及
一第三介电层位于该第二介电层上，其内设置有一焊垫，其中该焊垫覆盖该金属部分以及该电源导线，并电性连结于该金属部分与该电源导线。
13.如权利要求12所述的焊垫结构，其特征在于，该焊垫、该金属部分与该电源导线是通过多个导电连接物所电性连结，这些导电连接物形成于该第一与该第二介电层内。
14.如权利要求12所述的焊垫结构，其特征在于，该电源导线位于该焊垫的下方。
15.如权利要求12所述的焊垫结构，其特征在于，该第三介电层包括氮化硅。
16.如权利要求12所述的焊垫结构，其特征在于，该第二介电层包括氧化物。
17.如权利要求12所述的焊垫结构，其特征在于，该中空金属部分包含铝、铜与其合金的其中之一。
18.如权利要求12所述的焊垫结构，其特征在于，该焊垫包含铝、铜与其合金的其中之一。
19.一种半导体装置，其特征在于，包括：
一基底；
多个第一介电层，位于该基底上，其中这些第一介电层间设有多个第一金属层，且这些第一金属层之一是作为电源导线；
一第二介电层，位于前述多个第一介电层上，其内设置有多个导电连接物；以及
一金属焊垫，位于该第二介电层上，且为所述导电连接物所支撑，其中所述导电连接物沿着该焊垫的周边设置。
20.如权利要求19所述的半导体装置，其特征在于，所述导电连接物互为电性绝缘。
21.如权利要求19所述的半导体装置，其特征在于，所述导电连接物形成于该第二介电层内，且沿着该金属焊垫的周边形成一连续沟槽。
22.如权利要求19所述的半导体装置，其特征在于，更包括至少一元件位于该基底内，其中该焊垫位于该元件的上方。
23.如权利要求22所述的半导体装置，其特征在于，所述第一金属层电性连结于该元件与该焊垫。
24.如权利要求22所述的半导体装置，其特征在于，该元件为一晶体管、电容、电感与电阻的其中之一。
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