CN102931155A - 凸块接垫结构 - Google Patents

凸块接垫结构 Download PDF

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CN102931155A
CN102931155A CN2012101648243A CN201210164824A CN102931155A CN 102931155 A CN102931155 A CN 102931155A CN 2012101648243 A CN2012101648243 A CN 2012101648243A CN 201210164824 A CN201210164824 A CN 201210164824A CN 102931155 A CN102931155 A CN 102931155A
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bonding pad
pad structure
connection pads
conductive layer
projection
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CN102931155B (zh
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杨明宗
黄裕华
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MediaTek Inc
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Abstract

本发明公开一种凸块接垫结构。凸块接垫结构包括：绝缘层；导电接垫，设置于所述绝缘层上；环形导电层，埋设于所述绝缘层内且大体上沿着所述导电接垫的边缘下方；以及至少一第一导电介层插塞，埋设于所述绝缘层内且位于所述导电接垫与所述环形导电层之间，使所述导电接垫电性连接至所述环形导电层。本发明所公开的凸块接垫结构，通过环形导电层设置于绝缘层内且大体上沿着导电接垫的边缘下方，以及第一导电介层插塞的设置，可以减轻或排除白凸块的问题。

Description

凸块接垫结构
技术领域
本发明有关于一种半导体封装技术，特别是有关于一种用于电子装置的互连(interconnection)的凸块接垫（bump pad）结构。
背景技术
在微电子工业中，集成电路（integrated circuit,IC）的制造通常包括IC的制作与封装。IC芯片（dies/chips）需经过封装并通过凸块/接合接垫(bump/bond pads)而电性连接至外部电路，例如封装基板、印刷电路板（printed circuit board,PCB）或其他芯片。为了将芯片连接至外部电路，通常会使用接线和/或导电凸块。举例来说，将导电凸块形成于芯片的对应的凸块/接合接垫上，接着将芯片翻转，以将导电凸块连接至形成于外部电路上所对应的接触接点（contact）上。
近来，由于制造成本持续增加以及加上环境因素，越来越多使用无铅焊料来作为导电凸块。然而，上述的无铅焊料会因为无铅焊料的迁移而造成白凸块（white bump）的现象。「白凸块」表示在封装中，因为连接芯片时垂直应力的转移或是因为连接芯片之后进行其他热工序步骤而造成芯片破裂的问题。由于坚硬的无铅凸块，使白凸块的问题在无铅覆晶接合（Controlled Collapse ChipConnection,C4）技术中特别的严重。
图1为用于芯片的现有技术的凸块接垫结构100的剖面示意图。凸块接垫结构100包括绝缘层101，例如低介电材料（low-k material）层，其具有多层互连结构，包括彼此分隔开的金属层102、104、106及108。再者，金属介层插塞（via plug）(例如，金属介层插塞103、107)设置于金属层102、104、106及108之间，且与其电性连接。多层互连结构通常连接至芯片中的电子装置（未绘出）。凸块接垫112直接形成于多层互连结构的最上层金属层108上，且其局部为钝化保护层110所覆盖。凸块下方金属（underbump metallurgic,UBM）层114形成于凸块接垫112上，且露出于钝化保护层110，用以放置无铅焊料凸块（未绘出）。
在上述的凸块接垫结构100中，凸块接垫112通常使用较大的介层窗（via）112a来连接多层互连结构，因而产生较大的垂直应力。为了防止绝缘层101因施加的应力而受到损害，通常会使用至少二层较厚的金属层106及108。若仅使用一层较厚的金属层，较大的垂直应力会引发如上所述的「白凸块」的问题，因而降低装置的可靠度。然而，使用二层较厚的金属层则会增加制造成本。因此，有必要寻求一种新的凸块接垫结构，其能够改善上述的问题。
发明内容
由此，本发明的目的在于提供改良式的凸块接垫结构，以改善上述白凸块的问题。
一种凸块接垫结构的范例实施方式，包括：绝缘层；导电接垫，设置于绝缘层上；环形导电层，埋设于绝缘层内且大体上沿着导电接垫的边缘下方；以及至少一第一导电介层插塞，埋设于绝缘层内且位于导电接垫与环形导电层之间，使导电接垫电性连接至环形导电层。
一种凸块接垫结构的另一范例实施方式，包括：绝缘层；导电接垫，设置于绝缘层上；至少一导电区段，埋设于绝缘层内且大体上沿着导电接垫的边缘下方；以及至少一第一导电介层插塞，埋设于绝缘层内且位于导电接垫与导电区段之间，使导电接垫电性连接至导电区段。
本发明所公开的凸块接垫结构，通过环形导电层/导电区段设置于绝缘层内且大体上沿着导电接垫的边缘下方，以及第一导电介层插塞的设置，可以减轻或排除白凸块的问题。
对于已经阅读后续由各附图及内容所显示的较佳实施方式的本领域的技术人员来说，本发明的各目的是明显的。
附图说明
图1为用于芯片的现有技术的凸块接垫结构的剖面示意图；
图2A为根据本发明一实施例的具有环形导电层的凸块接垫结构的剖面示意图；
图2B为图2A中环形导电层的平面示意图；
图3A为根据本发明另一实施例的具有环形导电层的凸块接垫结构的剖面示意图；
图3B为图3A中环形导电层的平面示意图；
图4A为根据本发明一实施例的具有导电区段的凸块接垫结构的剖面示意图；
图4B为图4A中导电区段的平面示意图。
具体实施方式
以下说明包含了本发明实施例的制作与目的。然而，可轻易了解以下说明在于阐明本发明实施例的制作与使用，并非用于限定本发明的范围。在图示及说明书中，相同或相似的部件使用相同或相似的标号。再者，为了图示的简化与便利性，图示中部件的外形及厚度得以放大。另外，未绘出或未揭露于图示及说明书中的部件为现有技术中惯用的部件。
如图2A及图2B所示，图2A为根据本发明一实施例的具有环形导电层的凸块接垫结构的剖面示意图，图2B为图2A中环形导电层的平面示意图。凸块接垫结构200可使用于芯片或封装基底等等。如图2A所示，凸块接垫结构200包括绝缘层201。在一实施例中，绝缘层201形成于半导体基底（未绘出）上。半导体基底可包括硅基底或其他半导体材料基底。半导体基底可包含各种元件，例如可包括晶体管、电阻及其他熟知的半导体元件。绝缘层201可作为内层介电层（interlayer dielectric，ILD）或是金属层间介电层（inter-metal dielectric，IMD），且绝缘层201可包括氧化物、氮化物、氮氧化物或其组合，或低介电材料（low-k material），例如氟硅玻璃（fluorinated silicate glass，FSG）、掺杂碳的氧化物（carbon doped oxide）、甲基硅酸盐类（methyl silsequioxane，MSQ）、含氢硅酸盐类（hydrogen silsequioxane，HSQ）、或氟四乙基硅酸盐（fluorinetetra-ethyl-orthosilicate，FTEOS）等。绝缘层201可通过化学气相沉积（chemicalvapor deposition，CVD）、低压化学气相沉积（low pressure CVD，LPCVD）、电浆增强化学气相沉积（plasma enhanced CVD，PECVD）、高密度电浆化学气相沉积（high density plasma CVD，HDPCVD）、或其他现有的沉积技术来形成。
多层互连结构埋设于绝缘层201内，且电性连接至形成于半导体基底内或半导体基底上的的元件（未绘出）。多层互连结构可通过现有的镶嵌工序而形成，且其包括多个导电层202，位于绝缘层201内不同的层位，使内部的导电层202能够彼此分隔开来。再者，多层互连结构也包括多个导电介层插塞203，设置于绝缘层201内位于不同层位的导电层202之间，且电性连接至这些导电层202。
作为凸块/接合接垫的导电接垫212设置于绝缘层201上。导电接垫212可包括铝、铜、其合金或其他适当的现有的金属材料。
钝化保护层210形成于绝缘层201上，且覆盖导电接垫212。钝化保护层210可包括有机材料（例如，阻焊漆（solder mask））或无机材料（例如，氧化硅或氮化硅），且可通过沉积工序而形成。钝化保护层210内形成一个开口，以露出导电接垫212的上表面而作为后续凸块工序的接触窗口。
凸块下方金属（UBM）层214形成于自钝化保护层210露出的导电接垫212上，用以放置无铅焊料凸块（未绘出）。通常凸块下方金属层214为多层结构，且可包括粘着层（例如，钛钨(TiW)），接着为扩散阻障层（例如，镍、镍钒或铬铜(Ni、NiV or CrCu)）以及焊料润湿层（例如，铜）。
在本实施例中，特别的是环形导电层206（其厚度大于多层互连结构中每一导电层202的厚度）埋设于绝缘层201内，且其位于高于多层互连结构的层位，以降低导电接垫212施加至多层互连结构的巨大垂直应力。
环形导电层206可包括铜，且可通过现有的镶嵌工序而形成。再者，环形导电层206大体上设置于导电接垫212的下方并沿着导电接垫212的边缘，且通过导电介层插塞205（其埋设于环形导电层206与多层互连结构之间的绝缘层201内）而电性连接至多层互连结构，使来自导电接垫212的垂直应力可由环形导电层206以及位于导电接垫212与多层互连结构之间的绝缘层201来共同分担。也就是说，位于导电接垫212与多层互连结构之间的绝缘层201部分可作为应力缓冲层，用以降低施加于多层互连结构的应力。
在一实施例中，如图2B所示，环形导电层206的俯视形状为八边形。在另一实施例中，环形导电层206的俯视形状可为圆形、矩形、六边形或其他形状。
至少一导电介层插塞208埋设于导电接垫212与环形导电层206之间的绝缘层201内，使导电接垫212电性连接至环形导电层206。在本实施例中，多个导电介层插塞208埋设于绝缘层201内，且对应排列于八边形的环形导电层206的边缘。再者，每一导电介层插塞208在俯视图中的形状可为矩形、方形或其他形状。
由于所施加的应力是从导电接垫212经过每一导电介层插塞208与环形导电层206至多层互连结构，且导电介层插塞208的面积小于图1中所示的介层窗112a的面积，因此可施加相对较小的应力至多层互连结构。再者由于自导电接垫212施加的应力集中于导电接垫212的中心附近，环形导电层206放置于导电接垫212的边缘下方，也会使得施加到多层互连结构的应力较小。因此，因多层互连结构上的应力转移而造成绝缘层201损坏的问题得以减轻或排除。另外，相较于现有技术中使用二层厚的金属层来防止白凸块问题来说，根据上述实施例的具有环形导电层的凸块接垫结构可进一步降低制造成本而增加产品的竞争力。
如图3A及图3B所示，图3A为根据本发明一实施例的具有环形导电层的凸块接垫结构的剖面示意图，图3B为图3A中环形导电层的平面示意图，其中相同于图2A及图2B的部件使用相同的标号并省略其说明。在本实施例中，除了浮置（floating）导电层207埋设于导电接垫212正下方的绝缘层201内且被环形导电层206所围绕之外，图3A及图3B中的凸块接垫结构200的结构相同于图2A及图2B所示的实施例。
「浮置」表示导电层207与导电接垫212以及形成于半导体基底内及其上的任何元件（如以上所述）电性隔离。在本实施例中，浮置导电层207与环形导电层206位于相同的层位。在一实施例中，浮置导电层207与环形导电层206可同时通过现有的镶嵌工序而形成，因此浮置导电层207与环形导电层206可包括相同的材料。另外，浮置导电层207也可在形成环形导电层206之前或之后才形成，其可包括与环形导电层206的材料相同或不同的材料。
上述额外的浮置导电层207可进一步加强凸块接垫结构200中对导电接垫212的支撑性。再者，由于导电层207为浮置的，因此浮置导电层207不会引起寄生电容(parasitic capacitance)。另外，本实施例的凸块接垫结构200同样可获得图2A中的凸块接垫结构200所能获得的优点。
如图4A及图4B所示，图4A为根据本发明一实施例的具有导电区段的凸块接垫结构的剖面示意图，图4B为图4A中导电区段的平面示意图，其中相同于图2A及图2B的部件使用相同的标号并省略其说明。在本实施例中，凸块接垫结构200相似于图2A中所示的凸块接垫结构，而不同之处在于以至少一导电区段206a（其大体上位于导电接垫212边缘的下方）取代图2A中的环形导电层206，且使至少一导电介层插塞208埋设于导电接垫212与导电区段206a之间的绝缘层201内，用以作为导电接垫212与导电区段206a之间的电性连接。
在本实施例中，由于导电区段206a所占据的面积小于图2A中环形导电层206所占据的面积，因此所省下的面积可供接线布线用，以增加接线布线的设计弹性。同样地，本实施例的凸块接垫结构200同样可获得图2A中的凸块接垫结构200所能获得的优点。
在另一实施例中，如图4B所示，凸块接垫结构200可包括多个导电区段206a及与其对应的多个导电介层插塞208。举例来说，上述导电区段206a排列成环且大体上位于导电接垫212的边缘下方。同样地，本实施例的凸块接垫结构200同样可获得图2A中的凸块接垫结构200所能获得的优点。需注意的是虽然本实施例中不连续环的俯视形状为八边形，然而在一些实施例中，其也可为矩形、六边形或者其他形状。
在另一实施例中，如图4B所示，凸块接垫结构200还包括浮置导电层207埋设于导电接垫212正下方的绝缘层201内，且被上述导电区段206a所围绕。因此，本实施例的凸块接垫结构200同样可获得图3A中凸块接垫结构200所能获得的优点。
以上所述仅为本发明的较佳实施方式，凡依本发明权利要求所做的均等变化和修饰，均应属本发明的涵盖范围。

Claims (19)

1.一种凸块接垫结构，其特征在于，包括：
绝缘层；
导电接垫，设置于所述绝缘层上；
环形导电层，埋设于所述绝缘层内且大体上沿着所述导电接垫的边缘下方；以及
至少一第一导电介层插塞，埋设于所述绝缘层内且位于所述导电接垫与所述环形导电层之间，使所述导电接垫电性连接至所述环形导电层。
2.如权利要求1所述的凸块接垫结构，其特征在于，还包括浮置导电层，埋设于所述导电接垫正下方的所述绝缘层内且被所述环形导电层所围绕。
3.如权利要求1所述的凸块接垫结构，其特征在于，还包括多层互连结构，埋设于所述环形导电层下方的所述绝缘层内且电性连接至所述环形导电层，所述多层互连结构包括：
彼此分隔开的多个导电层；以及
多个第二导电介层插塞，设置于所述多个导电层之间且电性连接至所述多个导电层。
4.如权利要求1所述的凸块接垫结构，其特征在于，还包括凸块下方金属层，设置于所述导电接垫上。
5.如权利要求1所述的凸块接垫结构，其特征在于，所述导电接垫包括铝。
6.如权利要求1所述的凸块接垫结构，其特征在于，所述环形导电层包括铜。
7.如权利要求1所述的凸块接垫结构，其特征在于，所述环形导电层的俯视形状为圆形、矩形、六边形、或八边形。
8.如权利要求1所述的凸块接垫结构，其特征在于，所述第一导电介层插塞与所述导电接垫包括相同的材料。
9.如权利要求1所述的凸块接垫结构，其特征在于，所述第一导电介层插塞的俯视形状为矩形或方形。
10.一种凸块接垫结构，其特征在于，包括：
绝缘层；
导电接垫，设置于所述绝缘层上；
至少一导电区段，埋设于所述绝缘层内且大体上沿着所述导电接垫的边缘下方；以及
至少一第一导电介层插塞，埋设于所述绝缘层内且位于所述导电接垫与所述导电区段之间，使所述导电接垫电性连接至所述导电区段。
11.如权利要求10所述的凸块接垫结构，其特征在于，所述凸块接垫结构包括多个导电区段以及与其对应的多个第一导电介层插塞，且其中所述多个导电区段排列成一个环，且大体上沿着所述导电接垫的边缘下方。
12.如权利要求11所述的凸块接垫结构，其特征在于，还包括浮置导电层，埋设于所述导电接垫正下方的所述绝缘层内且被所述多个导电区段所围绕。
13.如权利要求11所述的凸块接垫结构，其特征在于，所述环的俯视形状为圆形、矩形、六边形、或八边形。
14.如权利要求10所述的凸块接垫结构，其特征在于，还包括多层互连结构，埋设于所述导电区段下方的所述绝缘层内且电性连接至所述导电区段，所述多层互连结构包括：
彼此分隔开的多个导电层；以及
多个第二导电介层插塞，设置于所述多个导电层之间且电性连接至所述多个导电层。
15.如权利要求10所述的凸块接垫结构，其特征在于，还包括凸块下方金属层，设置于所述导电接垫上。
16.如权利要求10所述的凸块接垫结构，其特征在于，所述导电接垫包括铝。
17.如权利要求10所述的凸块接垫结构，其特征在于，所述导电区段包括铜。
18.如权利要求10所述的凸块接垫结构，其特征在于，所述第一导电介层插塞与所述导电接垫包括相同的材料。
19.如权利要求10所述的凸块接垫结构，其特征在于，所述第一导电介层插塞的俯视形状为矩形或方形。
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