JP4759229B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4759229B2 JP4759229B2 JP2004141835A JP2004141835A JP4759229B2 JP 4759229 B2 JP4759229 B2 JP 4759229B2 JP 2004141835 A JP2004141835 A JP 2004141835A JP 2004141835 A JP2004141835 A JP 2004141835A JP 4759229 B2 JP4759229 B2 JP 4759229B2
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- 239000004065 semiconductor Substances 0.000 title claims description 56
- 239000002184 metal Substances 0.000 claims description 90
- 229910052751 metal Inorganic materials 0.000 claims description 90
- 230000002093 peripheral effect Effects 0.000 claims description 49
- 239000011810 insulating material Substances 0.000 claims description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000005368 silicate glass Substances 0.000 claims description 4
- 150000004760 silicates Chemical class 0.000 claims description 4
- 239000010408 film Substances 0.000 description 49
- 239000000463 material Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 14
- 239000000523 sample Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- 239000010949 copper Substances 0.000 description 9
- 230000007547 defect Effects 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 206010040844 Skin exfoliation Diseases 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 125000000962 organic group Chemical group 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Description
図12は、この方法に基づき本発明者が検討した構造を表す断面図である。
フロント・エンド層1201には、半導体基板に拡散層やゲート電極、トランジスタなどが適宜形成されている。このフロント・エンド層1201の上に、コンタクトプラグ層1202を挟んで、順次、同一層内を接続するために設けられた配線1203を含む配線層1204、1205、1206、1207が形成され、最上部に密着・バリア用金属とパッド接続用Al1208とパシベーション層1209が配置されている。そして、異なる配線層間を接続するために、各配線層の上下にビア層1210、1211、1212が設けられ、各配線を電気的に接続するためにビア1213が形成されている。配線層1204から上の絶縁膜1214や1215の材料として、比誘電率が3以下の低誘電率膜を使用し、配線やビアは銅を主成分とする金属を用いて作成することができる。
一般的な設計基準では、図13に表したように、配線層中の金属部分1301は幅広の配線を組み合わせたものであり、ビア層中の金属部分1302は、支柱状のビアを敷き詰めることにより、パッド下の強度を増大させている。
図14は、電極パッドの下の部分の機械的な強度を改良する構造の他の具体例を表す断面図である。この具体例の場合、電極パッド部1216の下の全面に金属膜1401が埋め込まれている。
半導体層と、
前記半導体層の上に設けられたコンタクトプラグ層と、
前記コンタクトプラグ層の上に設けられた積層体と、
前記積層体の上に設けられた電極パッドと、
を備え、
前記積層体は、前記電極パッドの下に位置するパッド下領域と、前記パッド下領域の外側に位置するパッド外領域と、を有し、
前記積層体は、配線が形成された複数の配線層と、前記複数の配線層間を電気的に接続するビアが形成された複数のビア層とを有し、
前記複数の配線層と前記複数のビア層の各々には、前記パッド下領域の周縁に沿って、閉じた構造のパッド周縁金属配線が形成され、
各々の前記パッド周縁金属配線は、その内側に配置される絶縁材料からなる部分を取り囲むことを特徴とする半導体装置が提供される。
図1は、本発明の実施の形態にかかる半導体装置を表す断面図である。
すなわち、この半導体装置は、半導体基板に拡散層やゲート電極、トランジスタなどが形成されているフロント・エンド層101を備える。そして、フロント・エンド層101の上に、コンタクトプラグ層102を挟んで、順次、同一層内を接続するために設けられた配線103を含む配線層104、105、106、107が形成され、最上部に密着・バリア用金属とパッド接続用アルミニウム(Al)108とパシベーション層109が配置されている。パッド接続用アルミニウム108の下を「パッド下領域」と称し、それ以外の領域を「パッド外領域」と称することとする。
なお、実際の半導体装置においては、所定の数だけ配線層とビア層が繰り返し積み上げられて多層配線が形成されるが、図1においては簡単のために省略した。
図3は、図2から配線層104、105の部分のみを抜き出した平面図である。これら図面に表した一点鎖線の切断線における断面構造を図1に表した。
図4は、図2からビア層110のみを抜き出した平面図である。同図に表した一点鎖線の切断線における断面構造を図1に表した。
ビア層110中の金属部分は符号202及び203により表した部分である。金属部分202は、ビア層110の中で支柱のような形の通常のビアである。これに対して、金属部分203は、ループ状に閉じた配線を形成し、パッド下領域に存在する低誘電率の絶縁材料115を囲む構造になっている。つまり、図2〜4に表したように、パッド下領域の各層の絶縁材料114と115は、必ずループ状に閉じた構造の同層の金属配線201や203に囲まれて配置されている。
図5は、この測定結果を表すグラフ図である。
すなわち、ここでは、本実施形態を適用した「くし型容量パターン」と、図13に表した構造を有する比較例の「くし型パターン」のそれぞれについて、I−V測定を実施した。これらサンプルのパターン形状自体は同一とした。これらのサンプルは、まず、プローブをあてブレークダウンしないように0〜3ボルトの電圧範囲で3回のI−V測定を繰り返し、その後3日間が経過した後に、0〜40ボルトの範囲でI−V測定を実施した。図5の実線は本発明を適用した「くし型パターン」のI−V特性を表し、破線は比較例の「くし型パターン」のI−V特性を表す。
次に、本発明の第2の実施の形態について説明する。
配線層104、105、106、107には、それぞれ配線1101が設けられている。また、ビア層110、111、112には、それぞれ配線層1102が設けられている。なお、配線層104、105、106、107のそれぞれには、低誘電率材料からなる絶縁膜114が設けられている。また、ビア層110、111、112のそれぞれにも、低誘電率の材料からなる絶縁膜115が設けられている。
102 コンタクトプラグ層
103 同一層内を接続するための配線
104、105、106、107 配線層
108 密着・バリア用金属とパッド接続用Al
109 パシベーション層
110、111、112 ビア層
113 ビア
114 配線層中の低誘電率の絶縁膜
115 ビア層中の低誘電率の絶縁膜
116 パッド下領域
201 配線層中の金属部分
202、203 ビア層中の金属部分
203a パッド周縁金属配線
1001 チップ内部
1002 チップ周縁金属配線
1101 配線層の配線
1102 ビア層の配線
1201 フロント・エンド層
1202 コンタクトプラグ層
1203 同一層内を接続するための配線
1204、1205、1206、1207 配線層
1208 密着・バリア用金属とパッド接続用Al
1209 パシベーション層
1210、1211、1212 ビア層
1213 ビア
1214 配線層中の低誘電率の絶縁膜
1215 ビア層中の低誘電率の絶縁膜
1216 パッド部
1301 配線層中の金属部分
1302 ビア層中の金属部分
1401 パッド下の全面金属層
1601 チップ内部
1602 従来のパッド構造を有するパッド部
1603 金属配線
1701 亀裂
Claims (9)
- 半導体層と、
前記半導体層の上に設けられたコンタクトプラグ層と、
前記コンタクトプラグ層の上に設けられた積層体と、
前記積層体の上に設けられた電極パッドと、
を備え、
前記積層体は、前記電極パッドの下に位置するパッド下領域と、前記パッド下領域の外側に位置するパッド外領域と、を有し、
前記積層体は、配線が形成された複数の配線層と、前記複数の配線層間を電気的に接続するビアが形成された複数のビア層とを有し、
前記複数の配線層と前記複数のビア層の各々には、前記パッド下領域の周縁に沿って、閉じた構造のパッド周縁金属配線が形成され、
各々の前記パッド周縁金属配線は、その内側に配置される絶縁材料からなる部分を取り囲むことを特徴とする半導体装置。 - 上下に隣接する層にそれぞれ設けられた前記パッド周縁金属配線が相互にオーバーラップしていることを特徴とする請求項1記載の半導体装置。
- 前記配線層及び前記ビア層の少なくともいずれかは、絶縁材料により離間し環状に形成された複数の前記パッド周縁金属配線を有することを特徴とする請求項1または2に記載の半導体装置。
- 前記配線層は、前記ビア層の前記パッド周縁金属配線よりも幅広の前記パッド周縁金属配線を有し、
前記ビア層は、前記配線層の前記パッド周縁金属配線よりも幅狭の複数の前記パッド周縁金属配線を有することを特徴とする請求項1〜3のいずれか1つに記載の半導体装置。 - 前記配線層及び前記ビア層の少なくともいずれかは、前記絶縁材料として、シリコン酸化膜もしくはFSG(フッ素化シリケートグラス)よりも硬度が低い絶縁材料を有することを特徴とする請求項1〜4のいずれか1つに記載の半導体装置。
- 前記配線層及び前記ビア層の少なくともいずれかは、前記絶縁材料として、比誘電率が3以下の絶縁材料を有することを特徴とする請求項1〜5のいずれか1つに記載の半導体装置。
- 前記電極パッドはチップの周縁に沿って複数配置され、
前記複数の配線層と前記複数のビア層の各々には、チップの周縁に沿って複数配置されている前記電極パッドの下にそれぞれ位置する前記パッド下領域をまとめて取り囲むように、閉じた構造のチップ周縁金属配線が、前記パッド外領域であってチップの周縁に沿った位置に配置されていることを特徴とする請求項1〜6のいずれか1つに記載の半導体装置。 - 前記配線層は、前記ビア層の前記チップ周縁金属配線よりも幅広の前記チップ周縁金属配線を有し、
前記ビア層は、前記配線層の前記チップ周縁金属配線よりも幅狭の複数の前記チップ周縁金属配線を有することを特徴とする請求項7記載の半導体装置。 - 前記配線層及び前記ビア層の少なくともいずれかは、絶縁材料により離間し環状に形成された複数の前記チップ周縁金属配線を有することを特徴とする請求項7または8に記載の半導体装置。
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JP2004141835A JP4759229B2 (ja) | 2004-05-12 | 2004-05-12 | 半導体装置 |
US11/015,016 US20050253269A1 (en) | 2004-05-12 | 2004-12-20 | Semiconductor device |
TW093139714A TWI276148B (en) | 2004-05-12 | 2004-12-20 | Semiconductor device |
FR0413597A FR2870385A1 (fr) | 2004-05-12 | 2004-12-20 | Dispositif a semiconducteur |
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US20060244156A1 (en) * | 2005-04-18 | 2006-11-02 | Tao Cheng | Bond pad structures and semiconductor devices using the same |
JP2006339343A (ja) | 2005-06-01 | 2006-12-14 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP5109258B2 (ja) * | 2006-01-18 | 2012-12-26 | 住友ベークライト株式会社 | 半導体装置 |
JP5329068B2 (ja) * | 2007-10-22 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5131180B2 (ja) * | 2008-12-23 | 2013-01-30 | 株式会社デンソー | 半導体装置およびその製造方法 |
US8278733B2 (en) * | 2009-08-25 | 2012-10-02 | Mediatek Inc. | Bonding pad structure and integrated circuit chip using such bonding pad structure |
US20110156260A1 (en) * | 2009-12-28 | 2011-06-30 | Yu-Hua Huang | Pad structure and integrated circuit chip with such pad structure |
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JPS612351A (ja) * | 1984-06-15 | 1986-01-08 | Hitachi Tobu Semiconductor Ltd | 半導体装置 |
JP2916326B2 (ja) * | 1992-06-11 | 1999-07-05 | 三菱電機株式会社 | 半導体装置のパッド構造 |
JP3432284B2 (ja) * | 1994-07-04 | 2003-08-04 | 三菱電機株式会社 | 半導体装置 |
JPH08213422A (ja) * | 1995-02-07 | 1996-08-20 | Mitsubishi Electric Corp | 半導体装置およびそのボンディングパッド構造 |
US5863832A (en) * | 1996-06-28 | 1999-01-26 | Intel Corporation | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system |
JP3482779B2 (ja) * | 1996-08-20 | 2004-01-06 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
KR100230428B1 (ko) * | 1997-06-24 | 1999-11-15 | 윤종용 | 다층 도전성 패드를 구비하는 반도체장치 및 그 제조방법 |
JPH1154508A (ja) * | 1997-07-30 | 1999-02-26 | Sanyo Electric Co Ltd | 半導体装置及び半導体装置の製造方法 |
JPH11150114A (ja) * | 1997-11-19 | 1999-06-02 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JPH11297733A (ja) * | 1998-04-07 | 1999-10-29 | Seiko Epson Corp | 半導体装置 |
KR100319896B1 (ko) * | 1998-12-28 | 2002-01-10 | 윤종용 | 반도체 소자의 본딩 패드 구조 및 그 제조 방법 |
TW430935B (en) * | 1999-03-19 | 2001-04-21 | Ind Tech Res Inst | Frame type bonding pad structure having a low parasitic capacitance |
US6261945B1 (en) * | 2000-02-10 | 2001-07-17 | International Business Machines Corporation | Crackstop and oxygen barrier for low-K dielectric integrated circuits |
US6509622B1 (en) * | 2000-08-23 | 2003-01-21 | Intel Corporation | Integrated circuit guard ring structures |
JP3538170B2 (ja) * | 2001-09-11 | 2004-06-14 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP2004095916A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP3802002B2 (ja) * | 2003-03-27 | 2006-07-26 | 三星電子株式会社 | 半導体装置の製造方法 |
JP2005116788A (ja) * | 2003-10-08 | 2005-04-28 | Renesas Technology Corp | 半導体装置 |
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JP2005327763A (ja) | 2005-11-24 |
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