JP4525143B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4525143B2 JP4525143B2 JP2004109793A JP2004109793A JP4525143B2 JP 4525143 B2 JP4525143 B2 JP 4525143B2 JP 2004109793 A JP2004109793 A JP 2004109793A JP 2004109793 A JP2004109793 A JP 2004109793A JP 4525143 B2 JP4525143 B2 JP 4525143B2
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- JP
- Japan
- Prior art keywords
- protective film
- external connection
- semiconductor device
- pad
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
2 バリアメタル
3 最上層メタル
4 層間絶縁膜
5 配線間絶縁膜
6 保護膜
9 保護膜
Claims (9)
- 導電層からなる複数の外部接続電極と、
前記外部接続電極同士が隣接する方向と平行方向に伸びるように形成され、前記外部接続電極と離間して開口が帯状の第1の保護膜と、
隣接する前記外部接続電極間に、前記外部接続電極と離間して形成された島状の第2の保護膜とを備え、
前記第1の保護膜と前記第2の保護膜とは離間していることを特徴とする半導体装置。 - 前記第2の保護膜を矩形状にしたことを特徴とする請求項1記載の半導体装置。
- 矩形状の前記第2の保護膜の長手方向寸法を対向する前記外部接続電極の幅と同等もしくは幅以上とすることを特徴とする請求項1または2記載の半導体装置。
- 前記外部接続電極のコーナー部を切断し、面取りすることを特徴とする請求項1記載の半導体装置。
- 前記第1の保護膜と前記第2の保護膜は、SiN、またはSiNとSiO2の2層からなる請求項1から請求項4のいずれかに記載の半導体装置。
- 前記帯状の開口は、隣接する全ての外部接続電極を含むことを特徴とする請求項1から請求項5のいずれかに記載の半導体装置。
- 前記第1の保護膜および前記第2の保護膜は、前記外部接続電極と重ならないように形成されていることを特徴とする請求項6に記載の半導体装置。
- 層間絶縁膜と、
前記層間絶縁膜上に形成された複数の下層メタルと、
前記下層メタル上に形成されたバリアメタルと、
前記バリアメタル上に形成された最上層メタルと、隣接する前記下層メタル間に形成された配線間絶縁膜と、
前記下層メタルのパッド部分を開口するように、前記配線間絶縁膜上に形成された1層目の保護膜とを備え、
前記1層目の保護膜上に形成された最上層の保護膜は、前記最上層メタルと重ならないように離間して、前記最上層メタル同士が隣接する方向と平行方向に伸びるように、前記最上層メタルを帯状に開口したような形状で形成され、かつ前記最上層の保護膜は、隣接する前記最上層メタル間においては、島状に形成されていることを特徴とする半導体装置。 - 導電層からなる複数の外部接続電極と、
前記外部接続電極と離間して開口が帯状の第1の保護膜と、
隣接する前記外部接続電極間に、前記外部接続電極と離間して形成された島状の第2の保護膜とを備え、
前記第1の保護膜は、前記第2の保護膜の長手方向とは垂直方向に伸びるように形成され、
前記第1の保護膜と前記第2の保護膜とは離間していることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004109793A JP4525143B2 (ja) | 2004-04-02 | 2004-04-02 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004109793A JP4525143B2 (ja) | 2004-04-02 | 2004-04-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005294676A JP2005294676A (ja) | 2005-10-20 |
JP4525143B2 true JP4525143B2 (ja) | 2010-08-18 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004109793A Expired - Fee Related JP4525143B2 (ja) | 2004-04-02 | 2004-04-02 | 半導体装置 |
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JP (1) | JP4525143B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008034472A (ja) * | 2006-07-26 | 2008-02-14 | Sony Corp | 半導体装置及びその製造方法 |
JP5098655B2 (ja) * | 2008-01-18 | 2012-12-12 | 富士通セミコンダクター株式会社 | 電子装置 |
JP7361566B2 (ja) * | 2019-10-25 | 2023-10-16 | エイブリック株式会社 | 半導体装置およびその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62261136A (ja) * | 1986-05-07 | 1987-11-13 | Nec Corp | 半導体装置 |
JPH0536696A (ja) * | 1990-12-20 | 1993-02-12 | Toshiba Corp | 半導体装置およびその製造方法 |
JPH0936166A (ja) * | 1995-07-13 | 1997-02-07 | Samsung Electron Co Ltd | ボンディングパッド及び半導体装置 |
JP2002299370A (ja) * | 2001-03-30 | 2002-10-11 | Fujitsu Quantum Devices Ltd | 高周波半導体装置 |
-
2004
- 2004-04-02 JP JP2004109793A patent/JP4525143B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62261136A (ja) * | 1986-05-07 | 1987-11-13 | Nec Corp | 半導体装置 |
JPH0536696A (ja) * | 1990-12-20 | 1993-02-12 | Toshiba Corp | 半導体装置およびその製造方法 |
JPH0936166A (ja) * | 1995-07-13 | 1997-02-07 | Samsung Electron Co Ltd | ボンディングパッド及び半導体装置 |
JP2002299370A (ja) * | 2001-03-30 | 2002-10-11 | Fujitsu Quantum Devices Ltd | 高周波半導体装置 |
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JP2005294676A (ja) | 2005-10-20 |
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