TWI718812B - 微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統 - Google Patents

微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統 Download PDF

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TWI718812B
TWI718812B TW108146081A TW108146081A TWI718812B TW I718812 B TWI718812 B TW I718812B TW 108146081 A TW108146081 A TW 108146081A TW 108146081 A TW108146081 A TW 108146081A TW I718812 B TWI718812 B TW I718812B
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wafer
level electronic
electronic chip
conductive
chip
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TW202125653A (zh
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廖建碩
張德富
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台灣愛司帝科技股份有限公司
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Priority to CN202010042697.4A priority patent/CN112992812A/zh
Priority to US16/997,191 priority patent/US11355407B2/en
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Abstract

本發明公開一種微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統。晶片組件堆疊系統包括依序堆疊且彼此電性連接的多個晶圓級電子晶片組件。每一晶圓級電子晶片組件包括一晶圓級電子晶片以及設置在晶圓級電子晶片上的一微加熱器晶片。微加熱器晶片包括一加熱結構以及設置在加熱結構與晶圓級電子晶片之間的一絕緣結構。加熱結構包括一承載本體、設置在承載本體上或者內部的至少一微加熱器以及多個貫穿承載本體的導電連接層。藉此，微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統各別都能夠擁有至少一微加熱器，以利於對錫球進行加熱。

Description

微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統
本發明涉及一種微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統，特別是涉及一種具有至少一微加器的微加熱器晶片、具有至少一微加器的晶圓級電子晶片組件以及具有至少一微加器的晶片組件堆疊系統。
現有的電子晶片會透過錫球的加熱而電性連接於一電路板上，然而在現有技術中對於錫球的加熱仍具有可改善空間。
本發明所要解決的技術問題在於，針對現有技術的不足提供一種微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統。
為了解決上述的技術問題，本發明所採用的其中一技術方案是，提供一種應用於晶圓級電子晶片的微加熱器晶片，其包括：一暫時性承載基板、一加熱結構以及一絕緣結構。所述加熱結構設置在所述暫時性承載基板上，且所述絕緣結構設置在所述加熱結構上。其中，所述加熱結構包括設置在所述暫時性承載基板上的一承載本體、設置在所述承載本體上或者內部的至少一微加熱器以及多個貫穿所述承載本體的導電連接層；其中，所述絕緣結構包括設置在所述加熱結構上的一絕緣本體以及貫穿所述絕緣本體的多個導電材料層，且多個所述導電材料層分別電性連接於多個所述導電連接層。
為了解決上述的技術問題，本發明所採用的另外一技術方案是，提供一種晶圓級電子晶片組件，其包括一晶圓級電子晶片以及設置在所述晶圓級電子晶片上的一微加熱器晶片，其特徵在於，所述微加熱器晶片包括：一加熱結構以及設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣結構；其中，所述加熱結構包括一承載本體、設置在所述承載本體上或者內部的至少一微加熱器以及多個貫穿所述承載本體的導電連接層；其中，所述絕緣結構包括設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣本體以及貫穿所述絕緣本體的多個導電材料層，且多個所述導電材料層分別電性連接於多個所述導電連接層。
為了解決上述的技術問題，本發明所採用的另外再一技術方案是，提供一種晶片組件堆疊系統，其包括依序堆疊且彼此電性連接的多個晶圓級電子晶片組件，每一所述晶圓級電子晶片組件包括一晶圓級電子晶片以及設置在所述晶圓級電子晶片上的一微加熱器晶片，其特徵在於，所述微加熱器晶片包括：一加熱結構以及設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣結構；其中，所述加熱結構包括一承載本體、設置在所述承載本體上或者內部的至少一微加熱器以及多個貫穿所述承載本體的導電連接層；其中，所述絕緣結構包括設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣本體以及貫穿所述絕緣本體的多個導電材料層，且多個所述導電材料層分別電性連接於多個所述導電連接層。
更進一步來說，所述晶圓級電子晶片包括一電路承載體、被所述電路承載體所承載的一電路布局以及貫穿所述電路承載體的多個導電貫穿層，所述電路布局電性連接於多個所述導電貫穿層，且所述晶圓級電子晶片具有一頂端導電接點；其中，所述導電材料層的一第一末端電性連接於所述晶圓級電子晶片的所述頂端導電接點，且所述導電材料層的一第二末端電性接觸所述導電連接層的一第一末端；其中，所述導電連接層的一第二末端從所述承載本體裸露，且所述導電連接層的所述第二末端通過一錫球以電性連接於相鄰的所述晶圓級電子晶片的一底端導電接點。
更進一步來說，所述加熱結構包括圍繞所述至少一微加熱器與多個所述導電連接層的絕緣性保護層，且所述絕緣性保護層設置在所述絕緣結構與相鄰的所述晶圓級電子晶片之間；其中，所述加熱結構包括電性連接於所述至少一微加熱器的一電源輸入點，且所述電源輸入點不會被相鄰的所述晶圓級電子晶片組件的所述晶圓級電子晶片所遮蔽；其中，所述晶圓級電子晶片組件的外側面為一切割面。
更進一步來說，多個所述晶圓級電子晶片組件依序堆疊在一電路基板上，且位於最下方的所述晶圓級電子晶片組件通過多個錫球以電性連接於所述電路基板。
本發明的其中一有益效果在於，本發明所提供的微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統，其能通過“所述加熱結構包括一承載本體、設置在所述承載本體上或者內部的至少一微加熱器以及多個貫穿所述承載本體的導電連接層”以及“所述絕緣結構包括設置在所述加熱結構上的一絕緣本體以及貫穿所述絕緣本體的多個導電材料層，且多個所述導電材料層分別電性連接於多個所述導電連接層”的技術方案，以使得所述微加熱器晶片能夠擁有所述至少一微加熱器，使得所述晶圓級電子晶片組件能夠擁有所述至少一微加熱器，且使得所述晶片組件堆疊系統能夠擁有所述至少一微加熱器。
為使能更進一步瞭解本發明的特徵及技術內容，請參閱以下有關本發明的詳細說明與圖式，然而所提供的圖式僅用於提供參考與說明，並非用來對本發明加以限制。
以下是通過特定的具體實施例來說明本發明所公開有關“微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統”的實施方式，本領域技術人員可由本說明書所公開的內容瞭解本發明的優點與效果。本發明可通過其他不同的具體實施例加以施行或應用，本說明書中的各項細節也可基於不同觀點與應用，在不悖離本發明的構思下進行各種修改與變更。另外，本發明的附圖僅為簡單示意說明，並非依實際尺寸的描繪，事先聲明。以下的實施方式將進一步詳細說明本發明的相關技術內容，但所公開的內容並非用以限制本發明的保護範圍。
應當可以理解的是，雖然本文中可能會使用到“第一”、“第二”等術語來描述各種元件，但這些元件不應受這些術語的限制。這些術語主要是用以區分一元件與另一元件。另外，本文中所使用的術語“或”，應視實際情況可能包括相關聯的列出項目中的任一個或者多個的組合。
[第一實施例]
參閱圖1與圖2所示，本發明第一實施例提供一種第一晶圓W1，其包括多個晶圓級電子晶片1，並且每一晶圓級電子晶片1包括一電路承載體100、被電路承載體100所承載的一電路布局101以及貫穿電路承載體100的多個導電貫穿層102。另外，電路布局101會電性連接於多個導電貫穿層102，並且晶圓級電子晶片1具有一底端導電接點1010以及頂端導電接點1020。舉例來說，電路布局101可以包括電性連接於多個導電貫穿層102的一導電線路區1011以及與多個導電貫穿層102彼此緣絕的一非線路區1012，然而本發明不以此舉例為限。
參閱圖3與圖4所示，本發明第一實施例還進一步提供一種第二晶圓W2，其包括多個應用於晶圓級電子晶片1的微加熱器晶片2，並且每一微加熱器晶片2包括一暫時性承載基板T、一加熱結構21以及一絕緣結構22。
更進一步來說，如圖4所示，加熱結構21被暫時性地設置在暫時性承載基板T上，並且絕緣結構22被設置在加熱結構21上。此外，加熱結構21包括設置在暫時性承載基板T上的一承載本體210、設置在承載本體210上或者內部的至少一微加熱器211以及多個貫穿承載本體210的導電連接層212。另外，加熱結構21還進一步包括圍繞至少一微加熱器211與多個導電連接層212的絕緣性保護層213，並且絕緣性保護層213被設置在暫時性承載基板T與絕緣結構22之間。再者，導電連接層212具有一第一末端2121以及一第二末端2122。
更進一步來說，如圖4所示，絕緣結構22包括設置在加熱結構21上的一絕緣本體220以及貫穿絕緣本體220的多個導電材料層221，並且多個導電材料層221分別電性連接於多個導電連接層212。另外，導電材料層221的一第一末端2211從絕緣本體220裸露，並且導電材料層221的一第二末端2212電性接觸導電連接層212的第一末端2121。
[第二實施例]
參閱圖5至圖8所示，在本發明第二實施例中，第一晶圓W1會先放置在第二晶圓W2上（配合圖5與圖6所示），接著再將暫時性承載基板T從第二晶圓W2移除（配合圖6與圖7所示），最後再沿著圖7的切割線（假想線）切割第一晶圓W1與第二晶圓W2，以形成多個晶圓級電子晶片組件A（如圖8所示）。因此，如圖8所示，本發明第二實施例能提供一種晶圓級電子晶片組件A，其包括一晶圓級電子晶片1以及設置在晶圓級電子晶片1上的一微加熱器晶片2，並且微加熱器晶片2包括一加熱結構21以及設置在加熱結構21與晶圓級電子晶片1之間的一絕緣結構22。
更進一步來說，如圖8所示，加熱結構21包括一承載本體210、設置在承載本體210上或者內部的至少一微加熱器211以及多個貫穿承載本體210的導電連接層212。另外，絕緣結構22包括設置在加熱結構21與晶圓級電子晶片1之間的一絕緣本體220以及貫穿絕緣本體220的多個導電材料層221，並且多個導電材料層221分別電性連接於多個導電連接層212。再者，加熱結構21包括圍繞至少一微加熱器211與多個導電連接層212的絕緣性保護層213，並且絕緣性保護層213設置在絕緣結構22與另一晶圓級電子晶片（圖未示）之間。值得注意的是，配合圖7與圖8所示，由於第一晶圓W1與第二晶圓W2經過切割步驟，所以晶圓級電子晶片組件A的外側面會因為切割步驟而呈現為一切割面A100。
更進一步來說，如圖8所示，晶圓級電子晶片1包括一電路承載體100、被電路承載體100所承載的一電路布局101以及貫穿電路承載體100的多個導電貫穿層102，電路布局101電性連接於多個導電貫穿層102，並且晶圓級電子晶片1的導電貫穿層102具有一頂端導電接點1020。另外，導電材料層221的一第一末端2211電性連接於晶圓級電子晶片1的頂端導電接點1020，並且導電材料層221的一第二末端2212電性接觸導電連接層212的一第一末端2121。此外，導電連接層212的一第二末端2122從承載本體210裸露，並且導電連接層212的第二末端2122能通過一錫球（圖未示）以電性連接於一另一晶圓級電子晶片（圖未示）的一底端導電接點。值得注意的是，當暫時性承載基板T從微加熱器晶片2移除後（配合圖7與圖8所示），導電連接層212的第二末端2122會從承載本體210裸露。
[第三實施例]
參閱圖8與圖9所示，本發明第三實施例提供一種晶片組件堆疊系統S，其包括依序堆疊且彼此電性連接的多個晶圓級電子晶片組件A。每一晶圓級電子晶片組件A包括一晶圓級電子晶片1以及設置在晶圓級電子晶片1上的一微加熱器晶片2，並且微加熱器晶片2包括一加熱結構21以及設置在加熱結構21與晶圓級電子晶片1之間的一絕緣結構22。再者，多個晶圓級電子晶片組件A會依序堆疊在一電路基板P上，並且位於最下方的晶圓級電子晶片組件A能通過多個錫球B以電性連接於電路基板P。藉此，本發明能驅動微加熱器211以對多個錫球B進行加熱，使得多個晶圓級電子晶片組件A能以焊接的方式堆疊設置在電路基板P上。
更進一步來說，如圖8所示，加熱結構21包括一承載本體210、設置在承載本體210上或者內部的至少一微加熱器211以及多個貫穿承載本體210的導電連接層212。另外，絕緣結構22包括設置在加熱結構21與晶圓級電子晶片1之間的一絕緣本體220以及貫穿絕緣本體220的多個導電材料層221，並且多個導電材料層221分別電性連接於多個導電連接層212。再者，加熱結構21包括圍繞至少一微加熱器211與多個導電連接層212的絕緣性保護層213，並且絕緣性保護層213設置在絕緣結構22與相鄰的晶圓級電子晶片1之間。值得注意的是，配合圖7與圖8所示，由於第一晶圓W1與第二晶圓W2經過切割步驟，所以晶圓級電子晶片組件A的外側面會因為切割步驟而呈現為一切割面A100。
更進一步來說，如圖8所示，晶圓級電子晶片1包括一電路承載體100、被電路承載體100所承載的一電路布局101以及貫穿電路承載體100的多個導電貫穿層102，電路布局101電性連接於多個導電貫穿層102，並且晶圓級電子晶片1的導電貫穿層102具有一頂端導電接點1020。另外，導電材料層221的一第一末端2211電性連接於晶圓級電子晶片1的頂端導電接點1020，並且導電材料層221的一第二末端2212電性接觸導電連接層212的一第一末端2121。此外，導電連接層212的一第二末端2122從承載本體210裸露，並且導電連接層212的第二末端2122能通過一錫球B以電性連接於相鄰的晶圓級電子晶片1的底端導電接點1010。
值得注意的是，配合圖8、圖10以及圖11所示，加熱結構21包括電性連接於至少一微加熱器211的一電源輸入點214。由於多個所述晶圓級電子晶片組件A能以彼此錯位（交錯設置）的方式依序堆疊在一起，所以電源輸入點214不會被相鄰的晶圓級電子晶片組件A的晶圓級電子晶片1所遮蔽，以便於使用者能直接對電源輸入點214輸入電源，藉此以驅動至少一微加熱器211對錫球B進行加熱，使得多個晶圓級電子晶片組件A能以焊接的方式堆疊在一起。舉例來說，電源輸入點214可以包括一正極接點與一負極接點，然而本發明不以上述所舉的例子為限。
[實施例的有益效果]
本發明的其中一有益效果在於，本發明所提供的微加熱器晶片1、晶圓級電子晶片組件A以及晶片組件堆疊系統S，其能通過“加熱結構21包括一承載本體210、設置在承載本體210上或者內部的至少一微加熱器211以及多個貫穿承載本體210的導電連接層212”以及“絕緣結構22包括設置在加熱結構21上的一絕緣本體220以及貫穿絕緣本體220的多個導電材料層221，且多個導電材料層221分別電性連接於多個導電連接層212”的技術方案，以使得微加熱器晶片2能夠擁有至少一微加熱器211，使得晶圓級電子晶片組件A能夠擁有至少一微加熱器211，且使得晶片組件堆疊系統S能夠擁有至少一微加熱器211。
以上所公開的內容僅為本發明的優選可行實施例，並非因此侷限本發明的申請專利範圍，所以凡是運用本發明說明書及圖式內容所做的等效技術變化，均包含於本發明的申請專利範圍內。
W1:第一晶圓　　　　　　 W2:第二晶圓　　　　　　 S:晶片組件堆疊系統　　 A:晶圓級電子晶片組件A100:切割面　　　　　　　 1:晶圓級電子晶片100:電路承載體　　　　　 101:電路布局　　　　　　 1010:底端導電接點　　　　 1011:導電線路區　　　　　 1012:非線路區　　　　　　 102:導電貫穿層　　　　　 1020:頂端導電接點　　　　 2:微加熱器晶片T:暫時性承載基板　　　 21:加熱結構　　　　　　 210:承載本體　　　　　　 211:微加熱器　　　　　　 212:導電連接層　　　　　 2121:第一末端　　　　　　 2122:第二末端　　　　　　 213:絕緣性保護層　　　　 214:電源輸入點　　　　　 22:絕緣結構　　　　　　 220:絕緣本體　　　　　　 221:導電材料層　　　　　 2211:第一末端　　　　　　 2212:第二末端　　　　　　 B:錫球　　　　　　　　 P:電路基板　　　　　　
圖1為本發明第一實施例的第一晶圓的示意圖。
圖2為本發明第一實施例的晶圓級電子晶片的示意圖。
圖3為本發明第一實施例的第二晶圓的示意圖。
圖4為本發明第一實施例的微加熱器晶片的示意圖。
圖5為本發明第二實施例的微加熱器晶片設置在晶圓級電子晶片之前的示意圖。
圖6為本發明第二實施例的微加熱器晶片設置在晶圓級電子晶片之後的示意圖。
圖7為本發明第二實施例的暫時性承載基板從第二晶圓移除之後的示意圖。
圖8為本發明第二實施例的晶圓級電子晶片組件的示意圖。
圖9為本發明第三實施例的其中一種晶片組件堆疊系統的示意圖。
圖10為本發明第三實施例的另外一種晶片組件堆疊系統的示意圖。
圖11為本發明第三實施例的微加熱器與電源輸入點相互電性連接的功能方塊圖。
A:晶圓級電子晶片組件
A100:切割面
1:晶圓級電子晶片
100:電路承載體
101:電路布局
1010:底端導電接點
1011:導電線路區
1012:非線路區
102:導電貫穿層
1020:頂端導電接點
2:微加熱器晶片
21:加熱結構
210:承載本體
211:微加熱器
212:導電連接層
2121:第一末端
2122:第二末端
213:絕緣性保護層
22:絕緣結構
220:絕緣本體
221:導電材料層
2211:第一末端
2212:第二末端

Claims (9)

  1. 一種應用於晶圓級電子晶片的微加熱器晶片，其包括：一暫時性承載基板；一加熱結構，其設置在所述暫時性承載基板上；以及一絕緣結構，其設置在所述加熱結構上；其中，所述加熱結構包括設置在所述暫時性承載基板上的一承載本體、設置在所述承載本體上或者內部的至少一微加熱器以及多個貫穿所述承載本體的導電連接層；其中，所述絕緣結構包括設置在所述加熱結構上的一絕緣本體以及貫穿所述絕緣本體的多個導電材料層，且多個所述導電材料層分別電性連接於多個所述導電連接層；其中，所述加熱結構包括圍繞所述至少一微加熱器與多個所述導電連接層的一絕緣性保護層，所述絕緣性保護層設置在所述暫時性承載基板與所述絕緣結構之間，且所述加熱結構包括電性連接於所述至少一微加熱器的一電源輸入點。
  2. 如申請專利範圍第1項所述的應用於晶圓級電子晶片的微加熱器晶片，其中，所述導電材料層的一第一末端從所述絕緣本體裸露，以用於電性連接於一第一晶圓級電子晶片的一頂端導電接點，且所述導電材料層的一第二末端電性接觸所述導電連接層的一第一末端；其中，當所述暫時性承載基板從所述微加熱器晶片移除後，所述導電連接層的一第二末端從所述承載本體裸露，且所述導電連接層的所述第二末端通過一錫球以電性連接於一第二晶圓級電子晶片的一底端導電接點。
  3. 一種晶圓級電子晶片組件，其包括一晶圓級電子晶片以及設置在所述晶圓級電子晶片上的一微加熱器晶片，其特徵在於，所述微加熱器晶片包括：一加熱結構以及設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣結構； 其中，所述加熱結構包括一承載本體、設置在所述承載本體上或者內部的至少一微加熱器以及多個貫穿所述承載本體的導電連接層；其中，所述絕緣結構包括設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣本體以及貫穿所述絕緣本體的多個導電材料層，且多個所述導電材料層分別電性連接於多個所述導電連接層；其中，所述加熱結構包括圍繞所述至少一微加熱器與多個所述導電連接層的一絕緣性保護層，所述絕緣性保護層設置在所述絕緣結構與一另一晶圓級電子晶片之間，且所述加熱結構包括電性連接於所述至少一微加熱器的一電源輸入點。
  4. 如申請專利範圍第3項所述的晶圓級電子晶片組件，其中，所述晶圓級電子晶片包括一電路承載體、被所述電路承載體所承載的一電路布局以及貫穿所述電路承載體的多個導電貫穿層，所述電路布局電性連接於多個所述導電貫穿層，且所述晶圓級電子晶片具有一頂端導電接點；其中，所述導電材料層的一第一末端電性連接於所述晶圓級電子晶片的所述頂端導電接點，且所述導電材料層的一第二末端電性接觸所述導電連接層的一第一末端；其中，所述導電連接層的一第二末端從所述承載本體裸露，且所述導電連接層的所述第二末端通過一錫球以電性連接於所述另一晶圓級電子晶片的一底端導電接點。
  5. 如申請專利範圍第3項所述的晶圓級電子晶片組件，其中，所述電源輸入點不會被所述另一晶圓級電子晶片所遮蔽；其中，所述晶圓級電子晶片組件的外側面為一切割面。
  6. 一種晶片組件堆疊系統，其包括依序堆疊且彼此電性連接的多個晶圓級電子晶片組件，每一所述晶圓級電子晶片組件包括一晶圓級電子晶片以及設置在所述晶圓級電子晶片上的一微加熱 器晶片，其特徵在於，所述微加熱器晶片包括：一加熱結構以及設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣結構；其中，所述加熱結構包括一承載本體、設置在所述承載本體上或者內部的至少一微加熱器以及多個貫穿所述承載本體的導電連接層；其中，所述絕緣結構包括設置在所述加熱結構與所述晶圓級電子晶片之間的一絕緣本體以及貫穿所述絕緣本體的多個導電材料層，且多個所述導電材料層分別電性連接於多個所述導電連接層。
  7. 如申請專利範圍第6項所述的晶片組件堆疊系統，其中，所述晶圓級電子晶片包括一電路承載體、被所述電路承載體所承載的一電路布局以及貫穿所述電路承載體的多個導電貫穿層，所述電路布局電性連接於多個所述導電貫穿層，且所述晶圓級電子晶片具有一頂端導電接點；其中，所述導電材料層的一第一末端電性連接於所述晶圓級電子晶片的所述頂端導電接點，且所述導電材料層的一第二末端電性接觸所述導電連接層的一第一末端；其中，所述導電連接層的一第二末端從所述承載本體裸露，且所述導電連接層的所述第二末端通過一錫球以電性連接於相鄰的所述晶圓級電子晶片的一底端導電接點。
  8. 如申請專利範圍第7項所述的晶片組件堆疊系統，其中，所述加熱結構包括圍繞所述至少一微加熱器與多個所述導電連接層的絕緣性保護層，且所述絕緣性保護層設置在所述絕緣結構與相鄰的所述晶圓級電子晶片之間；其中，所述加熱結構包括電性連接於所述至少一微加熱器的一電源輸入點，且所述電源輸入點不會被相鄰的所述晶圓級電子晶片組件的所述晶圓級電子晶片所遮蔽；其中，所述晶圓級電子晶片組件的外側面為一切 割面。
  9. 如申請專利範圍第6項所述的晶片組件堆疊系統，其中，多個所述晶圓級電子晶片組件依序堆疊在一電路基板上，且位於最下方的所述晶圓級電子晶片組件通過多個錫球以電性連接於所述電路基板。
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TWI718812B (zh) * 2019-12-17 2021-02-11 台灣愛司帝科技股份有限公司 微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200539247A (en) * 2004-05-20 2005-12-01 Shih-Hsien Tseng Modulized integrated circuit and a manufacturing method thereof
CN103187397A (zh) * 2011-12-27 2013-07-03 中芯国际集成电路制造(上海)有限公司 微加热装置
TW201338107A (zh) * 2012-03-09 2013-09-16 Univ Nat Chiao Tung 晶圓級封裝方法與封裝結構
TW201721781A (zh) * 2015-09-25 2017-06-16 英特爾股份有限公司 使用從載體晶圓的受控的去結合的選擇性晶粒轉移

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7332411B2 (en) * 2004-08-12 2008-02-19 Hewlett-Packard Development Company, Lp Systems and methods for wafer bonding by localized induction heating
DE102005009164B4 (de) * 2005-02-25 2007-09-06 Infineon Technologies Ag Kontaktanschlussfläche mit Heizerstruktur und Verfahren zum Herstellen oder Betreiben derselben
JP2006295019A (ja) * 2005-04-14 2006-10-26 Fujitsu Ltd 電子部品を基板に取り付け及び取り外す加熱装置
FR2912029B1 (fr) * 2007-01-31 2010-10-22 Hispano Suiza Sa Carte electronique incorporant une resistance chauffante.
JP2012049338A (ja) * 2010-08-27 2012-03-08 Hitachi Ltd ヒータ配線付き半導体チップ
FR2981795B1 (fr) * 2011-10-25 2015-01-02 Commissariat Energie Atomique Hybridation flip-chip de composants microelectroniques par chauffage local des elements de connexion
KR101939240B1 (ko) * 2011-11-25 2019-01-17 삼성전자 주식회사 반도체 패키지
US10731428B2 (en) * 2016-04-19 2020-08-04 Recover Energy Services Inc. Multi-stage drilling waste material recovery process
US10197623B2 (en) * 2016-09-15 2019-02-05 Texas Instruments Incorporated Heatable interposer for temperature-controlled testing of semiconductor devices
TWI698964B (zh) * 2019-03-15 2020-07-11 台灣愛司帝科技股份有限公司 晶片固接結構及晶片固接設備
TWI698949B (zh) * 2019-08-07 2020-07-11 台灣愛司帝科技股份有限公司 薄膜結構、晶片承載組件及晶片承載設備
TWI730493B (zh) * 2019-11-06 2021-06-11 台灣愛司帝科技股份有限公司 具有加熱功能的非導電薄膜以及電子裝置
TWI718812B (zh) * 2019-12-17 2021-02-11 台灣愛司帝科技股份有限公司 微加熱器晶片、晶圓級電子晶片組件以及晶片組件堆疊系統
TWI718923B (zh) * 2020-04-08 2021-02-11 台灣愛司帝科技股份有限公司 發光二極體晶片結構以及晶片移轉系統與方法
TWI775111B (zh) * 2020-07-15 2022-08-21 歆熾電氣技術股份有限公司 晶片承載結構與晶片安裝方法
TWI727853B (zh) * 2020-07-15 2021-05-11 歆熾電氣技術股份有限公司 晶片移轉系統與晶片移轉方法
TWI770612B (zh) * 2020-09-18 2022-07-11 歆熾電氣技術股份有限公司 晶片移轉系統與晶片移轉方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200539247A (en) * 2004-05-20 2005-12-01 Shih-Hsien Tseng Modulized integrated circuit and a manufacturing method thereof
CN103187397A (zh) * 2011-12-27 2013-07-03 中芯国际集成电路制造(上海)有限公司 微加热装置
TW201338107A (zh) * 2012-03-09 2013-09-16 Univ Nat Chiao Tung 晶圓級封裝方法與封裝結構
TW201721781A (zh) * 2015-09-25 2017-06-16 英特爾股份有限公司 使用從載體晶圓的受控的去結合的選擇性晶粒轉移

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