CN105789176A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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CN105789176A
CN105789176A CN201410809053.8A CN201410809053A CN105789176A CN 105789176 A CN105789176 A CN 105789176A CN 201410809053 A CN201410809053 A CN 201410809053A CN 105789176 A CN105789176 A CN 105789176A
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dielectric layer
layer
encapsulating structure
making
blind holes
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陈贤文
陈仕卿
赖杰隆
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装结构及其制法，该封装结构包括：具有相对的第一表面与第二表面的一介电层、形成于该第一表面上且具有贯穿该介电层的多个导电盲孔的线路层、设于该第一表面上且电性连接该线路层的电子组件、包覆该电子组件的封装材、以及设于该第二表面上并电性连接该些导电盲孔的封装基板，藉由介电层取代现有硅板体，并利用线路层作为电子组件与封装基板之间讯号传递的介质，所以无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构及其制法，尤指一种节省制作成本的封装结构及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术，例如芯片尺寸构装(ChipScalePackage，简称CSP)、芯片直接贴附封装(DirectChipAttached，简称DCA)或多芯片模块封装(Multi-ChipModule，简称MCM)等覆晶型态的封装模块、或将芯片立体堆栈化整合为三维集成电路(3DIC)芯片堆栈技术等。
图1A至图1F为现有3D芯片堆栈的封装结构1的制法的剖面示意图。
如图1A所示，提供一具有相对的转接侧10b与置晶侧10a的硅板体10，且该硅板体10的置晶侧10a上形成有多个开孔100。
如图1B所示，将绝缘材102与导电材(如铜材)填入该些开孔100中以形成导电硅穿孔(Through-siliconvia，简称TSV)101。接着，于该置晶侧10a上形成一电性连接该导电硅穿孔101的线路重布结构(Redistributionlayer，简称RDL)。
具体地，该线路重布结构的制法，其包括形成一介电层11于该置晶侧10a上，再形成一线路层12于该介电层11上，且该线路层12形成有位于该介电层11中并电性连接该导电硅穿孔101的多个导电盲孔120，之后形成一绝缘保护层13于该介电层11与该线路层12上，且该绝缘保护层13外露部分该线路层11，最后结合多个如焊锡凸块的第一导电组件14于该线路层12的外露表面上。
如图1C所示，研磨该转接侧10b的部分材质，使该些导电硅穿孔101的端面外露于该转接侧10b’。
如图1D所示，先形成一绝缘保护层15于该转接侧10b’上，且该绝缘保护层15外露该些导电硅穿孔101的端面，再结合多个第二导电组件16于该些导电硅穿孔101的端面上，且该第二导电组件16电性连接该导电硅穿孔101，其中，该第二导电组件16含有焊锡材料或铜凸块，且可选择性含有凸块底下金属层(UnderBumpMetallurgy，简称UBM)160。
如图1E所示，沿如图1D所示的切割路径S进行切单制程，以获取多个硅中介板(ThroughSiliconinterposer，简称TSI)1a，再将至少一硅中介板1a以其第二导电组件16设于一封装基板19上，使该封装基板19电性连接该些导电硅穿孔101，其中，该封装基板19以间距较大的电性接触垫190结合该些第二导电组件16，使该些第二导电组件16电性连接该些导电硅穿孔101，再以底胶191包覆该些第二导电组件16。
如图1F所示，将具有间距较小的电极垫的多个电子组件17(如芯片)设置于该些第一导电组件14上，使该电子组件17电性连接该线路层12，其中，该电子组件17以覆晶方式结合该些第一导电组件14，再以底胶171包覆该些第一导电组件14。
接着，形成封装材18于该封装基板19上，以令该封装材18包覆该电子组件17与该硅中介板1a。
最后，形成多个焊球192于该封装基板19的下侧，以供接置于一如电路板的电子装置(图略)上。
惟，现有封装结构1的制法中，使用硅中介板1a作为电子组件17与封装基板19之间讯号传递的介质，因需具备一定深宽比的控制(即该导电硅穿孔101的深宽比)，才能制作出适用的硅中介板1a，因而提高制程难度及制作成本。
此外，于制程中所使用的承载件(图略)均为硅板，且均以机械剥离方式移除该些硅板，导致容易损毁该些硅板，所以无法继续使用该些硅板，因而耗费材料。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明为提供一种封装结构及其制法，无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本。
本发明的封装结构，包括：一介电层，其具有相对的第一表面与第二表面；线路层，其形成于该介电层的第一表面上，且该线路层形成有贯穿该介电层的多个导电盲孔；至少一电子组件，其设于该介电层的第一表面上且电性连接该线路层；封装材，其形成于该线路层与该介电层的第一表面上并包覆该电子组件；以及封装基板，其设于该介电层的第二表面上并电性连接该些导电盲孔。
本发明还提供一种封装结构的制法，其包括：形成一介电层于一承载件上，且该介电层具有相对的第一表面与第二表面，并以该第二表面结合至该承载件上；形成线路层于该介电层的第一表面上，且该线路层形成有多个位于该介电层中的导电盲孔，该些导电盲孔并连通该介电层的第二表面；移除该承载件，使该些导电盲孔的端面外露于该介电层的第二表面；设置至少一电子组件于该介电层的第一表面上，使该电子组件电性连接该线路层；形成封装材于该线路层与该介电层的第一表面上，以令该封装材包覆该电子组件；以及设置封装基板于该介电层的第二表面上，使该封装基板电性连接该些导电盲孔。
前述的封装结构及其制法中，该些导电盲孔的端面齐平该介电层的第二表面。
前述的封装结构及其制法中，该电子组件为主动组件、被动组件或其二者组合。
前述的封装结构及其制法中，还包括形成多个第一导电组件于该线路层上，以供结合该电子组件于该些第一导电组件上。
前述的封装结构及其制法中，还包括形成该些第一导电组件前，形成绝缘保护层于该介电层的第一表面与该线路层上，且该绝缘保护层外露部分该线路层。
前述的封装结构及其制法中，还包括形成第二导电组件于该些导电盲孔的端面上，以供结合该封装基板于该些第一导电组件上。
前述的封装结构及其制法中，还包括形成该些第二导电组件前，形成绝缘保护层于该介电层的第二表面与该些导电盲孔的端面上，且该绝缘保护层外露该些导电盲孔的端面。
由上可知，本发明的封装结构及其制法，藉由介电层取代现有硅板体，并利用线路层作为电子组件与封装基板之间讯号传递的介质，所以无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本。
附图说明
图1A至图1F为现有封装结构的制法的剖面示意图；以及
图2A至图2G为本发明的封装结构的制法的剖面示意图。
主要组件符号说明
1、2封装结构
1a硅中介板
10硅板体
10a置晶侧
10b、10b’转接侧
100开孔
101导电硅穿孔
102绝缘材
11、21介电层
12、22线路层
120、220导电盲孔
13、15、23、25绝缘保护层
14、24第一导电组件
16、26第二导电组件
160、260凸块底下金属层
17、27电子组件
171、191、271、291底胶
18、28封装材
19、29封装基板
190、290电性接触垫
192、292焊球
2a封装件
20承载件
200结合层
21a第一表面
21b第二表面
210盲孔
221端面
270导电凸块
S切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的封装结构2的制法的剖面示意图。
如图2A所示，形成一介电层21于一承载件20上，且该介电层21具有相对的第一表面21a与第二表面21b，并以该第二表面21b结合至该承载件20上。
于本实施例中，该承载件20为玻璃板并具有如黏胶或离型膜的结合层200，以供结合该介电层21的第二表面21b。
此外，该介电层21的材质为感光介质(photoimageabledielectric，简称PID)或聚酰亚胺(Polyimide，简称PI)。
又，该介电层21具有贯穿该第一与第二表面21a,21b的多个盲孔210，以外露部分该承载件20的结合层200。
另外，该介电层21的第一表面21a作为置晶侧，而该介电层21的第二表面21b作为转接侧。
如图2B所示，是以电镀铜方式形成一线路层22于该介电层21的第一表面21a上，且该线路层22形成有多个位于该盲孔210中的导电盲孔220，该些导电盲孔220并连通该介电层21的第二表面21b。
如图2C所示，形成多个如导电凸块的第一导电组件24于该线路层22上。
于本实施例中，先形成一绝缘保护层23于该介电层21的第一表面21a与该线路层22上，且该绝缘保护层23外露部分该线路层21，再形成该些第一导电组件24于该线路层22的外露表面上。
此外，该第一导电组件24含有焊锡材料或铜凸块，且可选择性含有凸块底下金属层(UBM)。
如图2D所示，移除该承载件20及结合层200，使该导电盲孔220的端面221外露于该介电层21的第二表面21b。
于本实施例中，利用激光穿透该承载件20，以烧除该结合层200，而分离该承载件20与该介电层21；若该结合层200为离型膜，则直接剥离即可。
此外，该些导电盲孔220的端面221齐平该介电层21的第二表面21b。
如图2E所示，形成多个如导电凸块的第二导电组件26于该些导电盲孔220的端面221上。
于本实施例中，先形成一绝缘保护层25于该介电层21的第二表面21b与该些导电盲孔220的端面221上，且该绝缘保护层25外露该些导电盲孔220的端面221，再形成该些第二导电组件26于该些导电盲孔220的端面221上。
此外，该第二导电组件26含有焊锡材料或铜凸块，且可选择性含有凸块底下金属层(UBM)260。
如图2F所示，设置多个电子组件27于该介电层21的第一表面21a上的第一导电组件24上，使该电子组件27电性连接该线路层21。接着，形成封装材28于该线路层21与该介电层21的第一表面21a上，以令该封装材28包覆该电子组件27。
于本实施例中，该电子组件27为主动组件、被动组件或其二者组合，且该主动组件例如为半导体芯片，而该被动组件例如为电阻、电容及电感。
此外，该电子组件27以导电凸块270结合该第一导电组件24，再以底胶271包覆该些导电凸块270与该些第一导电组件24。
如图2G所示，沿如图2F所示的切割路径S进行切单制程，以获取多个封装件2a，再将至少一封装件2a以其第二导电组件26设于一封装基板29上，使该封装基板29电性连接该些导电盲孔220。接着，形成多个焊球292于该封装基板29的下侧，以供接置于一如电路板的电子装置上。
于本实施例中，该封装基板29以多个电性接触垫290结合该些第二导电组件26，再以底胶291包覆该些第二导电组件26。
本发明的制法中，其以感光介质或聚酰亚胺的介电层21取代现有硅板体，并利用线路层22作为电子组件27与封装基板29之间讯号传递的介质，所以无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本。
此外，于制程中所使用的承载件20为玻璃板，且以激光穿透玻璃板烧除该结合层200的方式而移除该承载件20，使该承载件20不受损毁，所以可重复使用该承载件20，以降低材料成本。
另外，本发明的方法的步骤可依需求调整，例如，于制作该些第一导电组件24(图2C)后，可先设置该电子组件27于该些第一导电组件24上，再移除该承载件20及其结合层200，之后制作该些第二导电组件26。
本发明提供一种封装结构2，其包括：一介电层21、一线路层22、多个电子组件27、封装材28以及一封装基板29。
所述的介电层21具有相对的第一表面21a与第二表面21b。
所述的线路层22形成于该介电层21的第一表面21a上，且该线路层22形成有贯穿该介电层21的多个导电盲孔220。
所述的电子组件27设于该介电层21的第一表面21a上且电性连接该线路层22。
所述的封装材28形成于该线路层22与该介电层21的第一表面21a上并包覆该电子组件27。
所述的封装基板29设于该介电层21的第二表面21b上并电性连接该些导电盲孔220。
于一实施例中，该些导电盲孔220的端面221齐平该介电层21的第二表面21b。
于一实施例中，该电子组件27为主动组件、被动组件或其二者组合。
于一实施例中，该封装结构2还包括形成于该线路层22上的多个第一导电组件24，其用于结合该电子组件27。
于一实施例中，该封装结构2还包括一绝缘保护层23，其形成于该介电层21的第一表面21a与该线路层22上，且该绝缘保护层23外露部分该线路层22。
于一实施例中，该封装结构2还包括形成于该些导电盲孔220的端面221上的多个第二导电组件26，其用于结合该封装基板29。
于一实施例中，该封装结构2还包括一绝缘保护层25，其形成于该介电层21的第二表面21b上，且该绝缘保护层25外露该些导电盲孔220的端面221。
综上所述，本发明的封装结构及其制法，藉由介电层取代现有硅板体，并利用线路层作为电子组件与封装基板之间讯号传递的介质，所以无需制作现有导电硅穿孔，因而大幅降低制程难度及制作成本。
此外，该承载件为玻璃板，且以激光烧除方式移除该承载件，使该承载件不受损毁，所以可重复使用该承载件，以降低材料成本。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (14)

1.一种封装结构，其特征为，该结构包括：
一介电层，其具有相对的第一表面与第二表面；
线路层，其形成于该介电层的第一表面上，且该线路层形成有多个贯穿该介电层的导电盲孔；
至少一电子组件，其设于该介电层的第一表面上且电性连接该线路层；
封装材，其形成于该线路层与该介电层的第一表面上并包覆该电子组件；以及
封装基板，其设于该介电层的第二表面上并电性连接该些导电盲孔。
2.根据权利要求1所述的封装结构，其特征为，该些导电盲孔的端面与该介电层的第二表面齐平。
3.根据权利要求1所述的封装结构，其特征为，该电子组件为主动组件、被动组件或其二者组合。
4.根据权利要求1所述的封装结构，其特征为，该结构还包括形成于该线路层上的多个第一导电组件，用于结合该电子组件。
5.根据权利要求1所述的封装结构，其特征为，该结构还包括一绝缘保护层，其形成于该介电层的第一表面与该线路层上，且该绝缘保护层外露部分该线路层。
6.根据权利要求1所述的封装结构，其特征为，该结构还包括形成于该些导电盲孔的端面上的多个第二导电组件，用于结合该封装基板。
7.根据权利要求1所述的封装结构，其特征为，该结构还包括一绝缘保护层，其形成于该介电层的第二表面上，且该绝缘保护层外露该些导电盲孔的端面。
8.一种封装结构的制法，其特征为，该制法包括：
形成一介电层于一承载件上，其中，该介电层具有相对的第一表面与第二表面，并以该第二表面结合至该承载件上；
形成线路层于该介电层的第一表面上，其中，该线路层形成有多个位于该介电层中的导电盲孔，该些导电盲孔并连通该介电层的第二表面；
移除该承载件，使该些导电盲孔的端面外露于该介电层的第二表面；
设置至少一电子组件于该介电层的第一表面上，使该电子组件电性连接该线路层；
形成封装材于该线路层与该介电层的第一表面上，以令该封装材包覆该电子组件；以及
设置封装基板于该介电层的第二表面上，使该封装基板电性连接该些导电盲孔。
9.根据权利要求8所述的封装结构的制法，其特征为，该些导电盲孔的端面齐平该介电层的第二表面。
10.根据权利要求8所述的封装结构的制法，其特征为，该电子组件为主动组件、被动组件或其二者组合。
11.根据权利要求8所述的封装结构的制法，其特征为，该制法还包括形成多个第一导电组件于该线路层上，以供结合该电子组件于该些第一导电组件上。
12.根据权利要求8所述的封装结构的制法，其特征为，该制法还包括形成绝缘保护层于该介电层的第一表面与该线路层上，且令该绝缘保护层外露部分该线路层。
13.根据权利要求8所述的封装结构的制法，其特征为，该制法还包括形成第二导电组件于该些导电盲孔的端面上，以供结合该封装基板于该些第二导电组件上。
14.根据权利要求8所述的封装结构的制法，其特征为，该制法还包括形成绝缘保护层于该介电层的第二表面与该些导电盲孔的端面上，且令该绝缘保护层外露该些导电盲孔的端面。
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US20160163632A1 (en) 2016-06-09
US10403596B2 (en) 2019-09-03

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