TW200935579A - Stacked chip structure and fabrication method thereof - Google Patents

Stacked chip structure and fabrication method thereof Download PDF

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Publication number
TW200935579A
TW200935579A TW097104601A TW97104601A TW200935579A TW 200935579 A TW200935579 A TW 200935579A TW 097104601 A TW097104601 A TW 097104601A TW 97104601 A TW97104601 A TW 97104601A TW 200935579 A TW200935579 A TW 200935579A
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Taiwan
Prior art keywords
wafer
polymer layer
patterned
patterned polymer
pads
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Application number
TW097104601A
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Chinese (zh)
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TWI356485B (en
Inventor
Ying-Ching Shih
Shu-Ming Chang
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Ind Tech Res Inst
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Priority to TW097104601A priority Critical patent/TWI356485B/en
Priority to US12/198,072 priority patent/US7541217B1/en
Publication of TW200935579A publication Critical patent/TW200935579A/en
Application granted granted Critical
Publication of TWI356485B publication Critical patent/TWI356485B/en

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A fabrication method of stacked structure of chips is provided. Firstly, a first conductive layer is formed on the first surface of a wafer. Afterwards, a first patterned polymer layer and a second patterned polymer layer are formed on the first conductive layer and the second surface of the wafer respectively. Next, a second conductive layer is electroplated on the first conductive layer and is heated to form a plurality of solder bumps. After that, a plurality of the wafers is stacked on a structural substrate. A first patterned polymer layer on one first wafer of the wafers is coincidently connected to a second patterned polymer layer on one second wafer of the wafers. The solder bumps are blocked form flowing to other pads by the patterned polymer layer, so the patterned polymer layer is suitable for the stacked structure of chips connected by the fine pitch solder bumps. Besides, the processes of the invention is simplified.

Description

200935579 25390twf.doc/d 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體結構及其製作方法 ^有關於一種具有®案化高分子層的晶片堆疊結構及其 【先前技術】 在現今的資訊社會中’使用者均是追求高速度、高品 ® 質、多功能性的電子產品。就產品外觀而言，電子產 設計是朝向輕、薄、短、小的趨勢邁進。為了達到上述目 的，近來發展出一種晶片堆疊結構，晶片堆疊結構即是將 夕個晶片以堆疊的方式相接合並電性連接。因此，晶片堆 疊結構具有更快的傳輸速度、更短的傳輸路程以及更佳的 電氣特性，並進一步縮小晶片封裝結構的尺寸及面積，因 而使得晶片堆疊結構已經普遍應用於各種電子產品之中， 並成為未來的主流產品。 Q 如圖1所示，形成晶片堆疊結構的方法主要是在各晶 片10上相同位置製作微通孔(Via)12，並配合高深寬比的 電錢使導電材料20填入微通孔12中並在各個微通孔12 上配置錫球(solder bump)30，錫球30可與位於相對應的微 通孔12中的導電材料20電性連接。然後，在晶片1〇上配 置一黏著層40。之後，再將晶片1〇堆疊以使各晶片1〇可 藉由其所具有的黏著層40相接，並藉由錫球30與相鄰晶 片10的導電材料20相接’以達成晶片1〇之間的電性導 通。然後，再於晶片10之間填入封裝膠體50，以保護錫 25390twf.doc/d 200935579 球30。其中，將各晶片1〇的錫球3〇與相鄰晶片1〇的導 電材料2〇相接的方式，多半是藉由加熱各晶片的錫球3〇 以使各晶片10的錫球30軟化進而與相鄰晶片1〇的導電材 料20相接。 然而’封裝膠體50本身為不良導體，因此將使得晶片 10之間的散熱能力較差。此外，當以晶圓堆疊（未繪示） 的方式形成堆疊結構時’要將封裝膠體5〇填入晶圓之間的 〇 困難度相當高’進而使所填入的封裝膠體50與晶圓之間易 有孔隙存在。當空氣易存在於孔隙中時，堆疊結構易因受 熱而產生爆米花效應（P〇pC〇m Ef^ect)。另外，各晶片1 〇 的錫球30易因受熱而軟化，並外溢到相鄰的錫球3〇進而 發生短路的情形。而且，當晶片1〇上的錫球3〇排列朝向 微細間距（finepitch)化發展時’由於錫球3〇間的間距縮 短，進而使得錫球30於加熱的過程中更容易因外溢到相鄰 的錫球30而發生短路的情形。 【發明内容】 © 本發明關於一種晶片堆疊結構，其具有較佳的散熱能 力且適於以微細間距的銲料凸塊來接合晶片，且晶片之間 藉由高分子層接合可增強晶片之間的接合強度。 本發明關於一種晶片堆疊結構的製作方法，適於製作 以微細間距的銲料凸塊來接合晶片的晶片堆疊結構，且製 程步驟較為簡化。 為具體描述本發明之内容，在此提出一種晶片堆疊結 構的製作方法。首先，提供一晶圓。晶圓具有一第一表面、 25390twf.doc/d 200935579 相對於第一表面的一第二表面、多個位於第一表面的第一 接墊、多個位於第二表面的第二接墊以及多個貫通第—與 第二表面並與第一與第二接墊電性連接的導通結構。接 著，形成一第一導電層於晶圓的第一表面上，而且第一導 電層覆盍第一接墊。然後，形成一第一圖案化高分子層於 第一 ^電層上，而且第一圖案化兩分子層具有多個第—開 口以暴露出第一導電層。之後，形成一第二圖案化高分子 ❹ 層於第二表面上，第二圖案化高分子層具有多個第二開 口，以暴露出第二接墊。接著，電鍍一第二導電層於第一 導電層上’且第二導電層位於第一開口中。然後，對第二 導電層進行加熱，以形成多個銲料凸塊於第一接墊上以及 形成一圖案化第一導電層。圖案化第一導電層具有—第一 部分以及一與第一部份分離的第二部分，而第一部份位於 銲料凸塊與第一接墊之間，且第二部分位於第一圖案化高 分子層與晶圓之間。之後，將多個晶圓相堆疊於一基底結 構^，其中-第一晶圓藉由銲料凸塊與其中一第二晶圓的 第二接塾電性連接。並且，第一晶圓藉由位於其上的第一 圖案化高分子層與位於第二晶圓上的第二圖案化高分 對應連接。 在本發明之一實施例中，第二導電層的材質包括錫或 錫合金。 在本發明之一實施例中，其中形成第一圖案化高分子 層於第-導電層上的方法包括形成一第一高分子層於第一 導電層上，並對第一高分子層進行圖案化。 7 25390twf.doc/d 200935579 幻卜2發Γΐ—實施例中，其中對第—高分子層進行圖 案化的方法包括曝光顯影或微影蝕刻。 純ί本發明之—實施例中，當形成銲料凸塊之後，更包 ίΙΓ圖案化高分子層進行圖案化，以使第—圖案化高 刀曰具有多條第-溝槽，且每―第—溝槽與其中一第一 開口相通並延伸至晶圓邊緣。 〇200935579 25390twf.doc/d IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure and a method of fabricating the same, and relates to a wafer stack structure having a polymer layer and a [previously Technology] In today's information society, 'users are electronic products that pursue high speed, high quality, and versatility. In terms of product appearance, electronic product design is moving toward a trend of light, thin, short and small. In order to achieve the above object, a wafer stack structure has recently been developed in which wafer stacks are joined and electrically connected in a stacked manner. Therefore, the wafer stack structure has a faster transfer speed, a shorter transfer path, and better electrical characteristics, and further reduces the size and area of the chip package structure, thereby making the wafer stack structure widely used in various electronic products. And become the mainstream product of the future. Q, as shown in FIG. 1, the method of forming a wafer stack structure is mainly to form a micro via hole (Via) 12 at the same position on each wafer 10, and fill the micro via hole 12 with the high aspect ratio electric money. Solder bumps 30 are disposed on the respective micro vias 12, and the solder balls 30 are electrically connected to the conductive material 20 located in the corresponding micro vias 12. Then, an adhesive layer 40 is disposed on the wafer 1A. Thereafter, the wafers are stacked one on another so that the wafers 1 can be connected by the adhesive layer 40 they have, and the solder balls 30 are connected to the conductive material 20 of the adjacent wafer 10 to achieve the wafer 1〇. Electrical continuity between. Then, an encapsulant 50 is filled between the wafers 10 to protect the tin 25390 twf.doc/d 200935579 balls 30. Wherein, the solder ball 3〇 of each wafer is connected to the conductive material 2〇 of the adjacent wafer 1〇, and the solder ball 3 of each wafer 10 is softened by heating the solder balls 3 of each wafer. Further, it is in contact with the conductive material 20 of the adjacent wafer. However, the encapsulant 50 itself is a poor conductor and therefore will result in poor heat dissipation between the wafers 10. In addition, when the stacked structure is formed by a wafer stack (not shown), it is difficult to fill the encapsulant 5 晶圆 between the wafers, and the encapsulating colloid 50 and the wafer are filled. There are easy to exist between the pores. When air is easily present in the pores, the stacked structure is susceptible to the popcorn effect (P〇pC〇m Ef^ect) due to heat. Further, the solder balls 30 of each of the wafers 1 are easily softened by heat and overflow to the adjacent solder balls 3 to cause a short circuit. Moreover, when the arrangement of the solder balls on the wafer 1 is toward the fine pitch, the pitch between the solder balls 3 is shortened, so that the solder balls 30 are more likely to overflow into the adjacent process during heating. The case where the solder ball 30 is short-circuited. SUMMARY OF THE INVENTION The present invention relates to a wafer stack structure having better heat dissipation capability and suitable for bonding wafers with fine pitch solder bumps, and bonding between wafers by polymer layer bonding can be enhanced between wafers. Bonding strength. The present invention relates to a method of fabricating a wafer stack structure suitable for fabricating a wafer stack structure in which solder bumps are finely pitched to bond wafers, and the process steps are simplified. To specifically describe the contents of the present invention, a method of fabricating a wafer stack structure is presented herein. First, a wafer is provided. The wafer has a first surface, a second surface of 25390 twf.doc/d 200935579 relative to the first surface, a plurality of first pads on the first surface, a plurality of second pads on the second surface, and a plurality of And a conductive structure that penetrates the first surface and the second surface and is electrically connected to the first and second pads. Then, a first conductive layer is formed on the first surface of the wafer, and the first conductive layer covers the first pad. Then, a first patterned polymer layer is formed on the first electrical layer, and the first patterned two molecular layer has a plurality of first openings to expose the first conductive layer. Thereafter, a second patterned polymer layer is formed on the second surface, and the second patterned polymer layer has a plurality of second openings to expose the second pads. Next, a second conductive layer is electroplated on the first conductive layer' and the second conductive layer is located in the first opening. Then, the second conductive layer is heated to form a plurality of solder bumps on the first pads and to form a patterned first conductive layer. The patterned first conductive layer has a first portion and a second portion separated from the first portion, and the first portion is located between the solder bump and the first pad, and the second portion is located at the first patterned high Between the molecular layer and the wafer. Thereafter, a plurality of wafer phases are stacked on a substrate structure, wherein the first wafer is electrically connected to the second interface of one of the second wafers by solder bumps. And, the first wafer is correspondingly connected to the second patterned high score layer located on the second wafer by the first patterned polymer layer located thereon. In an embodiment of the invention, the material of the second conductive layer comprises tin or a tin alloy. In an embodiment of the invention, the method for forming the first patterned polymer layer on the first conductive layer comprises forming a first polymer layer on the first conductive layer and patterning the first polymer layer Chemical. 7 25390 twf.doc/d 200935579 幻卜二发Γΐ—In the embodiment, the method of patterning the first polymer layer includes exposure development or lithography etching. In the embodiment of the present invention, after the solder bump is formed, the patterned polymer layer is patterned to have a plurality of first-grooves, and each - the trench communicates with one of the first openings and extends to the edge of the wafer. 〇

f本發明之—實施例中，對第—圖案化高分子層進行 圖案化的方法包括微影蝕刻或曝光顯影。 在本發明之—實施例中，更包括對第二醜化高分子 ς仃圖案化’以使第二圖案化高分子層更具有多條第二 且每帛一溝槽與其中一第二開口相通並延伸至晶 圓邊緣。 在本刺之-實_中，對第二導電層進行加 法為迴銲。 2具體描述本發明之内容，在此提出一種晶片堆疊結 ，、包括-基底結構以及多個堆疊於基底結構上的晶 二其中’每-晶片具有—第_表面以及相對於第一表面 ^第二表面。而且’每—晶片包括多個第—接墊、多個 古二接墊、多個導通結構、多個銲料凸塊、—第一圖案化 Ζ子層、—第二圖案化高分子層以及一圖案化導電層。 八，第—接墊位於第一表面上，且第二接墊位於第二表 2。導通結構貫通第—與第二表面並與第—與第二接塾 二L連接。料凸塊分別配置於第-雜上。-第-圖案 化馬分子相及-第二圖案化高分子紗麻置於晶片的 200935579 25390twf.doc/d Ο 魯 第:表面與第二表面H第—圖案化高分子層具有多 個第一開口，且第-開口暴露出鮮料 分::具有多個第二開口，且第二開口暴露出第= =導電層具有—第—部分以及—與第—部份分離的 ^一。P刀，而第一部份位於銲料凸塊與第一接墊之間，且 =-部分位於第—圖案化高分子層與晶片之間。A中一第 :晶片藉由銲料凸塊與其中—第二晶片的第二接墊電性連 笛且第-晶片藉由位於其上的第i案化高分子層與位 、弟一晶片上的第二圖案化高分子層對應連接。 合金在本發明之—實關巾，銲料凸塊的材質包括錫或錫 之—實施财，第—酵化高分子層具有多 =二且每一第一溝槽與其中-第-開口相通並延 停第在2明之—實關巾，第二_化高分子層具有多 條第一溝槽，且每一第二溝槽與其中一第 伸至晶片邊緣。 開口相通並延 在本發明之一實施例中，基底結構具有一第二==表面的第三接塾，且第二= 以 位於第三接墊與第二晶片之間的銲料凸塊而電性迷 综上所述，本發明保留晶圓上的圖案化高分子層以 =疊時可藉由晶κ上的圖案化高分子層對應連接 ，圖案化高分子層可增加晶圓之間的接合強度，進而^ 接 晶圓 9 25390twf.doc/d 200935579 加強晶片堆疊結構的可靠度。並且，不需如習知技術-般 而夕道步驟以移除圖案化高分子層。此夕卜將晶圓接合 時圖案化咼刀子層可阻擋銲料凸塊溢至其他接墊 。因此’ 本發明可適用於藉由微細間距的銲料凸塊接合的晶片堆疊 結構。 *為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例，並配合所關式，作詳細說明如 下。 【實施方式】 圖2A〜2H為本發明一實施例之晶片堆疊結構的製作 流程剖面圖，而圖3為圖2F的上視圖，且圖2F為圖3中 沿I-Ι線段的剖面圖。 首先，請參照圖2A，提供一晶圓210。晶圓210具有 一第一表面212、相對於第一表面212的一第二表面214、 多個位於第一表面212的第一接墊216、多個位於第二表 面214的第二接墊218以及多個貫通第一表面212與第二 表面214並與第一接墊216及第二接墊218電性連接的導 通結構c。接著，請參照圖2B，形成一第一導電層22〇於 晶圓210的第一表面212上，而且第一導電層220覆蓋第 一接墊216。 然後，請參照圖2C，形成一第一圖案化高分子層230 於第一導電層220上，而且第一圖案化高分子層23〇具有 多個第一開口 232以暴露出第一導電層220。並且，形成 一第二圖案化高分子層240於第二表面214上，第二圖案 200935579 25390twf.doc/d =高分子層240具有多個第二開口 242以暴露出第二接塾 。此外’形成第-圖案化高分子層23G於第 220上的方法例如形成一第一高分子層（未纷示）於二 導電層220上’並對第一高分子層進行圖案化。另外 =第-高分子層進行圖案化的方法包括曝光顯影或微^ 接著，請參照圖2D’電鍍一第二導電層25〇於 ❹ 電層220上，且第二導電層25〇位於第一開口 232中。 於本發明是利用電鍍的方式形成第二導電層250,因此 本發明可控制第二導電層25〇的量（或是厚度），故 免之後形成的銲料凸塊過大。也因此，可避免之後 疊如，銲料凸塊溢至晶圓上的其他接塾（未繪示）而 短路。此外，第二導電層25〇的材質例如是錫、錫合金 是其他適合的導電材料。 4 ,然後，請參照圖2E，對第二導電層250進行加熱，以 形成多個銲料凸塊S於第一接墊m上以及形成—圖案化 第一導電層220a。圖案化第一導電層22〇a具有—第一部 分222a以及一與第一部份222a分離的第二部分22乜，而 第一部份222a位於銲料凸塊s與第一接墊216之間，且第 二部分224a位於第一圖案化高分子層23〇與晶圓21〇之 間。而且，第二部分224a可有助於晶圓210散熱。 具體而言，當形成銲料凸塊s的同時也會使第一導電 層220圖案化，進而形成一具有相互分離的第一部分 與第二部分224a的圖案化第一導電層220a。因此，本發 11 25390twf.doc/d 200935579 月不而另外再移除第二部分224a。此外，對第二導電層25〇 進行加熱的方法例如迴銲。銲料凸塊s的材質例如是錫、 錫合金或是其他適合的導電材料。 此外，請同時參照圖2F與圖3,晶圓210可由多條預 切割線L劃分出多個晶片區域3〇〇。於本實施例中當形 成銲料凸塊s之後，還可對第一圖案化高分子層23〇 ^ 圖案化，以使第-圖案化高分子層MO具有多條第一溝槽 ❹ T1。而且，每一第一溝槽T1與其中一第一開口 232相^ 並延伸至晶圓210邊緣。此外，對第一圖案化高分子層23〇 進行圖案化的方法包括微影蝕刻或曝光顯影❶然而，前述 步驟僅為舉例說明’並非用以限定本發明。也就是說，前 述步驟可以選擇性地進行，亦即也可以不形成第一 II。 另外，請再次參照圖2F與圖3，於本實施例中，還可 對第二@案化高分子層進行随化，以使帛二圖案化 高分子層240具有多條第二溝槽T2。而且，每一第二溝槽 T2與j中一第二開口 242相通並延伸至晶圓21〇邊緣。然 ，’刖述步驟僅為舉例說明，並非用以限定本發明。也就 是說，前述步驟可以選擇性地進行，亦即也可以不形成第 一溝槽T2。並且，請參照圖2E，當不形成第一溝槽T1與 第一溝槽T2時，只需在真空的環境下即可接合晶片21〇。 承上所述，本發明之圖案化高分子層230、240所具有 的多條溝槽II、T2可使溝槽T1、T2内的氣體與大氣環境 相通，因而於接合晶圓210時不會將空氣埋藏在晶圓21〇 12 25390twf. doc/d ❹In the embodiment of the present invention, the method of patterning the first patterned polymer layer includes photolithography or exposure development. In an embodiment of the invention, the method further includes: patterning the second smear polymer ' to make the second patterned polymer layer further have a plurality of second and each groove is connected to one of the second openings And extend to the edge of the wafer. In the present, the second conductive layer is added as a reflow. 2 DETAILED DESCRIPTION OF THE INVENTION In the context of the present invention, a wafer stack junction is provided, comprising a substrate structure and a plurality of crystals stacked on the substrate structure, wherein each wafer has a surface and a surface relative to the first surface Two surfaces. Moreover, each of the wafers includes a plurality of first pads, a plurality of ancient pads, a plurality of conductive structures, a plurality of solder bumps, a first patterned germanium layer, a second patterned polymer layer, and a The conductive layer is patterned. Eight, the first pad is located on the first surface, and the second pad is located in the second table 2. The conductive structure is connected to the first and second surfaces and to the first and second interfaces. The material bumps are respectively disposed on the first impurity. - a first-patterned horse molecular phase and - a second patterned polymer gauze placed on the wafer 200935579 25390twf.doc / d : Lu: the surface and the second surface H - the patterned polymer layer has a plurality of first The opening, and the first opening exposes a fresh material: having a plurality of second openings, and the second opening exposing the == conductive layer has a - portion and - separated from the first portion. The P blade has a first portion between the solder bump and the first pad, and a =- portion between the first patterned polymer layer and the wafer. A: a wafer is electrically connected to the wafer by a solder bump and a second pad of the second wafer, and the first wafer is over the ith polymer layer and the wafer on the wafer The second patterned polymer layer is correspondingly connected. The alloy is in the present invention, the material of the solder bump includes tin or tin - the implementation of the first - fermented polymer layer has more = two and each of the first trenches is in communication with the - first opening The second _ chemical polymer layer has a plurality of first grooves, and each of the second grooves and one of the second grooves extends to the edge of the wafer. The opening is in communication and extends in an embodiment of the invention, the base structure has a third interface of a second == surface, and the second = electrically connected to the solder bump between the third pad and the second wafer In summary, the present invention preserves the patterned polymer layer on the wafer to be connected by the patterned polymer layer on the crystal κ when the stack is stacked, and the patterned polymer layer can increase the between the wafers. Bonding strength, and thus the wafer 9 25390twf.doc/d 200935579 to enhance the reliability of the wafer stack structure. Moreover, it is not necessary to remove the patterned polymer layer as in the prior art. In this case, the patterning of the knives layer when the wafer is bonded can block the solder bumps from overflowing to other pads. Therefore, the present invention is applicable to a wafer stack structure joined by fine pitch solder bumps. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. 2A to 2H are cross-sectional views showing a manufacturing process of a wafer stack structure according to an embodiment of the present invention, and Fig. 3 is a top view of Fig. 2F, and Fig. 2F is a cross-sectional view taken along line I-Ι in Fig. 3. First, referring to FIG. 2A, a wafer 210 is provided. The wafer 210 has a first surface 212 , a second surface 214 opposite to the first surface 212 , a plurality of first pads 216 on the first surface 212 , and a plurality of second pads 218 on the second surface 214 . And a plurality of conductive structures c penetrating the first surface 212 and the second surface 214 and electrically connected to the first pads 216 and the second pads 218. Next, referring to FIG. 2B, a first conductive layer 22 is formed on the first surface 212 of the wafer 210, and the first conductive layer 220 covers the first pad 216. Then, referring to FIG. 2C, a first patterned polymer layer 230 is formed on the first conductive layer 220, and the first patterned polymer layer 23 has a plurality of first openings 232 to expose the first conductive layer 220. . Moreover, a second patterned polymer layer 240 is formed on the second surface 214, and the second pattern 200935579 25390 twf.doc/d = the polymer layer 240 has a plurality of second openings 242 to expose the second interface. Further, the method of forming the first patterned polymer layer 23G on the 220th layer forms, for example, a first polymer layer (not shown) on the second conductive layer 220, and patterns the first polymer layer. In addition, the method of patterning the first polymer layer includes exposure development or microlithography. Referring to FIG. 2D, a second conductive layer 25 is plated on the tantalum layer 220, and the second conductive layer 25 is located at the first layer. In the opening 232. In the present invention, the second conductive layer 250 is formed by electroplating, so that the present invention can control the amount (or thickness) of the second conductive layer 25, so that the solder bumps formed later are excessively large. Therefore, it is possible to avoid a short circuit after the solder bumps overflow to other interfaces (not shown) on the wafer. Further, the material of the second conductive layer 25A is, for example, tin or a tin alloy, which is another suitable conductive material. 4, then, referring to FIG. 2E, the second conductive layer 250 is heated to form a plurality of solder bumps S on the first pads m and to form a patterned first conductive layer 220a. The patterned first conductive layer 22A has a first portion 222a and a second portion 22A separated from the first portion 222a, and the first portion 222a is located between the solder bump s and the first pad 216. The second portion 224a is located between the first patterned polymer layer 23A and the wafer 21A. Moreover, the second portion 224a can facilitate heat dissipation of the wafer 210. Specifically, the first conductive layer 220 is also patterned while forming the solder bumps s, thereby forming a patterned first conductive layer 220a having the first and second portions 224a separated from each other. Therefore, the second part 224a is not removed in addition to the present invention. Further, a method of heating the second conductive layer 25A is, for example, reflow soldering. The material of the solder bump s is, for example, tin, tin alloy or other suitable conductive material. In addition, referring to FIG. 2F and FIG. 3 simultaneously, the wafer 210 may be divided into a plurality of wafer regions 3 by a plurality of pre-cut lines L. After the solder bumps s are formed in this embodiment, the first patterned polymer layer 23 can be patterned so that the first patterned polymer layer MO has a plurality of first trenches ❹ T1. Moreover, each of the first trenches T1 and one of the first openings 232 extend to the edge of the wafer 210. Further, the method of patterning the first patterned polymer layer 23A includes lithography etching or exposure development. However, the foregoing steps are merely illustrative and are not intended to limit the present invention. That is to say, the foregoing steps may be selectively performed, that is, the first II may not be formed. In addition, referring to FIG. 2F and FIG. 3 again, in the embodiment, the second @案化polymer layer may be subjected to singulation so that the second patterned polymer layer 240 has a plurality of second trenches T2. . Moreover, each of the second trenches T2 communicates with a second opening 242 of j and extends to the edge of the wafer 21〇. However, the detailed description is merely illustrative and is not intended to limit the invention. That is to say, the foregoing steps can be selectively performed, that is, the first trench T2 may not be formed. Further, referring to Fig. 2E, when the first trench T1 and the first trench T2 are not formed, the wafer 21 can be bonded only in a vacuum environment. As described above, the plurality of trenches II and T2 of the patterned polymer layers 230 and 240 of the present invention allow the gas in the trenches T1 and T2 to communicate with the atmosphere, and thus do not adhere to the wafer 210. Buried air on the wafer 21〇12 25390twf. doc/d ❹

200935579 堆f吉構内，也可叫錢環境下接合晶® 210，而 不而，習知技術-般需在真空的環境下進行接合，故 降低W程的成本。當然，本發明也可以 ==明既可在真空中接合晶圓21〇亦可在= 兄下接σ日日圓210，故本發明對於晶圓21〇的接合製程 環境容忍度較高。此外，溝槽T1、Τ2還可以有助於將Β曰 圓210的導電結構（即為銲料凸塊8、第—接墊216與^曰 -接墊218)相接合時或者是之後形成的晶片堆疊結構（未 緣示）於運作時所產生的熱散至大氣環境t。此外，溝柙 T卜T2可暴露出局部的第二部分2族，因此溝槽η 可有助於晶圓210散熱。 之後，請參照圖2G’將多個晶圓21〇相堆疊於一基底 結構+260上，其中一第一晶圓21〇a藉由銲料凸塊si與其 中一第二晶圓21〇b的第二接墊218b電性連接。並且，第 一晶圓210a藉由位於其上的第一圖案化高分子層23〇&與 位於第二晶圓210b上的第二圖案化高分子層24%對應^ 接。圖2G僅繪示兩個晶圓21〇a、21〇b做為代表，但並非 用以限制本發明之晶圓210的數量。舉例來說，晶圓21〇 的數量可以是三個、四個、五個等多數個，而且這些晶圓 210可相互堆疊於一基底結構26〇上。 此外，於本實施例中，將多個晶圓210相堆疊於基底 結構260上的方式可以是先將多個晶圓21〇相互堆疊，再 將這些晶片210翻覆並配置於基底結構26〇上。舉例來說， 先將其中一第一晶圓210b配置於其中一第一晶圓210a 13 200935579 25390tw£doc/d 上，且第一晶圓210b的第二接墊218b可藉由銲料凸塊si 而與第一晶圓210a的第一接墊216電性連接。並且，將位 於第二晶圓210b上的第二圖案化高分子層24%與位於第 一晶圓210a上的第一圖案化高分子層23〇&對應連接。然 後再將第一晶圓210a與第二晶圓210b所構成的接合結構 (未繒'示）翻覆並配置於基底結構260上。 另外，於本實施例中，將多個晶圓21〇相堆疊於基底 Ο 結構260上的方式還可以是將多個晶圓210依序翻覆並相 互堆豐於基底結構260上。舉例來說，可以是先將其中一 第二晶圓210b翻覆並配置於基底結構260上，再將第一晶 圓210a翻覆並配置於第二晶圓2i〇b上。其中，第一晶圓 210a的第一接墊216可藉由銲料凸塊S1而與第二晶圓 210b的第二接墊218b電性連接。並且，第一晶圓21加可 藉由位於其上的第一圖案化高分子層23〇a與位於第二晶 圓210b上的第二圖案化高分子層24〇b對應連接。 ❺基於上述，本發明保留第一圖案化高分子層23〇a與第 二圖案化高分子層240b，以使第一晶圓210a可藉由位於 其上的第一圖案化高分子層23〇a與位於第二晶圓210b上 的第一圖案化高分子層240b對應連接。因此，本發明不需 額外多一道步驟以去除第一圖案化高分子層23〇a與第二 圖案化高分子層240b。另外，圖案化高分子層230a、240b 可增加晶圓210a、210b之間的接合強度，進而可加強之後 形成的晶片堆疊結構的可靠度。此外，將第一晶圓210a 與第二晶圓210b接合時，第一圖案化高分子層230a與第 200935579 25390tw£doc/d 二圖案化高分子層240b可阻擋銲料凸塊81溢至其他接墊 (未繪示）。因此，本發明可適用於藉由微細間距的銲料 凸塊接合的晶片堆疊結構。 *如圖2G所示，於本實施例中，基底結構26〇可具有 一第二表面262以及多個位於第三表面262的第三接墊 264。第二接墊264與第二晶圓2i〇b可藉由位於第三接墊 264與第二晶圓210b之間的銲料凸塊幻而電性連接。麸 ❹ 後，請參照圖纽，可沿著預切割線L切割晶B]21()a、21i 以及基底結構260以形成多個晶片堆疊結構4〇〇(圖2H僅 繪示-個晶片堆疊結構姻代表，但並非用以限林發明 之晶片堆疊結構的數量）。晶片堆疊結構4〇〇可由第一晶200935579 In the stack, it is also possible to join the Crystal® 210 in a money environment. However, conventional techniques generally need to be joined in a vacuum environment, thus reducing the cost of the W process. Of course, the present invention can also be used to bond the wafer 21 in a vacuum or to connect the sigma yen 210 to the next brother. Therefore, the present invention has a high tolerance to the bonding process of the wafer 21 环境. In addition, the trenches T1, Τ2 may also contribute to the bonding of the conductive structures of the dome 210 (ie, the solder bumps 8, the pads 216 and the pads 218) or the wafers formed later. The heat generated by the stacked structure (not shown) is transferred to the atmospheric environment t. In addition, the trench Tb T2 may expose a local second portion 2 group, and thus the trench η may contribute to heat dissipation of the wafer 210. Then, please refer to FIG. 2G' to stack a plurality of wafers 21 on a base structure +260, wherein a first wafer 21A is soldered by a solder bump si and one of the second wafers 21b The second pads 218b are electrically connected. Further, the first wafer 210a is 24% corresponding to the second patterned polymer layer located on the second wafer 210b by the first patterned polymer layer 23〇& 2G shows only two wafers 21A, 21B as representative, but is not intended to limit the number of wafers 210 of the present invention. For example, the number of wafers 21A may be three, four, five, etc., and the wafers 210 may be stacked on each other on a substrate structure 26A. In addition, in the embodiment, the plurality of wafers 210 are stacked on the base structure 260 by stacking the plurality of wafers 21 to each other, and then flipping and arranging the wafers 210 on the base structure 26 . For example, one of the first wafers 210b is disposed on one of the first wafers 210a 13 200935579 25390 tw doc/d, and the second pads 218b of the first wafer 210b can be soldered by the solder bumps si The first pad 216 of the first wafer 210a is electrically connected. Further, the second patterned polymer layer 24% on the second wafer 210b is connected to the first patterned polymer layer 23〇& located on the first wafer 210a. Then, the bonding structure (not shown) of the first wafer 210a and the second wafer 210b is overturned and placed on the base structure 260. In addition, in the embodiment, the plurality of wafers 21 are stacked on the substrate structure 260 in a manner that the plurality of wafers 210 are sequentially flipped over and stacked on the substrate structure 260. For example, one of the second wafers 210b may be overturned and disposed on the base structure 260, and the first wafer 210a may be overturned and disposed on the second wafer 2i〇b. The first pad 216 of the first wafer 210a can be electrically connected to the second pad 218b of the second wafer 210b by the solder bump S1. Further, the first wafer 21 may be connected to the second patterned polymer layer 24〇b located on the second wafer 210b by the first patterned polymer layer 23〇a located thereon. ❺ Based on the above, the present invention retains the first patterned polymer layer 23〇a and the second patterned polymer layer 240b such that the first wafer 210a can pass through the first patterned polymer layer 23 located thereon. a is correspondingly connected to the first patterned polymer layer 240b on the second wafer 210b. Therefore, the present invention does not require an extra step to remove the first patterned polymer layer 23a and the second patterned polymer layer 240b. In addition, the patterned polymer layers 230a, 240b can increase the bonding strength between the wafers 210a, 210b, thereby enhancing the reliability of the wafer stack structure formed thereafter. In addition, when the first wafer 210a and the second wafer 210b are bonded, the first patterned polymer layer 230a and the second patterned polymer layer 240b can block the solder bumps 81 from overflowing to other interfaces. Pad (not shown). Therefore, the present invention is applicable to a wafer stack structure bonded by fine pitch solder bumps. * As shown in FIG. 2G, in the present embodiment, the base structure 26A may have a second surface 262 and a plurality of third pads 264 on the third surface 262. The second pads 264 and the second wafers 2i〇b are electrically connected by solder bumps located between the third pads 264 and the second wafers 210b. After the bran, please refer to the figure, the crystals B] 21 () a, 21i and the base structure 260 can be cut along the pre-cut line L to form a plurality of wafer stack structures 4 (only one wafer stack is shown in FIG. 2H). The structure is represented by the marriage, but it is not used to limit the number of wafer stack structures invented by the forest). The wafer stack structure 4 can be made of the first crystal

综上所述’本發明保留晶圓上的圖案化高分子層以使 晶圓堆疊時可藉由晶圓上_案化高分子層對應連接。因 此•’太發明；啻雜从夂_、笔..In summary, the present invention preserves the patterned polymer layer on the wafer so that the wafer can be stacked by the on-wafer polymer layer. Therefore, 'too invented; noisy from 夂_, pen..

發明可適驗藉由微細間距的銲料凸塊接合的黑只 的銲料凸塊接合的黑Κ堆疊結The invention is capable of embedding a black solder bump bonded black ridge stack junction bonded by fine pitch solder bumps

15 25390twf.doc/d 200935579 將工^埋藏在晶圓堆疊結構内，也因此可以在大氣環境下 接°曰曰圓’而不需如習知技術一般需在真空的環境下進行 接合，故而可降低製程的成本，當然本發明也可以在真空 中進打接合。此外，溝槽還可以有助於將晶圓的導電結構 相接合時或者是晶片堆疊結構於運作時所產生的 氣環境中。 此外，本發明是利用電鍍的方式形成第二導電層。因 ® 此，本發明可控制第二導電層的量（或是厚度），故可避 ^後形成轉料凸塊過大。也因此，可避免之後晶圓堆 豐時’銲料凸塊溢至其他接塾（未緣示）而造成短路。 —另外，本發明之晶片堆疊結構的製作是對第二導電層 進行加,、、、以形成多個銲'料凸塊於第一接墊上以及形成一 圖案化第導電層。具體而言，當形成鮮料凸塊的同時也 ，使第-導電層圖案化，進而形成—具有相互分離的第一 ，分與第二部分的圖案化第—導電層。因此，本發明不需 多一道步驟以移除第二部分的圖案化第一導電層。另外， 第二部分可有助於晶圓散熱。 雖j本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬領域中具有通常知識者，在不脫離本發 日月之精神和範圍内’當可作些許之更動與潤飾，因此本發 明之保護範圍當視後附之巾請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知—種堆疊式晶片堆疊結構的剖面圖。 圖2A〜2H為本發明一實施例之晶片堆疊結構的製作 16 200935579 25390twf.doc/d 流程剖面圖。 圖3為圖2F的上視圖，且圖2F為圖3中沿I-Γ線段 的剖面圖。 【主要元件符號說明】 10 .晶片 12 :微通孔 20 :導電材料 30 :錫球 ® 40:黏著層 50 :封裝膠體 210 :晶圓 210a :第一晶圓 210a’：第一晶片 210b :第二晶圓 210b’ ：第二晶片 212 :第一表面 ❹ 214 :第二表面 216 :第一接墊 218、218b :第二接墊 220 :第一導電層 220a :圖案化第一導電層 222a :第一部分 224a :第二部分 230、230a:第一圖案化高分子層 17 25390twf.doc/d 200935579 232 :第一開口 240、240b :第二圖案化高分子層 242 :第二開口 250 :第二導電層 260、260’ ：基底結構 262 :第三表面 264 :第三接墊 300 :晶片區域 400 :晶片堆疊結構 C:導通結構 L:預切割線 S、SI、S2 :銲料凸塊 T1 :第一溝槽 T2 :第二溝槽15 25390twf.doc/d 200935579 burying the work in the stack structure of the wafer, so that it can be connected to the atmosphere in the atmosphere, without the need to join in a vacuum environment as in the conventional technology. The cost of the process is reduced, and of course the invention can also be joined in a vacuum. In addition, the trenches may also assist in bonding the conductive structures of the wafer or in the gaseous environment created by the wafer stack structure during operation. Further, the present invention forms a second conductive layer by means of electroplating. Because of this, the present invention can control the amount (or thickness) of the second conductive layer, so that the formation of the transfer bump is excessive. Therefore, it is possible to avoid a short circuit caused by the solder bump overflowing to other interfaces (not shown) after the wafer is accumulated. In addition, the wafer stack structure of the present invention is fabricated by applying a second conductive layer to form a plurality of solder bumps on the first pads and forming a patterned conductive layer. Specifically, while the fresh bumps are formed, the first conductive layer is patterned, thereby forming a patterned first conductive layer having the first and second portions separated from each other. Therefore, the present invention does not require a further step to remove the second portion of the patterned first conductive layer. In addition, the second part can help the wafer to dissipate heat. The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and any person having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a conventional stacked wafer stack structure. 2A to 2H are diagrams showing the fabrication of a wafer stack structure according to an embodiment of the invention. 16 200935579 25390twf.doc/d. Figure 3 is a top view of Figure 2F, and Figure 2F is a cross-sectional view along line I-Γ of Figure 3. [Major component symbol description] 10. Wafer 12: micro via 20: conductive material 30: solder ball 40: adhesive layer 50: encapsulant 210: wafer 210a: first wafer 210a': first wafer 210b: Two wafers 210b': second wafer 212: first surface 214 214: second surface 216: first pads 218, 218b: second pads 220: first conductive layer 220a: patterned first conductive layer 222a: First portion 224a: second portion 230, 230a: first patterned polymer layer 17 25390twf.doc/d 200935579 232: first opening 240, 240b: second patterned polymer layer 242: second opening 250: second Conductive layer 260, 260': base structure 262: third surface 264: third pad 300: wafer area 400: wafer stack structure C: conductive structure L: pre-cut line S, SI, S2: solder bump T1: a trench T2: a second trench

1818

Claims (1)

25390twf.doc/d 200935579 十、申請專利範圍： 1.一種晶片堆疊結構的製作方法，包括： 提供一晶圓，該晶圓具有一第一表面、相對於該第〆 表面的一第二表面、多個位於該第一表面的第一接墊、多 個位於第二表面的第二接墊以及多個貫通該第一與第二表 面並與該些第一與第二接墊電性連接的導通結構； 形成一第一導電層於該晶圓的該第一表面上，I覆蓋 ❹ 該些第一接墊； 形成一第一圖案化高分子層於該第一導電層上，其中 該第一圖案化高分子層具有多個第一開口，以暴露出該第 一導電層； 开>成一第二圖案化高分子層於該第二表面上，該第二 圖案化高分子層具有多個第二開口，以暴露出該些第二接 墊； — 電鍍一第二導電層於該第一導電層上，且位於該些第 一開口中； ❹ 對該第一導電層進行加熱，以形成多個銲料凸塊於該 二第接墊上以及形成一圖案化第一導電層，其中該圖案 化第一導電層具有一第一部分以及一與第一部份分離的第 二部分，而該第一部份位於該些銲料凸塊與該第一接墊之 間，且該第二部分位於該第一圖案化高分子層盥該晶圓之 間； ’、 將多個該晶圓相堆疊於一基底結構上，其中一第一晶 圓藉由該些銲料凸塊與其中一第二晶圓的該些第二接墊電 19 25390twf.doc/d25390twf.doc/d 200935579 X. Patent Application Range: 1. A method for fabricating a wafer stack structure, comprising: providing a wafer having a first surface, a second surface opposite to the second surface, a plurality of first pads on the first surface, a plurality of second pads on the second surface, and a plurality of first and second surfaces extending through the first and second surfaces and electrically connected to the first and second pads a first conductive layer is formed on the first surface of the wafer, and I covers the first pads; forming a first patterned polymer layer on the first conductive layer, wherein the first conductive layer a patterned polymer layer has a plurality of first openings to expose the first conductive layer; and a second patterned polymer layer on the second surface, the second patterned polymer layer has a plurality of a second opening to expose the second pads; - plating a second conductive layer on the first conductive layer and located in the first openings; ❹ heating the first conductive layer to Forming a plurality of solder bumps on the second pad And forming a patterned first conductive layer, wherein the patterned first conductive layer has a first portion and a second portion separated from the first portion, and the first portion is located at the solder bumps Between the first pads, and the second portion is located between the first patterned polymer layer and the wafer; ', stacking a plurality of the wafers on a substrate structure, wherein a first wafer The second bumps of the solder bumps and one of the second wafers are electrically 19 25390 twf.doc/d 200935579 ，且該第—晶圓藉由位於其上的該第—圖案化高分 =層與位於該第二晶圓上的該第二圖案化高分子層對應連 接0 、2.如申料職圍第1項所述之晶片堆疊結構的製作 方法，其中該第二導電層的材質包括錫或錫合金。 、3.如申請專利範圍第1項所述之晶片堆疊結構的製作 方法’其中形成該第一圖案化高分子層於該第一導電層上 的方法包括形成一第一高分子層於該第一導電層上並對 該第一高分子層進行圖案化。 、4.如申請專利範圍第3項所述之晶片堆疊結構的製作 方法’其中對該第一高分子層進行圖案化的方法包括 顯影或微影蝕刻。 、5·如申請專利範圍第1項所述之晶片堆疊結構的製作 f法，當形成該些銲料凸塊之後，更包括對該第一圖案化 鬲分子層進行圖案化，以使該第一圖案化高分子層具有多 條第一溝槽，且每一第一溝槽與其中一第—開口^並延 伸至該晶圓邊緣。 、6.如申請專利範圍第5項所述之晶片堆疊結構的製作 =法’對該第一圖案化高分子層進行圖案化的方法包括微 影餘刻或曝光顯影。 、7·如申請專利範圍第1項所述之晶片堆疊結構的製作 ^法，當形成該些銲料凸塊之後，更包括對該第二圖案化 高分子層進行圖案化，以使該第二圖案化高分子層更^有 多條第二溝槽，且每一第二溝槽與其中一第二開口相通並 20 200935579 25390twf.doc/d 延伸至該晶圓邊緣。 8. 如申請專利範圍第1項所述之晶片堆疊結構的製作 方法’其中對該第二導電層進行加熱的方法為迴銲。 9. 一種晶片堆疊結構，包括一基底結構以及多個堆疊 於該基底結構上的晶片，其中每一該晶片具有一第—表面 以及相對於該第一表面的一第二表面，且每一該晶片包括： 多個第一接墊，位於該第一表面上； ❹ 多個第二接墊，位於該第二表面上； 多個導通結構’貫通該第一與第二表面並與該些第一 與第二接墊電性連接； 多個鮮料凸塊’分別配置於該些第一接墊上；200935579, and the first wafer is connected to the second patterned polymer layer located on the second wafer by the first patterned high score=layer located thereon, 0. The method for fabricating a wafer stack structure according to Item 1, wherein the material of the second conductive layer comprises tin or a tin alloy. 3. The method for fabricating a wafer stack structure according to claim 1, wherein the method of forming the first patterned polymer layer on the first conductive layer comprises forming a first polymer layer in the first The first polymer layer is patterned on a conductive layer. 4. The method of fabricating a wafer stack structure according to claim 3, wherein the method of patterning the first polymer layer comprises development or photolithography. 5. The method of fabricating a wafer stack structure according to claim 1, wherein after forming the solder bumps, further comprising patterning the first patterned germanium molecular layer to make the first The patterned polymer layer has a plurality of first trenches, and each of the first trenches and one of the first openings ^ extend to the edge of the wafer. 6. The fabrication of the wafer stack structure as described in claim 5, wherein the method of patterning the first patterned polymer layer comprises lithography or exposure development. 7. The method of fabricating a wafer stack structure according to claim 1, wherein after forming the solder bumps, further comprising patterning the second patterned polymer layer to make the second The patterned polymer layer further has a plurality of second trenches, and each of the second trenches is in communication with one of the second openings and extends to the edge of the wafer by 200935579 25390 twf.doc/d. 8. The method of fabricating a wafer stack structure according to claim 1, wherein the method of heating the second conductive layer is reflow. 9. A wafer stack structure comprising a substrate structure and a plurality of wafers stacked on the substrate structure, wherein each of the wafers has a first surface and a second surface opposite the first surface, and each of the The wafer includes: a plurality of first pads on the first surface; ❹ a plurality of second pads on the second surface; a plurality of conductive structures passing through the first and second surfaces and the plurality of One is electrically connected to the second pad; a plurality of fresh bumps are respectively disposed on the first pads; 一第一圖案化高分子層以及一第二圖案化高分子層， 分別配置於該晶片的該第一表面與該第二表面，其中該第 一圖案化高分子層具有多個第一開口，且該些第一開口暴 露出該些銲料凸塊，該第二圖案化高分子層具有多個第二 開口，且該些第二開口暴露出該些第二接墊； 、、一圖案化導電層，具有一第一部分以及一與該第一部 伤刀離的第—部分’而該第-部份位於該些銲料凸塊與該 第接塾之間，且該第一部分位於該第一圖案化高分子芦 與該晶片之間；以及 θ 其中一第一晶片藉由該些鮮料凸塊盥苴中— = 該些第二接塾電性連接，且該第—晶片藉由位 第n”"第—圖案化高分子層與位於該第二晶片上的該 弟一圖案化高分子層對應連接。 21 25390twf.doc/d 200935579 10·如申請專利範圍第9項所述之晶片堆燊雜構/、 該些銲料凸塊的材質包括錫或錫合金。 其中 11. 如申請專利範圍第9項所述之晶片堆磬結構，二溝 该第一圖案化高分子層具有多條第一溝槽，真每^第 槽與其中一第一開口相通並延伸至該晶片邊緣。，其 12. 如申請專利範圍第9項所述之晶片堆鮝結構镇ς 中該第二圖案化高分子層具有多條第二溝槽，真每^ ’ ❹ 溝槽與其中一第二開口相通並延伸至該晶片邊緣。，其中 13. 如申請專利範圍第9項所述之晶片堆燊結構’二 該基底結構具有一第三表面以及多個位於該第三表面的 三接墊，且該些第三接墊與該第二晶片藉由位於該些第三 接墊與該第二晶片之間的該些銲料凸塊而電性連接。a first patterned polymer layer and a second patterned polymer layer are respectively disposed on the first surface and the second surface of the wafer, wherein the first patterned polymer layer has a plurality of first openings, And the first openings expose the solder bumps, the second patterned polymer layer has a plurality of second openings, and the second openings expose the second pads; and a patterned conductive a layer having a first portion and a first portion that is apart from the first portion of the blade and the first portion is located between the solder bumps and the first land, and the first portion is located in the first pattern Between the polymer reed and the wafer; and θ one of the first wafers is electrically connected by the plurality of bumps = - the second junctions, and the first wafer is by the nth "The first patterned polymer layer is correspondingly connected to the patterned polymer layer on the second wafer. 21 25390 twf.doc/d 200935579 10) The wafer stack as described in claim 9 The structure of the solder bumps, the solder bumps include tin or tin 11. The wafer stacking structure according to claim 9, wherein the first patterned polymer layer has a plurality of first trenches, and each of the first slots is in communication with one of the first openings. The second patterned polymer layer has a plurality of second trenches, each of which is a trench of the wafer stack structure according to claim 9 of claim 9 And a wafer stack structure according to claim 9 of the invention, wherein the substrate structure has a third surface and a plurality of the third surface The three pads are electrically connected to the second wafer by the solder bumps between the third pads and the second wafer. 22twenty two
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