CN105493269B - 超微间距PoP无芯封装 - Google Patents

超微间距PoP无芯封装 Download PDF

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CN105493269B
CN105493269B CN201480047712.7A CN201480047712A CN105493269B CN 105493269 B CN105493269 B CN 105493269B CN 201480047712 A CN201480047712 A CN 201480047712A CN 105493269 B CN105493269 B CN 105493269B
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substrate
enhancement layer
top surface
layer
couple
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CN105493269A (zh
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徐润忠
翟军
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Apple Inc
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Abstract

本发明公开了一种PoP(层叠封装)的底部封装件，该底部封装件可形成有支承薄或无芯衬底的加强层。加强层可为衬底提供硬度和刚度以提高底部封装件的硬度和刚度以及提供衬底的更好处理。加强层可利用芯材料、层合层和金属层来形成。衬底可形成在加强层上。加强层可包括尺寸设定成容纳裸片的开口。裸片可在开口中耦接到衬底的暴露表面。可使用穿过加强层的金属填充的通路来将衬底耦接到顶部封装件。

Description

超微间距PoP无芯封装
背景技术
技术领域
本发明涉及半导体封装以及用于封装半导体器件的方法。更具体地，本发明涉及容纳有源和无源部件的PoP(层叠封装)的底部封装件。
相关领域的描述
随着在半导体工业中对更低成本、更高性能、增大的集成电路密度和增大的封装密度的要求持续，层叠封装(“PoP”)技术已变得越来越普及。随着对越来越小的封装的推动加强，裸片和封装件的集成(例如，“预堆叠”或片上系统(“SoC”)技术与存储器技术的集成)允许更薄的封装件。此类预堆叠已成为薄细间距PoP封装件的关键组成部分。
减小封装件的尺寸(例如PoP封装件中的顶部封装件(存储器封装件)或底部封装件(SoC封装件))的一个限制是封装中所用的衬底的尺寸。薄衬底和/或无芯衬底(例如层合衬底)已经被用来将封装的厚度减小到更令人满意的水平。然而，由于在封装中使用更薄的衬底，所以可能增大由材料热特性的不同而导致的翘曲的可能性。由于薄或无芯衬底具有较低的机械强度来抵抗材料之间热特性的不同所导致的效应，所以翘曲可能性可能增大。
因此，随着PoP封装件变得更薄以及间距(例如触点之间的间隔)变得更细微，翘曲在PoP封装件的失效或性能降低和/或利用PoP封装件的器件的可靠性问题中扮演越来越重要的角色。例如，PoP封装件中顶部封装件和底部封装件之间的翘曲表现差异可能导致耦接封装的焊点的产率损失(例如相邻焊点之间的短接或桥接或者开路或断开的相对焊端，这具体取决于翘曲表现)。大部分PoP结构可能由于对顶部封装件和/或底部封装件提出的严格翘曲要求而被丢弃(拒绝)。拒绝PoP结构就促使预堆叠产率低下、材料浪费、以及制造成本提高。因此，很多升级和/或设计修改正被采纳和考虑以抑制在使用薄或无芯衬底的封装以及具有细微球间距的封装中的翘曲。
已经被用于细微球间距的一种方案是在底部封装件的顶表面上使用密封剂或模制材料。密封剂可用于抑制在焊接回流期间焊点之间的短接。密封剂还可提供在使用PoP封装件期间相邻焊点之间的电绝缘，和/或为耦接到底部衬底的裸片(例如SOC)提供机械支承。通常使用穿塑孔(TMV)来提供底部封装件上的用于连接到顶部封装上的端子(例如焊球)的端子。使用TMV而导致的一个问题是在形成通路(通常是利用激光烧蚀来实现)期间，通路可能被过烧蚀。过烧蚀可能在相邻TMV之间在密封剂中生成薄的壁。这些薄的壁可能允许焊料在焊接回流期间在相邻TMV之间流动并且桥接(短接)相应的相邻焊点。使用TMV还可能导致PoP封装件中的开路缺陷。开路缺陷可能是由于顶部封装件和/或底部封装件的移位、对TMV形状的控制不佳、和/或焊球因球尺寸而卡住而导致的。随着PoP球间距变得更小，桥接或开路缺陷所导致的问题可能变得更常见和/或更严峻。
发明内容
在某些实施例中，一种PoP封装件包括底部封装件和顶部封装件。底部封装件可包括耦接到衬底的裸片。衬底可以是薄或无芯衬底。加强层可耦接到衬底的上表面并至少部分地覆盖衬底。裸片可在加强层中的开口中耦接到衬底。衬底的至少部分可在所述开口中暴露。在某些实施例中，衬底中的至少一些导电(金属)迹线或垫盘在所述开口中暴露，并且裸片耦接到所述导电迹线或垫盘中的至少一些。
加强层可包括耦接到衬底的一个或多个端子。这些端子可以是穿过加强层的至少部分地被填充有金属的通路。这些端子可在加强层的顶表面处暴露。这些端子可用于通过耦接到顶部封装件上的一个或多个端子而将底部封装件耦接到顶部封装件。顶部封装件可包括存储器裸片。在一些实施例中，顶部封装件是印刷电路板(PCB)，并且存储器裸片耦接到底部封装件的另一(非PCB)侧面。
在某些实施例中，加强层包括芯材料、层合层和金属层(例如，至少部分地填充穿过所述芯材料的通路的金属)。层合层可包括增层膜或预浸材料。在一些实施例中，位于衬底上方的加强层的高度基本上类似于位于衬底上方的裸片的高度。
附图说明
当与附图结合时，参考根据本发明的目前优选的但仅为示例性的实施例的以下详细描述，将更充分地理解本发明的方法与装置的特征和优点，在该附图中：
图1A-K示出了一种用于形成PoP封装件的底部封装件的工艺流程的一个实施例的横截面表示。
图2A-K示出了一种用于形成PoP封装件的底部封装件的工艺流程的一个另选实施例的横截面表示。
图3示出了一种底部封装件的一个实施例的俯视图。
图4示出了耦接到顶部封装件以形成PoP封装件的一种底部封装件(图1K中所示)的一个实施例。
图5示出了耦接到顶部封装件以形成PoP封装件的一种底部封装件(图2K中所示)的另一个实施例。
图6示出了一种端子的一个实施例的横截面表示。
图7示出了一种端子的另一个实施例的横截面表示。
图8示出了耦接到印刷电路板和存储器裸片的一种底部封装件(图1K中所示)的一个实施例。
图9示出了耦接到印刷电路板和存储器裸片的一种底部封装件(图2K中所示)的另一个实施例。
尽管本发明可以容许各种修改形式和替代形式，但其特定实施例在附图中以举例的方式示出并将在本文对详细描述。附图可能不是按比例的。然而，应当理解，附图和详细描述并非旨在将本发明限制于所公开的特定形式，而正相反，其目的在于覆盖落在由所附权利要求所限定的本发明的实质和范围内的所有修改形式、等同形式和替代形式。
具体实施方式
图1A-K示出了一种用于形成PoP封装件的底部封装件的工艺流程的一个实施例的横截面表示。图1A示出了载体100的一个实施例的横截面表示。载体100可以是适于支承和承载无芯衬底或类似薄衬底的任何载体。载体100可以例如是用于无芯衬底或其他薄衬底的临时衬底。
图1B示出了耦接到载体100的芯材料102的一个实施例的横截面表示。芯材料102可以是本领域中已知的适于用作集成电路封装中的芯材料的任何合适的材料。例如，芯材料102可以是介电材料，诸如但不限于陶瓷或树脂材料。
芯材料102可通过例如将芯材料结合或层合到载体来被耦接到载体100。在某些实施例中，芯材料102利用层合层104而被耦接到载体100。在一些实施例中，在载体100和层合层104之间使用籽晶层103。籽晶层103可以是例如铜籽晶层。在某些实施例中，层合层104包括层合材料，诸如但不限于ABF(Ajinomoto增层膜)层合材料或预浸(预浸渍)层合材料。ABF层合可以例如利用真空层合来施加。预浸层合可以例如利用热压层合来施加。在一些实施例中，金属层108形成在芯材料102上。金属层108可以是铜或另一合适的导电金属。
在某些实施例中，在将芯材料102耦接到载体100之后，通路106(例如通孔)形成在芯材料中并且至少部分地填充有金属层108，如图1C中所示。通路106可例如通过在芯材料102中激光钻孔来形成。在形成通路106之后，可在通路中沉积附加金属层108(例如铜)。在一些实施例中，金属层108只部分地填充通路106。在一些实施例中，芯材料102的表面上的金属层108的部分被图案化或以其他方式限定，以在芯材料的表面上提供金属特征部。
在某些实施例中，阻隔层110形成在芯材料102上，如图1C中所示。阻隔层110可例如是通过镀覆形成的镍或镍-铜阻隔层。阻隔层110可在随后被用作用于耦接到封装的裸片的端(隆起)垫盘区域的区域(由图1C中的虚线限定)中形成在芯材料102的上方。
在芯材料102被图案化并且通路106填充有金属层108之后，可在芯材料102上形成底部封装衬底112，如图1D中所示。在某些实施例中，衬底112是无芯衬底(例如只由介电聚合物112A和导电(金属，诸如铜)迹线112B形成的衬底)。然而，衬底112可以是另一相对薄的衬底(例如厚度小于约400μm的衬底)。在某些实施例中，衬底112是由与层合层104基本类似的聚合物形成的无芯衬底。例如，衬底112可包括ABF或预浸材料作为围绕导电迹线的聚合物。在某些实施例中，衬底112由一层或多层聚合物材料和导电迹线形成。
如图1D所示，芯材料102、层合层104、和金属层108形成加强层128。加强层128为衬底112提供加强。例如，加强层128可支撑衬底112并强化衬底(例如使衬底更刚硬)。强化衬底112可允许更好地处理衬底以及为利用衬底制成的底部封装件提供更多硬度。
在形成衬底112之后，可在衬底上形成掩模114，如图1E中所示。掩模114可限定衬底112的表面上端子(例如隆起垫盘或焊球)的位置。掩模114可例如是阻焊层或利用激光烧蚀限定的另一材料。在形成掩模114之后，可从芯材料102和层合层104的底表面移除载体100，如图1F中所示。在层合层104和载体100之间具有籽晶层103的实施例中，还可移除籽晶层。在某些实施例中，层合层104的部分被移除，以暴露通路106中的金属层108。加强层128的存在提供了刚度和硬度以用于在没有载体100的情况下更好地处理衬底112。
在载体100被移除后，可形成腔体或开口，以允许穿过芯材料102将裸片连接到衬底112(例如形成腔体或开口以提供端(隆起)垫盘区域用于耦接到封装的裸片)。图1G-1J示出了一种用于形成为裸片提供端垫盘区域的腔体或开口的工艺的一个实施例。如图1G所示，可移除芯材料102以形成开口116。开口116可形成在图1C-F中所示虚线限定的区域中。芯材料102可例如通过激光烧蚀芯材料而被移除。在某些实施例中，芯材料移除过程(例如激光烧蚀过程)由金属层108的出现来停止。
在芯材料移除过程之后，可移除(例如蚀刻)金属层108(例如铜层)，如图1H中所示。阻隔层110可被用作用于金属层移除过程的蚀刻止挡层(例如阻隔层由耐抗用于移除金属层108的蚀刻过程的另一材料制成)。阻隔层110的存在可抑制在金属层移除过程期间衬底112的过蚀刻。
在金属层108被移除之后，可利用另一移除过程(例如另一蚀刻过程)移除阻隔层110，如图1I中所示。移除阻隔层110暴露开口116中衬底112的表面。在移除阻隔层110之后，一个或多个表面加工可施加于开口116中衬底112的表面，如图1J中所示。可使用的表面加工的示例包括但不限于用于PoP的OSP(有机保焊剂)、ENEPIG(无电镀镍/无电镀钯/浸金)、或SOP(焊料加在焊盘上)。加工衬底112的表面形成用于将裸片耦接到开口116中的衬底表面的端(隆起)垫盘118。
由于开口116是利用向下移除材料到衬底112的表面以暴露该表面的工艺来形成的，所以衬底上的端(隆起)垫盘图案由衬底的表面处的金属(导电)迹线来限定。与利用增层工艺限定图案来在衬底的表面上形成垫盘的情况相比，利用金属迹线限定端垫盘图案就允许实现端垫盘图案中更细微的间距。此外，利用激光烧蚀(或类似技术)来移除芯材料102和形成开口116就允许端垫盘区域(例如开口的宽度)如期望那么小。例如，开口116可具有略微比放置在开口中的裸片的宽度微大的宽度。
在端垫盘118形成在开口116中之后，裸片120可耦接到开口中的衬底112，如图1K中所示。裸片120可以是例如半导体芯片、集成电路裸片、无源部件、或倒装芯片裸片。在某些实施例中，裸片120是片上系统(“SoC”)。裸片120可利用一个或多个端子122耦接到衬底端垫盘118。例如，端子122可以是耦接到端垫盘118上的焊盘的焊球。在某些实施例中，如图1K中所示，裸片120的顶部位于与芯材料102的顶部上的层合层104的顶部基本上相似的高度或者位于比芯材料102的顶部上的层合层104的顶部低的高度。
在某些实施例中，端子124耦接到衬底112的底部(如掩模114所限定)，并且底部封装件126被形成。端子124可用于将衬底112和封装件126耦接到母板或系统印刷电路板(PCB)。
在某些实施例中，端子127形成在底部封装件126的顶部上的金属层108的暴露表面上或由底部封装件126的顶部上的金属层108的暴露表面形成。端子127可用于将底部封装件126耦接到PoP封装件中的顶部封装件。端子127可具有任何期望的端子形状(例如端子可利用激光蚀刻或烧蚀来成形(生成))。图6和7示出了可在底部封装件126中形成的端子127的不同形状的实施例的示例。端子127还可具有所期望的不同表面加工(例如SOP、ENEPIG、EPIG(无电镀钯/浸金)等)。
图2A-K示出了一种用于形成PoP封装件的底部封装件的工艺流程的一个另选实施例的横截面表示。图2A示出了具有填充穿过芯材料的通路106的金属层108的芯材料102的一个实施例的横截面表示。通路106可例如通过在芯材料102中激光钻孔来形成。金属层108可例如通过通路106的浆料孔(PTH)填充来形成。金属层108可以是铜或另一合适的导电金属。金属层108还可覆盖芯材料102的表面的部分。在一些实施例中，芯材料102的表面上的金属层108的部分被图案化或以其他方式限定，以在芯材料的表面上提供金属特征部。在一些实施例中，阻隔层110形成在芯材料102上。
在芯材料102被图案化且金属层108被形成之后，芯材料102可耦接到载体100(如图2B所示)。图2C示出了利用层合层104耦接的芯材料102和载体100。芯材料102可例如通过利用层合层104将芯材料结合或层合到载体来被耦接到载体100。在一些实施例中，在载体100和层合层104之间使用籽晶层(未示出)。在某些实施例中，层合层104包括层合材料，诸如但不限于ABF(Ajinomoto增层膜)层合材料或预浸(预浸渍)层合材料。
在芯材料102和载体100利用层合层104耦接之后，可在芯材料102上形成底部封装衬底112，如图2D中所示。芯材料102、层合层104、和金属层108形成加强层128'。图2D中所示的加强层128'基本上类似于图1D中所示的加强层128，区别在于用金属层108基本上完全填充芯材料102中的通路106(例如，由于通路的浆料孔填充，金属层基本上填充芯材料中的通路)。图2E-2K中载体100、芯材料102、层合层104、阻隔层110、和衬底112的后续处理也基本上类似于图1E-1K中所描绘的处理。因此，图2K中所示的具有加强层128'的封装件126'与图1K中所示的具有加强层128的封装件126具有基本上类似的结构。
如图1K和2K所示，加强层(加强层128或加强层128')以最小量的z高度(垂直高度)增加来提供对衬底112和底部封装件(底部封装件126或底部封装件126')的加强。如上所述，加强层128(或加强层128')可具有与裸片120的高度基本上类似的高度。在一些实施例中，调节加强层的高度以适应(例如基本上匹配)裸片120的高度。可将加强层的高度调节成为底部封装件提供某些硬度参数而需要的最小厚度。此外，使用加强层就允许通过使用由于加强层所提供的刚度而可具有最小厚度的薄或无芯衬底来减小底部封装件的总高度。
典型的衬底工艺包括使用密封剂或其他模制材料和/或形成穿塑孔(TMV)。由于增加的结合密封剂和/或TMV技术的复杂性，这样的衬底工艺可能是一定程度上不可靠的工艺。由于图1A-1K和图2A-2K中所示的衬底工艺实施例不包括使用密封剂或TMV，所以这样的衬底工艺可以是更简单且更可靠的衬底工艺。与利用密封剂或TMV的工艺相比，图1A-1K或图2A-2K中所示的对衬底的处理还可成本更低。提供加强层如上所述还提供了衬底的更好处理，这可通过减少处理期间的处理错误来提高衬底产率。
此外，图1A-1K和图2A-2K所示的工艺实施例在将衬底耦接到裸片(裸片120)之前处理衬底(衬底112)。通常，衬底处理是在裸片已经耦接到衬底(例如嵌入在衬底上)的情况下进行的。在这样的衬底工艺之后，如果衬底失效，则耦接的裸片与衬底一起被丢弃(扔掉)。利用这样的衬底工艺的衬底产率(并且因此封装产率)通常大约为约90％。然而，在将衬底耦接到裸片之前处理衬底就可通过只允许好的(通过的)衬底耦接到好的裸片来提供更高产率封装。利用图1A-1K和/或图2A-2K所示的工艺将好衬底耦接到好裸片就可将封装产率提高最高达约99％或更高。
在图1A-1K和图2A-2K所示的工艺实施例中，应当理解，芯材料102在一些实施例中可被耦接到载体100的两个侧面(例如芯材料被耦接到载体的顶部和底部二者)，并且随后的处理可利用载体的顶部和底部二者上的芯材料形成相同底部封装件(126或126’)。例如，载体100任一侧面上的芯材料102可与载体分离并随后被单独处理。此外，可由单层芯材料102在载体100的任一侧面上形成多于一个底部封装件(例如芯材料102可被用作用于载体的任一侧面上多个封装的基底层)。
图3示出了底部封装件126的一个实施例的俯视图。底部封装件126可利用图1A-1K和/或图2A-2K所示的工艺中任一者来生成。如图3所示，裸片120被定位于衬底112上，并基本上被扇出型晶圆级封装(FOWLP)布置的加强层128和端子130围绕。虽然示出了FOWLP布置，但应当理解，利用图1A-1K和/或图2A-2K所示的工艺也可想到其他晶圆封装布置。端子130可对应于(图1K和2K中所示)金属层108填充的通路106的位置。
底部封装件126可耦接到顶部封装件(例如存储器封装)以形成PoP封装件。图4示出了耦接到顶部封装件132以形成PoP封装件134的底部封装件126(图1K所示)的一个实施例。图5示出了耦接到顶部封装件132以形成PoP封装件134'的底部封装件126'(图2K所示)的一个实施例。顶部封装件132可包括例如存储器裸片或多层印刷电路板(MLB)。如图4和5所示，顶部封装件132可通过将顶部封装件上的端子136耦接到底部封装件顶部上的端子130而被耦接到底部封装件126(或126')中的加强层128(或128')。端子136可例如是焊球。
MLB可使用上文中为底部封装件126所述的相同工艺方法。因此，其它部件可位于与底部封装件126中的开口116类似的开口中。例如，可在MLB中使用扇出型晶圆级封装、RF模块、SiP(系统级封装)、电阻器、电容器、或SoC。将部件放置在相应开口中可减小SMT(表面安装技术)之后的总体高度。
在一些实施例中，本文所述的底部封装件(例如底部封装件126或底部封装件126')翻转，并且加强层耦接到印刷电路板(PCB)(例如，顶部封装件是PCB，但整个组件翻转，从而PCB在底部封装件下面)。存储器裸片然后可耦接到底部封装件的与印刷电路板相对的侧面。图8示出了耦接到印刷电路板(PCB)140和存储器裸片142的底部封装件126(图1K所示)的一个实施例。图9示出了耦接到PCB 140和存储器裸片142的底部封装件126'(图2K中所示)的另一个实施例。PCB 140可通过将PCB上的端子136耦接到底部封装件上的端子130而被耦接到底部封装件126(或126')。在某些实施例中，存储器裸片142利用端子124而在底部封装件126(或126')的非PCB侧面(现在顶部)上耦接到衬底112。存储器裸片142可例如是具有在彼此的顶部上堆叠的两个存储器裸片的存储器裸片堆叠。在一些实施例中，存储器裸片142是扇出型存储器裸片堆叠。
在某些实施例中，端子130之间的间距相对细微，如图3中所示。由于使用通路106中的金属层108来限定底部封装件126或126'上的端子130，所以细微的间距可以是可能的。利用通路106中的金属层108来限定端子130将端子提供为可在端子之间具有小间隔的柱状结构。因此，图4和5中所示顶部封装件132上的端子136可以是相对小的焊球，以在顶部封装件耦接到底部封装件126或126'时避免相邻焊球之间的桥接。
根据本说明书，本发明各个方面的其他修改和替代实施例对于本领域的技术人员而言将是显而易见的。因此，将本说明书理解为仅是示例性的并且目的是用于教导本领域的技术人员执行本发明的一般方式。应当理解，本文所示和所述的本发明形式将被当做目前优选的实施例。元素与材料可被本文所示和所述的那些元素与材料所替代，可反向部件和工艺并且可独立地利用本发明的某些特征，在受益于本发明的本说明书之后，所有这些对于本领域的技术人员而言都将是显而易见的。可在不脱离以下权利要求书中所描述的本发明的实质和范围的情况下对本文所述的元素作出修改。

Claims (18)

1.一种半导体器件封装组件，包括：
衬底，包括一个或多个介电材料层，并且在所述介电材料层中的一个或多个中具有一条或多条导电迹线；
至少部分地覆盖所述衬底的顶表面的加强层，所述加强层与所述衬底直接接触，其中所述加强层包括耦接到所述衬底并且在所述加强层的顶表面处暴露的一个或多个端子，并且其中所述加强层包括暴露位于所述衬底的所述顶表面的至少部分上的端垫盘图案的开口；和
裸片，耦接到所述衬底的所述顶表面上的所述端垫盘图案，其中所述裸片被定位在所述加强层中的所述开口中；
其中所述衬底的所述顶表面上的所述端垫盘图案由所述衬底的所述顶表面处的介电材料层中的导电迹线来限定，并且其中所述顶表面处的导电迹线暴露于所述加强层中的所述开口中。
2.根据权利要求1所述的组件，其中所述衬底为无芯衬底。
3.根据权利要求1所述的组件，其中所述加强层包括芯材料、层合层和金属层。
4.根据权利要求1所述的组件，其中所述加强层中的所述端子包括穿过所述加强层的至少部分地填充有金属的通路。
5.根据权利要求1所述的组件，其中位于所述衬底上方的所述加强层的高度基本上类似于位于所述衬底上方的所述裸片的高度。
6.根据权利要求1所述的组件，其中所述裸片包括片上系统(“SoC”)裸片。
7.一种用于形成半导体器件封装组件的方法，包括：
在载体上形成加强层；
在所述加强层上形成衬底，所述衬底的顶表面与所述加强层直接接触；
从所述加强层和所述衬底移除所述载体；
移除所述加强层的一部分以在所述加强层中形成开口，其中所述衬底的顶表面的至少部分在所述开口中暴露；以及
将裸片耦接到所述衬底的顶表面的所暴露的部分。
8.根据权利要求7所述的方法，其中所述加强层包括芯材料，所述方法还包括形成穿过所述芯材料的一条或多条通路以及用金属至少部分地填充所述通路。
9.根据权利要求7所述的方法，其中所述加强层包括芯材料，所述方法还包括利用激光烧蚀所述芯材料来形成所述开口的至少部分。
10.根据权利要求7所述的方法，其中通过形成所述加强层，然后将所述加强层耦接到所述载体来在所述载体上形成所述加强层。
11.根据权利要求7所述的方法，其中所述衬底包括一个或多个聚合物材料层，在所述聚合物材料层中具有一条或多条导电迹线，所述方法还包括在所述衬底的位于所述开口中的所述表面上暴露所述导电迹线中的至少一者，以及将所述裸片耦接到所暴露的导电迹线。
12.根据权利要求7所述的方法，其中所述衬底形成在所述加强层上并且与所述加强层直接接触，而没有居间材料。
13.根据权利要求7所述的方法，还包括在所述衬底的与所述加强层相背对的表面上形成掩模，以及在所述衬底的表面上形成由所述掩模限定的一个或多个端子。
14.一种半导体器件封装组件，包括：
底部封装件，所述底部封装件包括：
衬底，包括一个或多个介电材料层，并且在所述介电材料层中的一个或多个中具有一条或多条导电迹线；
至少部分地覆盖所述衬底的顶表面的加强层，所述加强层与所述衬底直接接触，其中所述加强层包括耦接到所述衬底并且在所述加强层的顶表面处暴露的一个或多个端子，并且其中所述加强层包括暴露位于所述衬底的所述顶表面的至少部分上的端垫盘图案的开口；和
裸片，耦接到所述衬底的所述顶表面上的所述端垫盘图案，其中所述裸片被定位在所述加强层中的所述开口中，并且其中所述衬底的所述顶表面上的所述端垫盘图案由所述衬底的所述顶表面处的介电材料层中的导电迹线来限定，并且其中所述顶表面处的导电迹线暴露于所述加强层中的所述开口中；和
顶部封装件；
其中所述顶部封装件耦接到所述加强层中的所述端子中的一个或多个端子。
15.根据权利要求14所述的组件，其中所述顶部封装件包括存储器裸片。
16.根据权利要求14所述的组件，其中所述顶部封装件包括印刷电路板，并且其中所述组件还包括耦接到所述衬底的底表面的存储器裸片。
17.根据权利要求14所述的组件，其中位于所述加强层中的所述端子包括穿过所述加强层的通路，所述通路至少部分地填充有金属并且至少部分地填充有来自所述衬底的所述顶表面处的聚合物材料层的聚合物材料，所述通路中的金属与所述衬底中的所述导电迹线中的一条或多条导电迹线接触并且在所述加强层的顶表面处暴露。
18.根据权利要求14所述的组件，其中所述衬底形成在所述加强层上并且与所述加强层直接接触，使得所述衬底与所述加强层直接接触而没有居间材料。
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