TWI594345B - 超微細間距層疊封裝（ＰｏＰ）無核心封裝 - Google Patents

超微細間距層疊封裝（ＰｏＰ）無核心封裝 Download PDF

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TWI594345B
TWI594345B TW103128693A TW103128693A TWI594345B TW I594345 B TWI594345 B TW I594345B TW 103128693 A TW103128693 A TW 103128693A TW 103128693 A TW103128693 A TW 103128693A TW I594345 B TWI594345 B TW I594345B
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substrate
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top surface
package
opening
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徐潤忠
軍 翟
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蘋果公司
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Description

超微細間距層疊封裝(PoP)無核心封裝
本發明係關於半導體封裝及用於封裝半導體裝置之方法。更明確而言，本發明係關於容納主動或被動組件之疊層封裝(package-on-package，PoP)之底部封裝。
隨著半導體工業中對於較低成本、較高效能、增加之積體電路密度及增加之封裝密度的需求繼續，疊層封裝(「PoP」)技術已變得愈來愈普及。隨著對愈來愈小之封裝的推動增加，晶粒與封裝之整合(例如，「預堆疊」或系統單晶片(system on a chip，「SoC」)技術與記憶體技術之整合)使得封裝更薄。此預堆疊已變為薄及微細間距PoP封裝之關鍵組件。
減小封裝(例如，PoP封裝中之頂部封裝(記憶體封裝)或底部封裝(SoC封裝))之尺寸的一個限制為封裝中所使用之基板之尺寸。已使用薄基板及/或無核心基板(例如，層合基板)將封裝厚度減小至較合意程度。然而，由於在封裝中使用較薄基板，由材料之熱特性之差異引起的翹曲之可能性可增加。因為薄或無核心基板具有較小機械強度來抵抗由材料之間的熱特性之差異導致的效應，所以翹曲可能性可增加。
因此，隨著PoP封裝變得較薄且間距(例如，觸點之間的間隔)變得較微細，在PoP封裝失效或低效及/或利用PoP封裝之裝置之可靠性問題中，翹曲之影響日益顯著。舉例而言，PoP封裝中之頂部封裝與 底部封裝之間的翹曲行為之差異可導致耦接封裝之焊接點中之良率損失(例如，取決於翹曲行為的鄰近焊接點之間的短路或橋接或開路或斷開之對置焊接端子)。由於強加於頂部封裝及/或底部封裝之嚴格翹曲規格，大部分PoP結構可被扔掉(丟棄)。丟棄PoP結構導致預堆疊良率降低、材料廢損及製造成本增加。因此，現正採用且預期諸多升級及/或設計修改以抑制使用薄或無核心基板之封裝及具有微細焊球間距之封裝中的翹曲。
已用於微細焊球間距之一種解決方案已在底部封裝之頂表面上使用囊封劑或模製材料。囊封劑可用於在焊料回焊期間抑制焊接點之間的短路。囊封劑亦可在使用PoP封裝期間提供鄰近焊接點之間的電絕緣及/或為耦接至底部基板之晶粒(例如，SOC)提供機械支撐。穿模通孔(through-mold vias，TMV)通常用於在底部封裝上提供端子以連接至頂部封裝上之端子(例如，焊球)。伴隨TMV使用出現的一個問題為在通孔形成(通常以雷射切除形成)期間，通孔可能經過度切除。過度切除可在鄰近TMV之間的囊封劑中產生薄壁。此等薄壁可允許焊料在焊料回焊期間在鄰近TMV之間流動且橋接相應鄰近焊接點(使該等相應鄰近焊接點短路)。使用TMV亦可在PoP封裝中產生開路缺陷。開路缺陷可由頂部封裝及/或底部封裝偏移、TMV形狀控制不佳及/或由焊球尺寸引起的焊球黏著導致。隨著PoP焊球間距變得較小，由橋接或開路缺陷引起之問題可變得愈發頻繁及/或愈發嚴重。
在某些實施例中，一PoP封裝包括一底部封裝及一頂部封裝。該底部封裝可包括耦接至一基板之一晶粒。該基板可為一薄或無核心基板。一強化層可耦接至該基板之一上表面且至少部分地覆蓋該基板。該晶粒可於該強化層之一開口中耦接至該基板。於該開口中曝露該基板之至少部分。在某些實施例中，於該開口中曝露該基板中之至少一 些導電(金屬)跡線或襯墊且該晶粒耦接至該等導電跡線或襯墊中之至少一些。
該強化層可包括耦接至該基板之一或多個端子。該等端子可為至少部分地填充有金屬的穿過該強化層之通孔。該等端子可於該強化層之一頂表面曝露。該等端子可用於藉由耦接至頂部封裝上之一或多個端子來將該底部封裝耦接至該頂部封裝。該頂部封裝可包括一記憶體晶粒。在一些實施例中，該頂部封裝為一印刷電路板(printed circuit board，PCB)且一記憶體晶粒耦接至該底部封裝之另一(非PCB)側。
在某些實施例中，該強化層包括核心材料、一層合層及一金屬層(例如，至少部分地填充穿過該核心材料之通孔的金屬)。該層合層可包括累積膜或預浸材料。在一些實施例中，在該基板上方之該強化層之一高度實質上與該基板上方之該晶粒之一高度相似。
100‧‧‧載體
102‧‧‧核心材料
103‧‧‧晶種層
104‧‧‧層合層
106‧‧‧通孔
108‧‧‧金屬層
110‧‧‧障壁層
112‧‧‧底部封裝基板/基板
112A‧‧‧介電聚合物
112B‧‧‧導電(金屬)跡線
114‧‧‧遮罩
116‧‧‧開口
118‧‧‧端子(凸塊)墊
120‧‧‧晶粒
122‧‧‧端子
124‧‧‧端子
126‧‧‧底部封裝
126'‧‧‧底部封裝
127‧‧‧端子
128‧‧‧強化層
128'‧‧‧強化層
130‧‧‧端子
132‧‧‧頂部封裝
134‧‧‧PoP封裝
134'‧‧‧PoP封裝
136‧‧‧端子
140‧‧‧印刷電路板(PCB)
142‧‧‧記憶體晶粒
當與附圖結合取用，藉由參考根據本發明之本發明目前較佳但仍為說明性實施例的以下詳細描述時，將更充分理解本發明之方法及設備的特徵及優勢，在該等附圖中：圖1A至圖1K描繪用於形成PoP封裝之底部封裝之程序流程的實施例之截面表示。
圖2A至圖2K描繪用於形成PoP封裝之底部封裝之程序流程的替代性實施例之截面表示。
圖3描繪底部封裝之實施例的俯視圖。
圖4描繪耦接至頂部封裝以形成PoP封裝的底部封裝(展示於圖1K中)之實施例。
圖5描繪耦接至頂部封裝以形成PoP封裝的底部封裝(展示於圖2K中)之另一實施例。
圖6描繪端子之實施例的截面表示。
圖7描繪端子之另一實施例的截面表示。
圖8描繪耦接至印刷電路板及記憶體晶粒之底部封裝(展示於圖1K中)的實施例。
圖9描繪耦接至印刷電路板及記憶體晶粒之底部封裝(展示於圖2K中)的另一實施例。
雖然本發明易有各種修改及替代形式，但本發明之特定實施例係藉助於附圖中之實例展示且將在本文中對加以詳細描述。該等附圖可能並非按比例的。應瞭解，該等圖式及對其之詳細描述不欲將本發明限制於所揭示之特定形式，相反，本發明意欲涵蓋屬於如隨附申請專利範圍所界定的本發明之精神及範疇的所有修改、等效物及替代物。
圖1A至圖1K描繪用於形成PoP封裝之底部封裝之程序流程的實施例之截面表示。圖1A描繪載體100之實施例之截面表示。載體100可為適於支撐及攜載無核心基板或類似薄基板之任何載體。載體100可為例如用於無核心基板或其他薄基板之臨時基板。
圖1B描繪耦接至載體100之核心材料102的實施例之截面表示。核心材料102可為此項技術中已知的用作積體電路封裝中之核心材料的任何適合材料。舉例而言，核心材料102可為諸如(但不限於)陶瓷或樹脂材料之介電材料。
可藉由例如將核心材料接合或層合至載體來將核心材料102耦接至載體100。在某些實施例中，使用層合層104來將核心材料102耦接至載體100。在一些實施例中，在載體100與層合層104之間使用晶種層103。晶種層103可為例如銅晶種層。在某些實施例中，層合層104包括諸如(但不限於)ABF(Ajinomoto Build-Up Film，味之素累積膜) 層合材料或預浸(預浸漬)層合材料之層合材料。可例如使用真空層合來塗覆ABF層合材料。可例如使用熱壓層合來塗覆預浸層合材料。在一些實施例中，於核心材料102上形成金屬層108。金屬層108可為銅或另一適合之導電金屬。
如圖1C中所示，在某些實施例中，在將核心材料102耦接至載體100後，於核心材料中形成通孔106(例如，穿孔)且該等通孔至少部分地填充有金屬層108。可例如藉由在核心材料102中雷射鑽孔來形成通孔106。在通孔106形成後，可在通孔中沈積額外金屬層108(例如，銅)。在一些實施例中，金屬層108僅部分地填充通孔106。在一些實施例中，圖案化或以其他方式界定核心材料102表面上的金屬層108之多個部分以在核心材料表面上提供金屬特徵。
如圖1C中所示，在某些實施例中，於核心材料102上形成障壁層110。障壁層110可為例如藉由電鍍形成之鎳或鎳銅障壁層。障壁層110可在一區域(由圖1C中虛線界定)中形成於核心材料102之上，該區域稍後被用作耦接至封裝之晶粒的端子(凸塊)墊區域。
如圖1D中所示，在圖案化核心材料102且用金屬層108填充通孔106後，可於核心材料102上形成底部封裝基板112。在某些實施例中，基板112為無核心基板(例如，僅由介電聚合物112A及導電(諸如銅之金屬)跡線112B製成之基板)。然而，基板112可為另一相對薄之基板(例如，厚度小於約400μm之基板)。在某些實施例中，基板112為由實質上類似於層合層104之聚合物製成之無核心基板。舉例而言，基板112可包括ABF或預浸材料以作為導電跡線周圍之聚合物。在某些實施例中，基板112由一或多層聚合物材料及導電跡線製成。
如圖1D中所示，核心材料102、層合層104及金屬層108形成強化層128。強化層128為基板112提供強化。舉例而言，強化層128可支撐基板112且硬化基板(例如，使基板更堅硬)。硬化之基板112可使基板 處置較佳且為使用該基板製成之底部封裝提供較高硬度。
如圖1E中所示，在基板112形成後，可於該基板上形成遮罩114。遮罩114可界定基板112之表面上之端子(例如，凸塊墊或焊球)的位置。遮罩114可為例如使用雷射切除界定之阻焊劑或另一材料。如圖1F中所示，在遮罩114形成後，可自核心材料102及層合層104之底表面移除載體100。在層合層104與載體100之間有晶種層103之實施例中，亦可移除晶種層。在某些實施例中，移除層合層104之多個部分以曝露通孔106中之金屬層108。強化層128之存在提供無載體100時用於基板112之更佳處置的剛度及硬度。
在載體100移除後，可形成凹穴或開口以使晶粒經由核心材料102連接至基板112(例如，形成凹穴或開口以提供耦接至封裝之晶粒的端子(凸塊)墊區域)。圖1G至圖1J描繪用於形成提供晶粒的端子墊區域之凹穴或開口的程序之實施例。如圖1G中所示，可移除核心材料102以形成開口116。可在由圖1C至圖1F中所描繪之虛線界定的區域中形成開口116。可例如藉由雷射切除核心材料來移除核心材料102。在某些實施例中，由於金屬層108存在而終止核心材料移除程序(例如，雷射切除程序)。
如圖1H中所示，在核心材料移除程序之後，可移除(例如，蝕刻)金屬層108(例如，銅層)。障壁層110可用作金屬層移除程序之蝕刻終止層(例如，障壁層由可抵抗用於移除金屬層108之蝕刻程序的另一材料製成)。障壁層110之存在可在金屬層移除程序期間抑制基板112之過度蝕刻。
如圖1I中所示，在金屬層108移除後，可使用不同移除程序(例如，不同蝕刻程序)來移除障壁層110。障壁層110之移除使基板112之表面曝露於開口116中。如圖1J中所示，在障壁層110移除後，可對開口116中的基板112之表面應用一或多個表面加工。可用之表面加工之 實例包括(但不限於)用於PoP之有機焊料防腐劑(organic solder preservative，OSP)、無電電鍍鎳/無電電鍍鈀/浸鍍金(electroless nickel/electroless palladium/immersion gold，ENEPIG)或有墊焊料(solder on pad，SOP)。加工基板112之表面形成用於將晶粒耦接至開口116中的基板表面之端子(凸塊)墊118。
因為使用將材料向下移除至基板112之表面以曝露該表面的程序來形成開口116，所以藉由基板之表面處之金屬(導電)跡線來界定基板上之端子(凸塊)墊圖案。相比使用累積程序在基板之表面上形成襯墊來界定圖案之情況，使用金屬跡線界定端子墊圖案允許端子墊圖案中的更微細間距。此外，使用雷射切除(或類似技術)移除核心材料102且形成開口116使得端子墊區域(例如，開口之寬度)如所要地一樣小。舉例而言，開口116可具有略大於置放於開口中之晶粒之寬度的寬度。
如圖1K中所示，在於開口116中形成端子墊118後，可在該開口中將晶粒120耦接至基板112。晶粒120可為例如半導體晶片、積體電路晶粒、被動組件或覆晶晶粒。在某些實施例中，晶粒120為系統單晶片(「SoC」)。可使用一或多個端子122將晶粒120耦接至基板端子墊118。舉例而言，端子122可為耦接至端子墊118上之焊接墊的焊球。在某些實施例中，如圖1K中所示，相比核心材料102之上的層合層104之頂部，晶粒120之頂部處於實質上類似之高度或較低高度。
在某些實施例中，將端子124耦接至基板112之底部(如遮罩114所界定)且形成底部封裝126。端子124可用於將基板112及封裝126耦接至主機板或系統印刷電路板(PCB)。
在某些實施例中，在底部封裝126之上的金屬層108之曝露表面上或自該表面形成端子127。端子127可用於將底部封裝126耦接至PoP封裝中之頂部封裝。端子127可具有所要的任何端子形狀(例如，可使 用雷射蝕刻或切除來塑形(產生)端子)。圖6及圖7描繪可形成於底部封裝126中之端子127之不同形狀之實施例的實例。端子127亦可按需要具有不同表面加工(例如SOP、ENEPIG、EPIG(無電電鍍鈀/浸鍍金)等)。
圖2A至圖2K描繪用於形成PoP封裝之底部封裝之程序流程的替代性實施例之截面表示。圖2A描繪具有金屬層108之核心材料102的實施例之截面表示，該金屬層填充穿過該核心材料之通孔106。可例如藉由在核心材料102中雷射鑽孔來形成通孔106。可例如藉由通孔106之焊膏孔(paste hole，PTH)填充來形成金屬層108。金屬層108可為銅或另一適合之導電金屬。金屬層108亦可覆蓋核心材料102之表面之多個部分。在一些實施例中，圖案化或以其他方式界定核心材料102之表面上的金屬層108之多個部分以在核心材料之表面上提供金屬特徵。在某些實施例中，於核心材料102上形成障壁層110。
在圖案化核心材料102且形成金屬層108後，可將核心材料102耦接至載體100(展示於圖2B中)。圖2C描繪使用層合層104耦接之核心材料102與載體100。可藉由例如使用層合層104將核心材料接合或層合至載體來將核心材料102耦接至載體100。在一些實施例中，於載體100與層合層104之間使用晶種層(未圖示)。在某些實施例中，層合層104包括諸如(但不限於)ABF(味之素累積膜)層合材料或預浸(預浸漬)層合材料之層合材料。
如圖2D中所示，在使用層合層104耦接核心材料102與載體100後，可於核心材料102上形成底部封裝基板112。核心材料102、層合層104及金屬層108形成強化層128'。圖2D中所展示之強化層128'實質上類似於圖1D中所展示之強化層128，區別在於核心材料102中之通孔106實質上全部填充有金屬層108(例如，歸因於通孔之焊膏孔填充，金屬層實質上填充核心材料中之通孔)。圖2E至圖2K中的對載體 100、核心材料102、層合層104、障壁層110及基板112的後續處理亦實質上類似於圖1E至圖1K中所描述之處理。因此，圖2K中所展示的具有強化層128'之封裝126'具有實質上與圖1K中所展示的具有強化層128之封裝126相似的結構。
如圖1K及圖2K中所示，強化層(強化層128或強化層128')以最小量之添加z高度(垂直高度)為基板112及底部封裝(底部封裝126或底部封裝126')提供強化。如上所述，強化層128(或強化層128')可具有實質上與晶粒120之高度相似的高度。在一些實施例中，調整強化層之高度以適應(例如，實質上匹配)晶粒120之高度。可將強化層之高度調整至為底部封裝提供特定硬度參數所需的最小厚度。此外，由於強化層所提供之剛度，強化層之使用允許經由使用可具有最小厚度之薄或無核心基板來減小底部封裝之總高度。
典型基板程序包括使用囊封劑或其他模製材料及/或形成穿模通孔(TMV)。歸因於囊封劑結合及/或TMV技術中的增加之複雜度，此等基板程序在某種程度上可為不可靠程序。因為圖1A至圖1K及圖2A至圖2K中所描繪之基板程序實施例不包括囊封劑或TMV之使用，所以此等基板程序可為較容易且較可靠之基板程序。相比使用囊封劑或TMV之處理，如圖1A至圖1K或圖2A至圖2K所描繪的基板處理亦可為成本較低的。如上所述，提供強化層亦提供較佳基板處置，其可藉由在處理期間減少處置錯誤來改善基板良率。
此外，圖1A至圖1K及圖2A至圖2K中所描繪的程序實施例在處理基板(基板112)後將該基板耦接至晶粒(晶粒120)。通常，在晶粒已耦接至基板(例如，嵌於基板上)之情況下基板處理發生。在此等基板程序後，若基板發生故障，則將耦接之晶粒連同基板一起丟棄(扔掉)。使用此等基板程序之基板良率(及由此之封裝良率)通常相當於約90%。然而，在處理基板後將基板耦接至晶粒可藉由僅允許良好(合 格)基板耦接至良好晶粒來提供較高良率之封裝。使用圖1A至圖1K及/或圖2A至圖2K中所描繪的程序將良好基板耦接至良好晶粒可將封裝良率增加達到約99%或更高。
在圖1A至圖1K及圖2A至圖2K中所描繪的程序實施例中，應理解，在一些實施例中，可將核心材料102耦接至載體100兩側(例如，將核心材料耦接至載體之頂部及底部兩者)，且使用載體之頂部及底部兩者上之核心材料進行後續處理可形成相同底部封裝(126或126')。舉例而言，載體100之任一側上之核心材料102可與載體分離且隨後予以獨立處理。此外，可於載體100之任一側上由單層核心材料102形成一個以上底部封裝(例如，核心材料102可用作載體之任一側上之多個封裝之基層)。
圖3係描繪底部封裝126之實施例的俯視圖。可使用圖1A至圖1K及/或圖2A至圖2K中所描繪的程序中之任一者來製造底部封裝126。如圖3中所示，晶粒120位於基板112上且實質上由強化層128及成扇出晶圓級封裝(fan-out wafer level package，FOWLP)配置之端子130包圍。雖然已展示FOWLP配置，但應理解，使用圖1A至圖1K及/或圖2A至圖2K中所描繪之程序，亦可預期其他晶圓封裝配置。端子130可對應於填充有金屬層108之通孔106之位置(展示於圖1K及圖2K中)。
底部封裝126可耦接至頂部封裝(例如，記憶體封裝)以形成PoP封裝。圖4描繪耦接至頂部封裝132以形成PoP封裝134之底部封裝126(展示於圖1K中)的實施例。圖5描繪耦接至頂部封裝132以形成PoP封裝134'之底部封裝126'(展示於圖2K中)的實施例。頂部封裝132可包括例如記憶體晶粒或多層印刷電路板(multilayer printed circuit board，MLB)。如圖4及圖5中所示，可藉由將頂部封裝上之端子136耦接至底部封裝上之端子130來將頂部封裝132耦接至底部封裝126(或126')中之強化層128(或128')。端子136可為例如焊球。
MLB可使用上文針對底部封裝126所描述之相同程序方法。因此，其他組件可位於類似於底部封裝126中之開口116的開口中。舉例而言，可在MLB中使用扇出晶圓級封裝、RF模組、系統級封裝(system in package，SiP)、電阻器、電容器或SoC。將組件置於各別開口中可減小表面黏著技術(surface mount technology，SMT)之後的總高度。
在一些實施例中，如本文中所描述之底部封裝(例如，底部封裝126或底部封裝126')經翻轉且強化層經耦接至印刷電路板(PCB)(例如，頂部封裝為PCB，但整個總成經翻轉，以使PCB處於底部封裝下方)。記憶體晶粒可接著耦接至底部封裝的與印刷電路板相反之側。圖8描繪耦接至印刷電路板(PCB)140及記憶體晶粒142之底部封裝126(展示於圖1K中)的實施例。圖9描繪耦接至PCB 140及記憶體晶粒142之底部封裝126'(展示於圖2K中)的另一實施例。可藉由將PCB上之端子136耦接至底部封裝上之端子130來將PCB 140耦接至底部封裝126(或126')。在某些實施例中，使用端子124將記憶體晶粒142耦接至底部封裝126(或126')之非PCB側(目前為頂部)上的基板112。記憶體晶粒142可為例如兩個記憶體晶粒相互堆疊於彼此之上的記憶體晶粒堆疊。在一些實施例中，記憶體晶粒142為扇出記憶體晶粒堆疊。
如圖3中所示，在某些實施例中，端子130之間的間距相對微細。微細間距可由於使用通孔106中之金屬層108來界定底部封裝126或126'上之端子130而係可能的。使用通孔106中之金屬層108來界定端子130使端子呈可具有端子間的小間距之柱狀結構。因此，圖4及圖5中所示的頂部封裝132上之端子136可為相對小之焊球以在頂部封裝經耦接至底部封裝126或126'時避免鄰近焊球之間的橋接。
鑒於本描述，對於熟習此項技術者而言，本發明之各種態樣之進一步修改及替代性實施例將為顯而易知的。因此，本描述應僅理解 為說明性的且用於教示熟習此項技術者進行本發明之通用方式的目的。應瞭解，本文中所展示及描述的本發明之形式應視為目前較佳實施例。元件及材料可替代本文中所說明及描述之元件及材料，部分及程序可顛倒，且可獨立利用本發明之某些特徵，以上所有在具有本發明之本描述之益處後對熟習此項技術者而言將為顯而易知的。在不背離如以下申請專利範圍中所描述的本發明之精神及範疇的情況下，可對本文所描述之元件作出改變。
102‧‧‧核心材料
104‧‧‧層合層
106‧‧‧通孔
108‧‧‧金屬層
112‧‧‧底部封裝基板
120‧‧‧晶粒
122‧‧‧端子
124‧‧‧端子
126‧‧‧底部封裝
127‧‧‧端子
128‧‧‧強化層

Claims (14)

  1. 一種半導體裝置封裝總成，其包含：一基板，其包含一或多層介電材料，並具有一或多根導電跡線於該一或多層介電材料中；至少部分地覆蓋該基板之一頂表面的一強化層，該強化層係直接接觸於該基板之該頂表面，其中該強化層包含耦接至該基板且曝露於該強化層之一頂表面的一或多個端子，且其中該強化層包含一開口，其曝露一端子墊圖案於該基板之該頂表面之至少一部分上；及耦接至該基板之該頂表面上的該端子墊圖案的一晶粒，其中該晶粒位於該強化層中之該開口中；其中該基板之該頂表面上的該端子墊圖案是由該基板之該頂表面處之一層介電材料中的該等導電跡線所定義，該頂表面處之該等導電跡線在該強化層中之該開口被形成時是暴露於該強化層中之該開口中。
  2. 如請求項1之總成，其中該基板為一無核心基板。
  3. 如請求項1之總成，其中該強化層包含一核心材料、一層合層及一金屬層。
  4. 如請求項1之總成，其中該強化層中之該等端子包含至少部分地填充有金屬的穿過該強化層之通孔。
  5. 如請求項1之總成，其中該基板上方之該強化層之一高度實質上與該基板上方之該晶粒之一高度相似。
  6. 一種用於形成一半導體裝置封裝總成之方法，其包含：於一載體上形成一強化層；於該強化層上形成一基板，該基板之一頂表面係直接接觸於 該強化層；自該強化層及該基板移除該載體；移除該強化層的一部份以於該強化層中形成一開口，其中該基板之該頂表面之至少部分於該開口中曝露；及將一晶粒耦接至該基板之該頂表面之經曝露部分。
  7. 如請求項6之方法，其中該強化層包含核心材料，該方法進一步包含形成穿過該核心材料之一或多個通孔及用金屬至少部分地填充該等通孔。
  8. 如請求項6之方法，其中該強化層包含核心材料，該方法進一步包含使用雷射切除該核心材料之至少部分以形成該開口。
  9. 如請求項6之方法，其中藉由形成該強化層且接著將該強化層耦接至該載體而於該載體上形成該強化層。
  10. 如請求項6之方法，其中該基板包含一或多根導電跡線，該方法進一步包含曝露該開口中的該基板之該表面上之該等導電跡線中之至少一者，及將該晶粒耦接至該等曝露之導電跡線。
  11. 一種半導體裝置封裝總成，其包含：一底部封裝，其包含：一基板，其由一或多層介電材料所組成，該一或多層介電材料並具有一或多根導電跡線於該一或多層介電材料中；至少部分地覆蓋該基板之一頂表面的一強化層，該強化層係直接接觸於該基板之該頂表面，其中該強化層包含耦接至該基板且曝露於該強化層之一頂表面的一或多個端子，且其中該強化層包含曝露該基板之該頂表面之至少部分的一開口；及耦接至該基板之該頂表面的一晶粒，其中該晶粒位於該強化層中之該開口中；及一頂部封裝； 其中該頂部封裝耦接至該強化層中之該等端子中之一或多者。
  12. 如請求項11之總成，其中該頂部封裝包含一記憶體晶粒。
  13. 如請求項11之總成，其中該頂部封裝包含一印刷電路板，且其中該總成進一步包含耦接至該基板之一底表面的一記憶體晶粒。
  14. 如請求項11之總成，其中該強化層中之該開口曝露一端子墊圖案於該基板之該頂表面之至少一部分上，其中該晶粒耦接至該端子墊圖案，且其中該基板之該頂表面上的該端子墊圖案是由該基板之該頂表面處之一層介電材料中的該等導電跡線所定義，該頂表面處之該等導電跡線在該強化層中之該開口被形成時是暴露於該強化層中之該開口中。
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WO2015031030A1 (en) 2015-03-05
US20160172261A1 (en) 2016-06-16
JP2016529734A (ja) 2016-09-23
JP6271021B2 (ja) 2018-01-31
CN105493269B (zh) 2018-10-02
CN105493269A (zh) 2016-04-13

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