CN100390951C - 电子部件安装基板的制造方法 - Google Patents

电子部件安装基板的制造方法 Download PDF

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Publication number
CN100390951C
CN100390951C CNB038262207A CN03826220A CN100390951C CN 100390951 C CN100390951 C CN 100390951C CN B038262207 A CNB038262207 A CN B038262207A CN 03826220 A CN03826220 A CN 03826220A CN 100390951 C CN100390951 C CN 100390951C
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China
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circuit board
electrode
lamination portion
electronic unit
electrode part
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CN1759477A (zh
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阿部知行
山岸康男
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Fujitsu Ltd
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Fujitsu Ltd
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Abstract

电子部件安装基板(X)的制造方法包括升温工序和结合工序，所述升温工序是，将具有包含焊药的焊药凸点电极(31)的电子部件(30A)加热到高于焊药的熔点的第一温度，并将具有与焊药凸点电极(31)对应的电极部(21)的布线基板(X’)加热至低于第一温度的第二温度；所述结合工序是，对接焊要凸点电极(31)和电极部(21)，并相对于布线基板(X’)按压电子部件(30A)，以此来结合焊药凸点电极(31)和电极部(21)。

Description

电子部件安装基板的制造方法
技术领域
本发明涉及一种包括热膨胀率不同的布线基板和电子部件的电子部件安装基板的制造方法。
背景技术
近年来，随着对电子设备的高性能化以及小型化等的要求，组装到电子设备中的电子部件的高密度封装有了迅速的发展。为了适应这样的高密度封装，有时将半导体芯片以裸芯片的状态通过芯片凸块而面向布线基板进行封装，即倒装芯片封装。随着半导体芯片的多端子化，用于安装半导体芯片的布线基板有时在实现布线的高密度化的基础上采用适当的层积多层布线基板。这样的半导体芯片或层积多层布线基板记载在例如日本专利文献特开昭58-157146号公报以及“High-Performance Flip-Chip BGA basedon Multi-Layer Thin-Film Packaging Technology”(Tadanori SHIMOTO et al.，Proceedings of the 2002International microelectronics and Packaging Society，pp.10-15.)中。
用于在布线基板上倒装芯片封装半导体芯片的以往的方法中，首先在芯片的预定面上形成多个焊料凸点。另一方面，在布线基板所具有的外部连接用的电极衬垫上印刷锡药。接着，将芯片放置到布线基板上，使得布线基板的电极衬垫上的焊药与芯片的焊料凸点电极抵接。然后，在回流炉中将半导体芯片和布线基板升温至焊料的熔点以上的温度，然后冷却。在该冷却过程中，焊料凝固，从而将芯片和电极衬垫焊接在一起。
由一般的半导体母材制成的半导体芯片的面延展方向上的热膨胀率为3～5ppm/℃左右，采用环氧玻璃基板作为内层基板的一般的布线基板中，其面延展方向上的热膨胀率为10～20ppm/℃左右，两者的热膨胀率之差较大。除此以外，当布线基板具有层积多层布线结构时，该层积多层布线结构的面延展方向上的热膨胀率为15～25ppm/℃，该层积多层布线结构和芯片间的热膨胀率之差就相当大了。
因此，在倒装芯片封装过程中，芯片和布线基板经过相同峰值温度达到常温后，由于芯片和布线基板的热膨胀率之差，导致特别是在布线基板上产生不当的变形或起伏，从而易于在两者之间的电连接部产生应力。若在电连接部产生的应力高于预定应力，则在该连接部中芯片的凸点电极和布线基板的电极衬垫之间的界面等处易于产生裂缝或剥离。这种不好的现象在下述情况时有变显著的倾向，即：在对不具有内层基板的层积多层布线结构倒装芯片封装半导体芯片时，或在包括内层基板和层积多层布线结构的布线基板上，对不与层积多层布线结构中的内层基板连接的部位倒装芯片封装半导体芯片时。
发明内容
本发明是基于上述情况而想出的，其目的在于提供一种即使在半导体芯片等电子部件和布线基板的热膨胀率不同时，也能够对布线基板适当地安装电子部件从而制造电子部件安装基板的方法。
根据本发明的第一方面提供电子部件安装基板的制造方法。本方法包括：升温工序，用于将具有包含焊药的焊药凸点电极的电子部件加热至高于焊药的熔点的第一温度，并且，将具有与焊药凸点电极对应的电极部并具有高度比所述电极部高的隔垫的布线基板加热至低于第一温度的第二温度；和结合工序，用于通过使焊药凸点电极和电极部对接，且且将电子部件向布线基板按压，来结合焊药凸点电极和电极部。既可以在结束升温工序之后进行结合工序，也可并行进行两工序。当并行进行两工序时，一边分别加热电子部件和布线基板，一边在对接凸点电极和电极部的状态下相对于布线基板按压电子部件。
电子部件的热膨胀率和布线基板的热膨胀率一般是不同的，关于它们的差，多数情况下是布线基板的热膨胀率相当大，例如电子部件是半导体芯片，而布线基板是层积多层布线基板的情况。即使在电子部件和布线基板的热膨胀率相差比较大的情况下，也可根据本发明的第一方面的方法来给布线基板适当安装电子部件。
在本发明的第一方面的升温工序中，例如作为半导体芯片的电子部件和作为层积多层布线基板的布线基板被分别加热到预定的温度。该焊药凸点电极以及电子部件为了该焊药凸点电极所包含的焊药熔融而被加热至该焊药的熔点以上的第一温度。此时，电子部件整体处于与第一温度相应的膨胀状态。另一方面，该电极部以及布线基板被加热至低于第一温度的第二温度。此时，布线基板整体处于与第二温度相应的膨胀状态。假设第二温度下的布线基板的膨胀程度小于布线基板在第一温度时的膨胀程度。从而即使布线基板具有大于电子部件的热膨胀率，在升温工序中也能够抑制布线基板相对于电子部件的过度膨胀。此外，第二温度下的布线基板从布线基板没有被加热的常温状态开始膨胀。通过适当确定第一温度和第二温度，可适当调节布线基板相对于电子部件的热膨胀的程度。
在结束这样的升温工序之后而进行的结合工序中，或者在与这样的升温工序同时进行的结合工序中，可在布线基板适度膨胀的状态下，将布线基板的电极部和电子部件的凸点电极焊接在一起。从而可在焊接后冷却至常温的状态下抑制布线基板中的不当的变形或起伏，也可抑制在电子部件和布线基板之间的电连接部的应力。其结果，可避免在该连接部发生裂缝或剥离。
这样根据本发明的第一方面，即使当电子部件和布线基板的热膨胀率相差比较大时，也可相对于布线基板适当地安装电子部件，从而可适当制造电子部件安装基板。
在本发明的第一方面中，优选第二温度低于焊药的熔点。为了不使布线基板不适当地膨胀，最好是这样的结构。
优选在升温工序之前进一步包括给焊药凸点电极附着乙二醇、二缩三乙二醇或四甘醇的工序。这样的结构适合在升温工序中防止凸点电极的氧化。
优选布线基板具有由内层基板和层积部构成的层积结构。该内层基板具有容纳电子部件用的贯通孔，且该层积部具有由布线图和绝缘层构成的层积结构，并具有在贯通孔中露出的电极部。本结构的布线基板具有由布线图和绝缘层构成的例如层积多层布线结构。在结合工序中，使电子部件进入内层基板的贯通孔，并在电子部件存在于该贯通孔内的状态下对凸点电极和电极部进行焊接。该层积多层布线结构中的安装该电子部件的面没有被内层基板直接支撑，从而易于热膨胀。根据本发明的第一方面，即使对于这样的易于热膨胀的部位，也可适当安装电子部件。
根据本发明的第二方面提供电子部件安装基板的制造方法。本方法包括：在内层基板的隔离层上形成层积部，从而来制作布线基板的工序，其中所述内层基板具有包括内层和隔离层的层积结构，所述层积部具有由布线图和绝缘层构成的层积结构，并具有与隔离层相连接的电极部；针对内层，从层积部的相反侧实施蚀刻处理，从而去除内层的与电极部对应的部位的工序；针对隔离层，从层积部的相反侧实施蚀刻处理，从而使电极部露出，且在层积部的电子部件安装面上残留形成隔垫的工序；以及使电子部件和层积部之间有隔垫，并结合凸点电极和电极部，从而将具有凸点电极的电子部件安装到布线基板的工序。
根据这样的方法，可以适当制造将预定的电子部件容纳于内层基板内的电子部件安装基板。在本发明的第二方面中获得的布线基板具有包含内层和隔离层的内层基板以及与隔离层相结合的层积部。通过从层积部的相反侧开始的多个蚀刻处理，在内层基板中形成面向层积部的电极部的贯通孔。内层基板中的内层、隔离层以及有其他层存在时的其它层通过与之分别对应的蚀刻技术而被蚀刻处理。在对隔离层进行的蚀刻处理中，露出层积部的电极部，且残留形成隔垫。在电子部件的结合工序中，在内层基板的贯通孔内存在电子部件的状态下对电子部件和布线基板进行加热，并相对于层积部按压电子部件，从而将凸点电极和电极部焊接在一起。此时，由于在电子部件和层积部之间有先前形成的隔垫，所以可以防止电子部件和层积部过度接近。从层积部开始的隔垫的高度，即隔离层的厚度由电子部件的凸点电极的尺寸来确定。因此，防止了在焊接过程中对经过熔融状态的凸点电极作用不适当的负荷，从而可将电子部件相对于布线基板进行适当安装。
若给这样获得的电子部件安装基板的层积部，即层积多层布线结构的部件和贯通孔内的电子部件时降低两电子部件之间的布线电阻。这是由于可通过层积多层布线结构来将两芯片之间的布线长设计得较短。例如，当贯通孔内的电子部件是IC芯片，且后加电子部件是电容芯片时，可通过降低两芯片之间的布线电阻来充分抑制两芯片之间的信号噪声。
在本发明的第二方面中，优选内层基板具有在内层和隔离层之间有中间层的层积结构。此时，优选内层和隔离层由金属材料构成，且中间层为树脂材料构成。在这样的结构中，内层基板中相邻接的两层具有迥然不同的蚀刻特性。因此，这样的构成适于对内层基板适当地进行多个蚀刻处理。具体来说，最好在隔离层中残留形成隔垫，且在内层基板中开口设置容纳电子部件用的贯通孔。
优选凸点电极包含焊药，并在安装工序中将电子部件加热至高于焊药熔点的第一温度，且将布线基板加热至低于第一温度的第二温度，对接凸点电极和电极部，并相对于布线基板按压电子部件。根据这样的结构，基于与本发明的第一方面相关的上述理由的相同理由，可给布线基板的层积部适当安装电子部件，从而可适当制造电子部件安装基板。
附图说明
图1A至图1D表示本发明中的芯片安装基板制造方法中的一部分工序；
图2A至图2C表示图1D的后续工序；
图3A至图3C表示图2C的后续工序；
图4A和图4B表示图3C的后续工序；
图5A和图5B表示图4B的后续工序；
图6A至图6C表示图5B的后续工序；
图7A至图7C表示图6C的后续工序；
图8A和图8B表示图7C的后续工序；
图9A和图9B表示对布线基板安装芯片的过程；
图10表示在本发明中的芯片安装基板上进一步安装电子部件的状态；
图11表示本发明中的芯片安装基板具有散热器的状态。
具体实施方式
在本发明的芯片安装基板X的制造过程中，首先准备图1A所示的内层材料11。内层材料11为金属制造的基板，例如从钨、钼、锆、铬以及钽所组成的族中选择的金属单质，或包括从该族中所选金属的合金。或者内层基板11由42合金、不锈钢、科瓦铁镍钴合金、不胀钢或是具有铜/不胀钢/铜的层积结构的覆层材料来构成。内层材料11中面延展方向上的热膨胀率最好与所安装的半导体芯片等电子部件的热膨胀率相近似，例如为2～10ppm/℃。此外，内层材料11的厚度例如为0.1～2.0mm。
接着，如图1B所示，用粘着剂将隔离材料12粘贴到内层材料11上。粘着剂在内层材料11和隔离材料12之间硬化，从而构成中间层13。这样就制成了由内层材料11、中间层13以及隔离材料12构成的、具有第一面10a和第二面10b的内层基板10。隔离材料12为金属制造的板材或箔片，例如由铜、镍或铝构成。隔离材料12的厚度例如为30～100μm。中间层13由主要成分例如包括还氧树脂的热硬化树脂材料构成。中间层13的厚度例如为10～30μm。在内层基板10的面延展方向上的热膨胀率中，内层材料11的面延展方向上的热膨胀率是支配性的。
在本发明的芯片安装基板X的制造过程中，接着，如图1C所示，在隔离材料12上形成抗蚀图41。抗蚀图41具有与在下一工序中形成的电极衬垫的形状相对应的开口部41a。在抗蚀图41的形成过程中，首先将具有感光性的薄膜状的光刻胶碾压在隔离材料12上。接着，经过对该光刻胶膜的曝光处理及显影处理，在该光刻胶膜上形成开口部41a。这样就能够形成抗蚀图41。
在本发明的芯片安装基板X的制造过程中，接着，如图1D所示形成电极衬垫21。电极衬垫21是利用将隔离材料12用作通电层而进行的电镀法，通过在开口部41a的内部沉积预定的导电材料而形成的。例如，可通过在开口部41a的内部顺次沉积Ni、Au、Ni、Cu来形成电极衬垫21。除此之外，也可通过顺次沉积Au、Ni、Cu来形成电极衬垫21。取而代之，也可以通过顺次沉积Au、Ni、Cu来形成电极衬垫21。此时，参照图1C，在上述抗蚀图41的形成工序之前，通过电镀法在隔离材料11的露出面预先形成Ni镀膜。形成电极衬垫21时的最下层的Ni镀膜或在形成抗蚀图41之前形成的Ni镀膜作为抑制金属材料在隔离材料12和电极衬垫21的Au镀膜之间进行扩散的阻挡层来发挥作用。电极衬垫21中的Au镀膜与Cu镀膜之间的Ni镀膜作为抑制金属材料(Au、Cu)在该Au镀膜和Cu镀膜之间进行扩散的阻挡层来发挥作用。
接着，如图2A所示，从内层基板10上去除抗蚀图41。去除时，使用与抗蚀图41的组成相应的剥离液。
接着，如图2B所示，在内层基板10的第一面10a上层积形成绝缘层22，同时，在第二面10b上层积形成绝缘层22’。在绝缘层22的形成过程中，对薄膜状树脂合成物进行加热并加压使之与内层基板10结合。或用旋压覆盖法将液状树脂合成物涂布于内层基板10上，然后进行干燥。绝缘层22’的形成方法和绝缘层22的形成方法相同。作为绝缘层22、22’的构成材料，可以举出例如环氧树脂、聚砜、聚醚砜、聚苯基砜(polyphenylsulphone)、聚邻苯二甲酰胺、聚酰胺-酰亚胺、聚酮、缩醛树脂、聚酰亚胺、聚碳酸酯、改性聚苯醚、聚苯醚、聚对苯二甲酸二丁酯、聚甲基丙烯酸甲酯(ポリァクリレ一ト)、聚苯乙烯、聚苯硫醚、聚醚醚酮、全氟乙烯、氰酸酯、双马来酰亚胺等。
接着，如图2C所示，在绝缘层22的对应于电极衬垫21的部位形成通孔22a。通孔22a例如可用UV-YAG激光器、二氧化碳激光器、受激准分子激光器或使用等离子的干式蚀刻机来形成。或者可在绝缘层22具有感光性时由光刻法来形成通孔22a。
接着，通过无电解电镀法将预定的金属材料在绝缘层22、22’的露出面上成膜，从而形成晶层(省略图示)，之后如图3A所示，在对绝缘层22层积形成抗蚀图42的同时，对绝缘层22’层积形成抗蚀图43。晶层在之后进行的电镀方法中被用作通电层，此外在通孔22a的内壁上也行成有晶层。晶层例如是铜镀膜。抗蚀图42、43各自具有与形成在绝缘层22、22’上的布线图相对应的预定的图案形状。抗蚀图42、43的形成方法与抗蚀图41的形成方法相同。
接着，如图3B所示，将抗蚀图42、43作为掩模，利用电镀法在先前形成的晶层(省略图示)上沉积铜。由此在通孔22a上形成由铜构成的通路23，从而在绝缘层22、22’上没有被抗蚀图42、43所掩盖的部位形成铜镀膜。
接着，如图3C所示剥离抗蚀图42、43。之后蚀刻除去没有被电镀铜模所覆盖的箔层(省略图示)。由此，在绝缘层22上形成布线图24的同时，在绝缘层22’上形成布线图24’。
在芯片安装基板X的制造过程中，在内层基板10的第一面10a一侧重复预定次数的包括基于上述层积法的绝缘层22的形成、通孔22a的形成以及通路23和布线图24的形成在内的一连串的步骤，同时，在第二面10b一侧重复相同次数的包括基于层积法的绝缘层22’的形成、通孔22a’的形成以及通路23’和布线图24’的形成在内的一连串的步骤，由此来形成图4A所示的层积部20、20’。通孔22a’和通路23’的形成方法与通孔22a和通路23的形成方法相同。在本实施方式中，布线图24的层积数为5，且最外面的布线图24设有外部连接用的电极衬垫24a。
接着，如图4B所示，在层积部20的表面形成覆盖层25。覆盖层25对应于电极衬垫24a开口。在覆盖层25的形成过程中，首先利用印刷技术在层积部20上形成覆盖层用的感光树脂。然后利用光刻法形成预定的开口部。也可以在形成覆盖层25之后利用无电解电镀法在电极衬垫24a的露出面上形成例如Ni镀膜和其上的Au镀膜。
在芯片安装基板X的制造过程中，接着，如图5A所示，设有覆盖层25的层积部20被保护膜44所覆盖。保护膜44例如由干膜抗蚀层组成。
接着，如图5B所示，例如通过研磨等机械加工除去层积部20’。由此使内层基板10的内层材料11露出。在本发明中，取而代之，对于层积部20’也可通过NC切削或激光加工仅除去与后来芯片安装区域相当的部位。
接着，如图6A所示，在内层基板10的内层材料11上形成抗蚀图45。抗蚀图45在对应于电极衬垫21的部位具有开口部。抗蚀图45的形成方法和抗蚀图41的形成方法相同。
接着，如图6B所示，以抗蚀图45为掩模，对内层材料11进行蚀刻处理，直至露出中间层13。在本工序中，根据内层材料11的构成材料，蚀刻液例如可以使用氯化亚铁水溶液、氟化酸或玉水(玉水)等。蚀刻处理之后，剥离抗蚀图45。
接着，如图6C所示，以内层材料11为掩模对中间层13进行蚀刻处理，直至露出隔离材料12。本工序以干蚀刻进行。作为干蚀刻，可以例举出反应离子蚀刻(RIE)、离子磨削。
接着，如图7A所示，在隔离材料12上形成抗蚀图46。抗蚀图46用于掩盖隔离材料12上后来形成隔垫的部位。在抗蚀图46的形成过程中，首先将具有感光性的墨水类型(液体)的光刻胶涂布在隔离材料12的露出面上，并例如在80℃下干燥30分钟。接着，经过对该光刻膜进行曝光处理以及显影处理，从而在该光刻胶膜上形成预定的图案。由此可以形成抗蚀图46。
接着，如图7B所示，以抗蚀图46为掩模对隔离材料12进行蚀刻处理，直至充分露出电极衬垫21。由此在内层基板10中形成容纳芯片用的贯通孔10c，从而露出层积部20中的芯片安装区域20a。与此同时，在芯片安装区域20a的上面形成隔垫12a。在本工序中，根据隔离材料12的构成材料，蚀刻液例如可以使用氯化铜水溶液等。之后如图7C所示剥离抗蚀图46。然后将该基板分割成单片即封装尺寸。由此形成布线基板X’。
接着，如图8A所示，将具有外部连接用的凸点电极31的半导体芯片30A安装到布线基板X’上。即，将半导体芯片30A倒装芯片封装到布线基板X’上。凸点电极31整体由焊药构成。或者凸点电极31例如由铜等的芯球和覆盖该芯球的焊药构成。
在芯片安装工序中，首先如图9A所示，将半导体芯片30A固定到加热板51上，并将布线基板X’固定到加热板52上，之后通过吸附头53吸附加热板51并操作该吸附头53，从而使半导体芯片30A相对于布线基板X’定位。加热板51具有可调节温度的发热功能，从而通过该加热板51将半导体芯片30A加热到第一温度。第一温度高于凸点电极31所包含的焊药的熔点。加热板52具有可调节温度的发热功能，从而通过该加热板52将布线基板X’加热到第二温度。第二温度低于第一温度，并低于凸点电极31所包含的焊药的熔点。此外，在加热板51加热半导体芯片30A之前，预先在半导体芯片30A的凸点电极31上涂布抗氧化剂54。抗氧化剂54可以使用乙二醇、二缩三乙二醇或四甘醇。
在芯片安装步骤中，接着，如图9B所示，通过操作吸附头53而在凸点电极31和电极衬垫21相抵接的状态下，将半导体芯片30A压向布线基板X’。在按压状态下对半导体芯片30A和凸点电极31进行温度调节，使它们经过第一温度，由此，凸点电极31的焊药曾一度经过熔融状态。因此，经过本工序的凸点电极31和电极衬垫21被焊接在一起。焊接时，附着在凸点电极31上的抗氧化剂54蒸发。
在这样的芯片安装工序中，半导体芯片30A和布线基板X’被分别加热。该缓冲电极31以及半导体芯片30A为了使该凸点电极31所包含的焊药熔融而被加热至该焊药的熔点以上的第一温度。此时半导体芯片30A整体处于与第一温度相应的膨胀状态。另一方面，该电极衬垫21以及布线基板X’被加热至低于第一温度的第二温度。此时半导体基板X’整体处于与第二温度相应的膨胀状态。从而在半导体芯片30A和布线基板X’的升温过程中能够防止布线基板X’相对于半导体芯片30A过度膨胀。
在芯片安装工序中，当结合凸点电极31和电极衬垫21时，可以在布线基板X’适度膨胀的状态下进行焊接。从而可以在焊接后冷却至常温的状态下抑制布线基板X’中的不当的变形或起伏，从而可抑制由半导体芯片30A和布线基板X’之间的凸点电极31和电极衬垫21组成的电连接部产生应力。其结果，可以避免该连接部的裂缝或剥离，从而可以在半导体芯片30A和布线基板X’之间获得高的连接可靠性。
除此之外，在芯片安装工序中，由于在半导体芯片30A和层积部20之间隔有隔垫12a，所以可防止半导体芯片30A和层积部20过于接近。从层积部20开始的隔垫12a的高度、即隔离层12的厚度是根据半导体芯片30A的凸点电极31的尺寸来确定的。因此，防止在焊接过程中对经过熔融状态的凸点电极31作用不适当的负荷，从而能够将半导体芯片30A相对于布线基板X’进行适当安装。
在芯片安装基板X的制造过程中，接着，如图8B所示，在内层基板10的贯通孔10c中填充底部填充剂55。在底部填充剂55充满半导体芯片30A和层积部20之间的同时，密封半导体芯片30A。这样的底部填充剂55具有缓和在凸点电极31和电极衬垫21所组成的电连接部产生的应力的作用。通过该应力缓和功能，可以确保该倒装芯片封装中的连接可靠性。
如上制造由布线基板X’和半导体芯片30A组成的芯片安装基板X。
在芯片安装基板X中，如图10所示安装有半导体芯片30B。半导体芯片30B具有外部连接用的凸点电极32。凸点电极32整体由焊药构成。或者凸点电极32例如由铜等的芯球和覆盖该芯球的焊药构成。可通过与上述的半导体芯片30A安装方法相同的方法将半导体芯片30B安装在芯片安装基板X上。在安装状态下，凸点电极32和电极衬垫24a熔融结合直到被焊接在一起。
这样，若在芯片安装基板X上安装半导体芯片30B，则可在电连接半导体芯片30B和半导体芯片30A时降低两芯片之间的布线电阻。这是由于可通过层积部20的微细布线结构来将两芯片之间的布线设计得较短。例如，当半导体芯片30A是IC芯片，且半导体芯片30B是电容芯片时，可通过降低两芯片之间的布线电阻来充分抑制两芯片之间的信号噪声。
如图11所示，也可在芯片安装基板X中安装散热器56。散热器56用于散发在半导体芯片30A中产生的热，并通过预定的粘着剂57连接到内层基板10和半导体芯片30A上。当半导体芯片30A是IC芯片时，芯片安装基板X具有这样的散热器56的结构特别有实际效益。IC芯片在驱动时所产生的热量比较多。
在本实施方式中，在对内层材料11进行蚀刻处理之前，将全部层积部20当作无效(dummy)层积部，并通过机械研磨除去。取而代之，在本发明中也可将层积部20’的一部分留在内层基板10上，并将该残留部所包含的布线结构用作所形成的芯片安装基板X的布线结构的一部分。参照图5B，此时在上述步骤中不去除全部的层积部20’，而只是去除相当于芯片安装区域20a的部分。作为层积部20’的部分去除方法，可采用例如NC切削或激光加工。
(实施例)
在本实施例的芯片安装基板的制作过程中，首先制作内层基板。在内层基板的制作中，具体来说，将作为隔离材料的电解铜箔(厚度：70μm)通过作为构成中间层的粘着剂的还氧树脂片(商品名：ABF，味之素精密技术公司(Ajinomoto Fine-Techno Co.，)制造)粘贴在作为内层材料的42合金板(平面尺寸：150mm×150mm、厚度：0.5mm)上。42合金板的组成为Fe-42wt％Ni。
在芯片安装基板的制作中，接着通过电镀法在电解铜箔上形成Ni镀膜。接着经由Ni镀膜在电解铜箔上形成抗蚀图。该抗蚀图具有多个与在下一工序中形成的电极衬垫的形状相对应的开口部。在抗蚀图的形成过程中，首先将具有感光性的干膜抗蚀层(商品名：NIT-240，日合モ一トン制造)贴到电解铜箔上。接着经过对该光刻胶膜进行曝光处理和显影处理，从而在该光刻胶膜上形成开口部。
在芯片安装基板的制作过程中，接着，在抗蚀图的各个开口部形成电极衬垫。具体来说，利用电镀法在各个开口部的内部顺次形成Au镀膜(厚度：1μm)、Ni镀膜(厚度：5μm)和Cu镀膜(厚度：15μm)，从而形成电极衬垫。形成电极衬垫之后，通过使作为剥离液的3wt％氢氧化钠水溶液发挥作用，将抗蚀图从电解铜箔上剥离。以下，在内层基板中形成该电极衬垫一侧的面为第一面，该第一面相反侧的面为第二面。
接着在内层基板的两面形成绝缘层。具体来说，首先使用真空层压法压接还氧树脂片(平面尺寸：200mm×200mm、厚度：50μm、商品名：ABF，味之素精密技术公司(Ajinomoto Fine-Techno Co.，)制造)。压接温度为130℃，压接时间为2分钟。之后在170℃下加热30分钟，由此使还氧树脂硬化。
接着，在第一面一侧的绝缘层中与上述电极衬垫对应的部位，通过二氧化碳激光形成多个通孔(直径：60μm)，以便露出各个电极衬垫的一部分。
接着，使用半添加法在两面的绝缘层上形成铜布线图案。此时，在第一面一侧的绝缘层中的通孔的表面上也沉积铜，从而在该通孔中也形成通路。具体来说，首先在各绝缘层表面和通孔表面实施除污处理，之后利用无电解电镀法在绝缘层和通孔的表面形成无电解电镀铜膜。在除污处理中使用含有高锰酸盐的水溶液。接着，在无电解铜镀膜上形成光刻胶膜，之后通过对该光刻胶膜进行曝光和显影来形成抗蚀图。该抗蚀图具有与以形成为目的的布线图对应的图案形状。接着利用电镀法，在没有被抗蚀图掩盖的无电解镀膜上将无电解铜镀膜用作箔层来沉积电镀铜。接着在去除抗蚀图之后，蚀刻去除一直被抗蚀图覆盖的无电解铜镀膜。通过这样的半添加法，在两侧绝缘层上形成布线图案的同时，在第一面一侧的绝缘层的通孔中形成通路。
之后，通过在内层基板的两面进一步重复四次从绝缘层的层积形成到布线图案以及通路的形成的上述一连串的工序，从而在内层基板的两面形成五层布线结构的层积部。
接着通过丝网印刷和光刻法，在第一面一侧的层积部的表面形成覆盖层。在覆盖层的预定部位设置开口部，以便层积部中的位于最上的布线图案的一部分作为电极衬垫露出。接着利用无电解电镀法在电极衬垫的露出面上顺次形成Ni镀膜(厚度：5μm)及其上面的Au镀膜(厚度：0.1μm)。
接着，由作为保护膜的干膜抗蚀层覆盖第一面一侧的层积部，之后研磨去除第二面一侧的层积部。由此露出内层基板的内层材料(42合金板)。接着，在内层材料中露出的表面上形成抗蚀图。该抗蚀图在对应连接内层基板而形成的上述电极衬垫的部位，即对应芯片安装区域的部位具有开口部。
接着，将该抗蚀图作为掩模来对内层材料进行蚀刻处理，直至露出中间层。作为蚀刻液，使用氯化亚铁水溶液。接着通过使用氧气的RIE，将内层材料作为掩模来对中间层进行蚀刻处理，直至露出隔离材料(电解铜箔)。接着，在隔离材料中露出的表面上形成抗蚀图。该抗蚀图用于掩盖在隔离材料中形成隔垫的部位。
接着，将该抗蚀图作为掩模来对隔离材料进行蚀刻处理，直至第一面一侧的最下层的绝缘层以及埋置于该绝缘层中的电极衬垫充分露出。作为蚀刻液，使用氯化铜水溶液。由此在内层基板上形成容纳芯片用的贯通孔，从而在层积部的内层基板一侧露出芯片安装区域。同时在芯片安装区域上形成隔垫。接着剥离用于形成隔垫的抗蚀图。之后将该基板分割成单片，即封装尺寸。如此来形成芯片安装用的多个布线基板。
接着，对布线基板来倒装芯片封装另外准备的半导体芯片。该半导体芯片具有外部连接用的凸点电极。该凸点电极对应布线基板的电极衬垫而设置，并由焊药(组成：Sn-3wt％Ag-0.5wt％Cu、熔点：220℃)构成。
在芯片安装步骤中，首先将半导体芯片固定到第一加热板上，之后通过吸附头来吸附第一加热板，并且在该半导体芯片的凸点电极上涂布作为抗氧化剂的乙二醇。另一方面，将布线基板固定在第二加热板上。第一和第二加热板具有可调节温度的功能。接着，通过第一加热板将半导体芯片加热至255℃，且通过第二加热板将布线基板加热至150℃。接着通过操作吸附头，在半导体芯片的凸点电极和布线基板的电极衬垫对接的状态下，相对于布线基板来按压半导体芯片。在按压状态下，停止第一和第二加热板的加热，从而使半导体芯片和布线基板的温度下降并充分冷却。由此将半导体芯片的凸点电极和布线基板的电极衬垫焊接在一起。
接着，在内层基板的贯通孔中填充底部填充剂，密封半导体芯片。此时，底部填充剂也被填充到半导体芯片和层积部之间。通过以上就制成了本实施例的芯片安装基板。

Claims (5)

1.一种电子部件安装基板的制造方法，包括：
升温工序，用于将具有包含焊药的焊药凸点电极的电子部件加热至高于所述焊药的熔点的第一温度，并且，将具有与所述焊药凸点电极对应的电极部并具有高度比所述电极部高的隔垫的布线基板加热至低于所述第一温度的第二温度；和
结合工序，用于通过使所述焊药凸点电极和所述电极部对接，且将所述电子部件向所述布线基板的隔垫按压，来结合所述焊药凸点电极和所述电极部。
2.如权利要求1所述的电子部件安装基板的制造方法，其中，
所述第二温度低于所述焊药的熔点。
3.如权利要求1所述的电子部件安装基板的制造方法，还包括：
在所述升温工序之前，给所述焊药凸点电极附着乙二醇、二缩三乙二醇或四甘醇的工序。
4.如权利要求1所述的电子部件安装基板的制造方法，其中，
所述布线基板具有由内层基板和层积部构成的层积结构，所述内层基板具有容纳电子部件用的贯通孔，所述层积部具有由布线图和绝缘层构成的层积结构，且具有在所述贯通孔中露出的所述电极部。
5.一种电子部件安装基板的制造方法，包括如下工序：
在内层基板的隔离层上形成层积部，从而来制作布线基板，其中所述内层基板具有包括内层和隔离层的层积结构，所述层积部具有由布线图和绝缘层构成的层积结构，并具有与所述隔离层相连接的电极部；
针对所述内层，从所述层积部的相反侧实施蚀刻处理，从而去除所述内层的与所述电极部对应的部位；
针对所述隔离层，从所述层积部的相反侧实施蚀刻处理，从而使所述电极部露出，且在所述层积部的电子部件安装面上残留形成隔垫；以及
使所述电子部件和所述层积部之间有所述隔垫，并结合凸点电极和所述电极部，从而将具有凸点电极的电子部件安装到所述布线基板。
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CN1759477A (zh) 2006-04-12
JP4057589B2 (ja) 2008-03-05
US7595228B2 (en) 2009-09-29
TW591765B (en) 2004-06-11

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