TW591765B - Method of making electronic element-mounted substrate - Google Patents

Method of making electronic element-mounted substrate Download PDF

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Publication number
TW591765B
TW591765B TW092107132A TW92107132A TW591765B TW 591765 B TW591765 B TW 591765B TW 092107132 A TW092107132 A TW 092107132A TW 92107132 A TW92107132 A TW 92107132A TW 591765 B TW591765 B TW 591765B
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TW
Taiwan
Prior art keywords
substrate
layer
electrode
wiring
electronic component
Prior art date
Application number
TW092107132A
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English (en)
Other versions
TW200419737A (en
Inventor
Tomoyuki Abe
Yasuo Yamagishi
Original Assignee
Fujitsu Ltd
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Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
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Publication of TW591765B publication Critical patent/TW591765B/zh
Publication of TW200419737A publication Critical patent/TW200419737A/zh

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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
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    • H05K2203/04—Soldering or other types of metallurgic bonding
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494—Heating methods for reflowing of solder
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

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玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明） 【發明所屬之技術領域】 發明領域 本發明係有關於一種包含有不同熱膨脹率之配線基板 5 與電子零件之電子零件搭載基板。 C 先前 背景技術 近年來’隨著電子機器趨向高性能化及小型化等，組 裝入電子機器之電子零件係急速地邁向高密度封裝化。為 10 了配合如此之高密度封裝化，半導體晶片係以裸晶片之狀 態透過凸塊封裝於配線基板，即，倒裝晶片封裝。有關於 用以搭載半導體晶片之配線基板，係配合半導體晶片之多 端子化而採用在適於達到配線之高密度化之增層式多層配 線基板。前述半導體晶片或增層式多層配線基板，例如， 15 揭示於曰本專利公開公報58-157146號中，及“High-Performace Flip-Chip BGA based on Multi-Layer Thin Film Packing Technology”（Tadanori SHIMOTO et al·，Proceedings of the 2002 International Microelectronics and Packing Society, pp.10-15·)中。 20 以往用以將半導體晶片封裝於配線基板之以倒裝晶片 法封裝之方法中，首先，係於晶片之預定面上形成多數焊 料凸塊電極。且，於配線基板所具有之用以連接外部之電 極接合點上印刷焊膏。接著，將晶片載置於配線基板上， 並使配線基板中之電極接合點上之焊膏抵接晶片之焊料凸 6 玖、發明說明 塊電極。然後’以回流爐將半導體晶片及配線基板昇溫至 呵於焊接材料之熔點之溫度後冷卻。於該冷卻過程中，焊 接材料凝固’晶片與電極接合點焊接接合。 由一般之半導體母材料構成之半導體晶片中之面寬方 向之熱膨脹率係3〜5ppm厂C左右，而採用玻璃環氧基板作 為核心基板之一般之配線基板中之面寬方向之熱膨脹率係 〜20ppm/°C左右，兩者之熱膨脹率之差較大。另外，配 線基板具有增層式多層配線構造時，該增層式多層配線構 造之面寬方向中之熱膨脹率係15〜25ppm/°C，該多層配線 構造與晶片之熱膨脹率之差非常大。 因此’晶片及配線基板於以倒裝晶片法封裝之過程中 ，歷經同一峰值溫度並到達常溫後，由於晶片及配線基板 之熱膨脹率之差，特別是於配線基板中，會產生不良之彎 曲或起伏’而容易於兩者之間之電性連接部產生應力。於 電性連接部產生超過所需之應力時，於該連接部中之晶片 之凸塊電極與配線基板之電極接合點之界面等容易產生破 裂或剝落。如此之不良情況特別容易發生於對沒有具有核 心基板之增層式多層配線構造以倒裝晶片法封裝半導體晶 片時，或於含有核心基板及增層<多層配線構造之配線基 板中’對增層式多層配線構造中沒有連接核心基板之部位 以倒裝晶片法封裝半導體晶片之情況下。 【智?^明内溶^】 發明揭示 本發明係基於前述情形而研究出者，其目的係提供一 玖、發明說明 種即使半導體晶片等電子零件與配線基板之熱膨脹率不同 時，仍可適當地將電子零件搭載於配線基板而製造電子零 件搭載基板之方法。 本發明之第1方面係提供電子零件搭載基板之製造方 5 法。該方法係包含有昇溫步驟及接合步驟，前述昇溫步驟 係將具有含有焊接材料之焊料凸塊電極之電子零件加熱至 較前述焊接材料之熔點還高之第1溫度，且，將具有對應 前述焊料凸塊電極之電極部之配線基板加熱至較前述第1 ✓JHL度還低之第2溫度，而前述接合步驟則係使前述焊料凸 10塊電極抵接前述電極部並且將前述電子零件按壓於前述配 線基板上，藉此接合前述焊料凸塊電極及前述電極部。可 於昇溫步驟結束後進行接合步驟，亦可同時進行兩步驟。 同時進行兩步驟時，係一面個別加熱前述電子零件及該配 線基板，一面於前述焊料凸塊電極及該電極部相抵接之狀 15態不將前述電子零件按壓於該配線基板上。 一般而言，電子零件之熱膨脹率及配線基板之熱膨脹 率係不同的，其差距於如電子零件為半導體晶片，配線基 板為增層式多層配線基板時，配線基板大多大很多。即使 電子零件及配線基板之熱膨脹率如前述相差很大時，依據 2〇本發明之第1方面之方法，可適當地將電子零件搭載於配 線基板。 於本發明之第1方面之昇溫步驟中，諸如半導體晶片 之電子零件，及諸如增層式多層配線基板之配線基板係個 別地加熱至預定溫度。隨著電子零件加熱，其焊料凸塊電 8 玖、發明說明 極係加熱至可使該焊料凸塊電極中所含之焊接材料暫時溶 融之高於該焊接材料之㈣的第1溫度。此時，電子零件 整體係對應於帛i溫度而膨脹。另外，隨著配線基板加熱 ，其電極部係加熱至較第i溫度還低之第2溫度。此時， 該配線基板整體係對應於第2溫度而賴。加熱至第2溫 度時之前述配線基板之膨脹程度係較假設將該配線基板加 熱至第1溫度時之膨脹程度小。因此，即使該配線基板具 有較刖述電子零件還大之熱膨脹率時，還是可於昇溫過程 中防止该配線基板相對於前述電子零件過度膨脹之情形。 又，加熱至第2溫度之前述配線基板係由無法加熱該配線 基板之常溫下之狀態開始膨脹。藉適當地決定第1溫度及 第2溫度，可適當地調整該配線基板相對於前述電子零件 之熱膨脹之程度。 於結束如此之昇溫過程後進行之接合步驟中，或於與 如此之昇溫過程同時進行之接合步驟中，可於該配線基板 業已適當地膨脹之狀態下，將前述配線基板之該電極部與 前述電子零件之該焊料凸塊電極焊接接合。因此，可防止 焊接接合後冷卻至常溫之狀態時，該配線基板令之不良彎 曲或起伏’及前述電子零件及該配線基板之間之電性連接 部中產生應力。其結果為可避免該連接部中產生破裂或剝 落。 如此一來，依據本發明之第丨方面，即使該電子零件 及刖述配線基板之熱膨脹率相差甚鉅時，仍可適當地將該 電子零件搭載於前述配線基板，因此，可適當地製造電子 玖、發明說明 零件搭載基板。 本發明之第1方面中，第2溫度宜較焊接材料之熔點 還低。為了使該配線基板不會不當地膨脹，如此之構成係 恰當的。 且宜於昇溫步驟前更包含有使乙二醇、三甘醇、四甘 醇附著於前述焊料凸塊電極之步驟。如此之構成係有助於 防止昇溫過程中該凸塊電極氧化。 且，該配線基板係以具有由核心基板及增層部構成之 積層構造為佳。該核心基板係具有用以收容前述電子零件 之貫通孔，前述增層部則係具有由配線圖案及絕緣層構成 之積層構造且具有由該貫通孔露出之電極部。本結構之配 線基板係具有由配線圖案及絕緣層構成之諸如增層式多層 配線構造。接合步驟係使前述電子零件進入該核心基板之 前述貫通孔，並於該貫通孔内具有該電子零件之狀態下， 進行刖述凸塊電極與前述電極部之焊接接合。該增層式多 層配線構造中純該電子零件m系沒有由前述核心基 板直接支撐，容易熱膨脹。根據本發明之第丨方面，亦可 適當地將該電子零件搭載於前述容易熱膨脹之部位， 本發明之第2方面係提供另一電子零件搭載基板之製 造方法。該方法係於具有包含有核心層及分隔層之積層構 造之核心基板中之分隔層上，形成具有由配線圖案及絕緣 層構成之積層構造且具有連接前述分隔層之電極部的增層 部，藉此製作配線基板之步驟，與由相對於前述增層部之 側對前述核心層施行_處理，藉此除去該核心層中對應 591765 玖、發明說明 月ϋ述電極部之處之步驟’由相對於前述增層部之側對前述 分隔層施行蝕刻處理，藉此使前述電極部露出，且，於前 述增層部中之電子零件搭載面上殘留形成分隔物之步驟， 及使該電子零件及前述增層部之間隔著前述分隔物接合凸 5塊電極及前述電極部，藉此將具有前述凸塊電極之前述電 子零件搭載於前述配線基板之步驟。 依據如此之方法，可適當地製造於核心基板内收容有 預疋之電子零件之電子零件搭載基板。本發明之第2方面 · 中得到之配線基板，係具有含有核心層及分隔層之核心基 10板，與接合分隔層之增層部。於核心基板中，藉多數自相 對於增層部之側蝕刻之蝕刻處理，形成朝向增層部之電極 4的貫通孔。核心基板中之核心層、分隔層、及有時存在 之其他層，係藉分別對應之蝕刻技術進行蝕刻處理。於分 隔層進行之蝕刻處理，係使增層部之電極部露出，且殘留 15形成分隔物。電子零件之接合步驟中，係於核心基板之貫 通孔内具有電子零件之狀態下，加熱電子零件及配線基板 ，且按壓電子零件於增層部，而焊接接合凸塊電極與電極 部。此時，由於電子零件與增層部之間隔著先前形成之分 - 隔物，因此，可防止電子零件及增層部過度接近。由增層 - 20 部高起之分隔物之高度，即分隔層之高度，係配合電子零 件之凸塊電極之尺寸而決定。因此，於焊接接合之過程中 ，可防止不良之負荷作用於歷經熔融狀態之凸塊電極，而 可適當地將電子零件搭載於配線基板。 於如此得到之電子零件搭載基板之增層部，即增層式 11 591765 玖、發明說明 夕層配線構造中’於相對於核心基板之側之露出面再搭載 電子零件時，可降低該追加之電子零件與貫通孔内之電子 · 零件電性地連接時兩電子零件間之配線抗阻。這係因為兩 · 電子零件間之配線長度可透過增層式多層配線構造設計成 5短。例如，貫通孔内之電子零件為IC晶片，且追加之電子 零件為電容晶片時，藉兩晶片間之配線抗阻之降低，可充 分地防止兩晶片間之信號干擾。 本發明之第2方面中，核心基板係以具有於核心層及 · 分隔層之間間隔有中間層之積層構造為佳。此時，係以該 1〇核心層及刖述分隔層由金屬材料構成，而該中間層由樹脂 材料構成為佳。如此之結構中，於該核心基板中相接鄰之 2層係充分地具有不同之蝕刻特性。因此，如此之構成係 適於在前述核心基板中進行多數蝕刻處理。具體而言，係 有助於在該分隔層中殘留形成分隔物，且在該核心基板中 15開設用以收容電子零件之貫通孔。 且凸塊電極係以包含有焊接材料為佳，且宜於搭載過 · 权中’將該電子零件加熱至較前述焊接材料之溶點還高之 第1溫度，且，將配線基板加熱至較前述第1溫度還低之 第2溫度’並一面使該凸塊電極及電極部抵接一面按壓前 ‘ 20述電子零件至前述配線基板上。依據如此之構成，基於與 本發明之第1方面有關之前述相同理由，可適當地將該電 - 子零件載置於前述配線基板之前數增層部，因此，可適當 地製造電子零件搭載基板。 圖式簡單說明 12 59口65 玖、發明說明 第1A圖〜第1D圖係顯示本發明之晶片搭載基板之製 造方法中之一部份步驟。 第 9 Δ 圓 a 〜第2C圖係顯示接續第id圖之步驟。 第3A圖〜第3C圖係顯示接續第2c圖之步驟。 5 第々A圖〜第4B圖係顯示接續第3c圖之步驟。 第5A圖〜第5B圖係顯示接續第4B圖之步驟。 第6A圖〜第6C圖係顯示接續第5B圖之步驟。 第7A圖〜第7C圖係顯示接續第6c圖之步驟。 第8 A圖〜第8B圖係顯示接續第7c圖之步驟。 10 第9A圖及第9B圖係顯示將晶片搭載於配線基板之過 程。 第丨〇圖係顯示於晶片搭載基板上更搭載有電子零件之 狀態。 第U圖係顯示本發明之晶片搭載基板具有散熱體之狀 15態。 L實施方式；j 實施發明之最佳形態 製造本發明之晶片搭載基板X時，首先，準備第1A 圖所示之核心材料11。核心材料n係金屬製之基板，例 20如，由自鎢、鉬、鍅、鉻、及鈕構成之群選出之單體金屬 ,或包含有自該群選出之金屬之合金構成者。或者，核心 基板11係由42合金、不鏽鋼、柯伐、不變鋼、或具有鋼/ 不變鋼/銅之積層構造之護面材料構成。核心材料u中之 面寬方向之熱膨脹率係以接近所搭載之半導體晶片等之電 13 591765 玖、發明說明 子零件之熱_率者為佳，例如2〜iGppmrc。又枝 料η之厚度係諸如為o.W.—。 ^材 接者’如第1B圖所示，透過黏著劑黏貼分隔 於核心材料u。黏著劑係於核心材料u及分隔材料 5間硬化並形成中間層13。如此地製成由核心 層13、及分隔材料12構成之具有第1面他及第2面1% 之核心基板10。分隔材料12係金屬製之板材或箱材 如由銅、錦、或銘構成。分隔材料12之厚度係例如 3二〇—。中間層13係由包含有主要成分之諸如環氧樹 10脂等熱硬化性樹脂材料構成。中問屏 10〜30μιη。核心基板1〇 9 之旱度係例如 板10之©寬方向之熱膨脹率係受核 料11中之面寬方向之熱膨脹率支配。 製造本發明之q搭餘板X中，接著，如第1C0 15 所不’於分隔材料12上形成抗钮圖案41。抗㈣宰則 具有對應下-步驟中形成之電極接合點之形狀之開口部 _ —。抗_案41之形成中’首先’係將具有感光性之薄 膜狀之光μ層於分隔材料12。接著，對該光阻膜進行曝 光處理及顯像處理後，於該光阻膜中形成開口部41a。如 此，可形成抗蝕圖案41。 20 製造晶片搭載基板x中，接著’如第m圖所示，形 成電極接合點21。電極接合點η係藉使分隔材料12作為 通電層並利用其進行電鍍法，且使開口 ^ 定之導電材料形成者。例如，乒 a内部堆積預 稭於開口部4la内部依序堆 積mCu可形成電極接合點21。亦可藉依序堆 14 591765 玖、發明說明 積Au、Ni、Cu加以替代，而形成電極接合點21。此時， 參照第1C圖於前述抗蝕圖案41之形成步驟前，藉電鍍法 - 於分隔材料12之露出面預先形成Ni鍍膜。形成電極接合 - 點21時之最下層之Ni鍍膜，或於形成抗蝕圖案41前形成 5 之Ni鍍膜，係於分隔材料12與電極接合點21之Au鍍膜 之間作為防止金屬材料擴散之阻擋層而發揮功效。電極接 合點21中之Au鍍膜與Cu鍍膜之間之Ni鍍膜，則係於該 Au鍍膜與Cu鍍膜之間作為防止金屬材料（Au、Cu)擴散之 · 阻擋層而發揮功效。 10 接著，如第2A圖所示，將抗蝕圖案41由核心基板10 除去。於除去時，使用配合抗蝕圖案41之組成之剝離液。 接著，如第2B圖所示，於核心基板10之第1面10a上積 層形成絕緣層22，且於第2面10b上積層形成絕緣層22’ 。絕緣層22之形成係一面加熱薄膜狀樹脂組成物，一面將 15 其壓著於核心基板10。或藉旋轉塗布法塗布液狀樹脂組成 物於核心基板10上，然後進行乾燥。絕緣層22’之形成手 # 法係與絕緣層22之形成手法相同。絕緣層22、22’之構成 材料，例如可舉例有環氧、聚颯物、聚醚颯、聚苯颯、聚 w 鄰苯二甲酸胺、聚醚胺亞胺、聚酮、聚縮醛、聚醯亞胺、 - 20 聚碳、變性聚苯醚、聚氧化醚、聚對苯二甲酸二丁酯、聚 丙烯酸酯、聚颯、聚苯硫、聚醚醚酮、四氣乙烯、氰酸鹽 酯、雙馬來醯亞胺等。 接著，如第2C圖所示，於絕緣層22中對應電極接合 點21之處形成通孔22a。通孔22a，舉例而言，可藉UV- 15 玖、發明說明 YAG雷射、二氧化碳雷射、激生分子雷射、或藉利用電漿 之乾蝕刻形成。或者，通孔22a於絕緣層22具有感光性時 ，可藉微影成像術形成。
接著，藉無電解電鍍法於絕緣層22、22’之露出面使 5 金屬材料成膜而形成晶種層（圖示省略）後，如第3A圖所示 ，於絕緣層22積層形成抗蝕圖案42，且於絕緣層22’積層 形成抗蝕圖案43。晶種層係於之後進行之電鍍法中作為通 電層以供利用，且亦形成於通孔22a之内壁上。晶種層係 諸如銅鍍膜。抗蝕圖案42、43係具有對應分別之絕緣層 10 22、22’上形成之配線圖案之預定的圖案形狀。抗蝕圖案 42、43之形成手法，係與抗蝕圖案41之形成手法相同。 接著，如第3B圖所示，以抗蝕圖案42、43作為屏蔽 ，藉電鍍法於已事先形成之晶種層（圖示省略）上堆積銅。 藉此，於通孔22a形成由銅構成之孔23，並於絕緣層22、 15 22’中沒有受抗蝕圖案42、43遮蔽之部位形成電性銅鍍膜
〇 接著，如第3C圖所示，剝離抗蝕圖案42、43。然後 ，蝕刻除去電性銅鍍膜所沒有包覆之晶種層（圖示省略）。 藉此，於絕緣層22上形成配線圖案24，且於絕緣層22’上 20 形成配線圖案24’。 製造晶片搭載基板X中，將藉如此之增層法形成絕緣 層22、形成通孔22a，與形成孔23及配線圖案24之一連 串之過程，於核心基板10之第1面10a之側重複預定次數 ，且將包含有藉增層法形成絕緣層22’、形成通孔22a’、 16 591765 玖、發明說明 與形成孔23’及配線圖案24’之一連串過程於第2面10b之 側重複相同次數，藉此形成如第4A圖所示之增層部20、 · 20’。通孔22a’、及孔23’之形成手法係與通孔22a及孔23 - 之形成手法相同。本實施形態中，配線圖案24之積層數為 5 5，且於最外面之配線圖案24設置有用以連接外部之電極 接合點24a。 接著，如第4B圖所示，於增層部20表面形成塗刷層 25。塗刷層25係對應電極接合點24a而具有開口。塗刷層 · 25之形成中，首先，藉印刷技術使作為塗刷層之用之感光 10 性樹脂於增層部20上成膜。接著，藉微影成像術形成預定 之開口部。形成塗刷層25後，於電極接合點24a之露出面 上，可藉無電解電鍍法形成諸如Ni鍍膜及於其上形成Au 鑛膜。 製造晶片搭載基板X中，接著，如第5A圖所示，以 15 保護膜44被覆設置有塗刷層25之增層部20。保護膜係諸 如由乾膜構成。 · 接著，如第5B圖所示，藉諸如研磨等機械加工除去 增層部20’。藉此，使核心基板10之核心材料11露出。 ^ 此外，本發明中，亦可僅將積層部20’中相當於之後之晶 - 20 片封裝區域之部份，藉NC切削或雷射加工除去。 然後，如第6 A圖所示，於核心基板10之核心材料11 上形成抗蝕圖案45。抗蝕圖案45係於對應電極接合點21 之處具有開口部。抗姓圖案45之形成手法係與抗蚀圖案 41之形成手法相同。 17 591765 玖、發明說明 接著，如第6B圖所示，使抗蝕圖案45作為屏蔽，於 核〜材料11進行㈣處理直至中間層13露出為止^本步 · 驟中，_液係配合核心材料u之構成材料，例如，可使 . 用氯化鐵水溶液、氫氟酸、王水等。姓刻處理後，抗_ 5 案45剝離。 接著，如第6C圖所示，以核心材料n作為屏蔽，於 中間層13進行關處理直至分隔材料12露出為止。本步 驟係以乾㈣進行。乾餘刻係例如可舉例有反應性離怕 · 刻（RIE)或離子研磨。 1〇 接著，如第7A圖所示，於分隔材料12上形成抗關 案46。抗蝕圖案46係用以遮蔽於分隔材料丨2中於後形成 之分隔物之處者。形成抗姓圖案46時，首先，將具有感光 性之油墨類型（液體）之光阻塗布於分隔材料12之露出面， 並以例如80 C乾燥30分鐘。接著，對該光阻膜進行曝光 15處理及顯像處理，於該光阻膜中形成預定之圖案。如此一 來，可形成抗蝕圖案46。 · 接著，如第7B圖所示，以抗蝕圖案46作為屏蔽，於 分隔材料12進行蝕刻處理直至電極接合點21充分地露出 - 為止。藉此，於核心基板1〇中，形成用以收容晶片之貫通 一 2〇孔10c，且增層部2〇中之晶片搭載區域施露出。且，於 晶片搭載區域20a上形成分隔物12a。於本步驟中，職 液係配合分隔材料12之構成材料，可使用諸如氣化銅水溶 液等。之後，如第7C圖所示，剝離抗蝕圖案46。然後， 使該基板分割成單片，即封裝尺寸。如此一來，形成配線 18 591765 玖、發明說明 基板X’。 接著，如第8A圖所示，將具有用以連接外部之凸塊 · 電極31的半導體晶片30A搭載於配線基板X’。即，將半 - 導體晶片30A以倒裝晶片法封裝於配線基板X’。凸塊電極 5 31之整體係以焊接材料構成。或，凸塊電極31係由諸如 銅等突出部分，與包覆該突出部分之焊接材料構成。 晶片搭載步驟中，首先，如第9A圖所示，將半導體 晶片30A固定於加熱板51且將配線基板X’固定於加熱板 · 52後，藉吸著夾頭53吸著加熱板51，且操作該吸著夾頭 10 53藉此使半導體晶片30A對位於配線基板X’。加熱板51 係具有可調節溫度之發熱機能，藉該加熱板51將半導體晶 片30A加熱至第1溫度。第1溫度係較凸塊電極31所含 有之焊接材料之溶點還高。加熱板52係具有可調節溫度之 發熱機能，藉該加熱板52將配線基板X’加熱至第2溫度 15 。第2溫度係較第1溫度還低，且係較凸塊電極31所含有 之焊接材料之熔點還低。又，於半導體晶片30A之凸塊電 · 極31上，於藉加熱板51加熱半導體晶片30A前，預先塗 布氧化防止劑54。氧化防止劑54可使用乙二醇、三甘醇 ‘ 、或四甘醇。 - 20 晶片搭載步驟中，接著，如第9B圖所示，藉操作吸 著夾頭53，於凸塊電極31及電極接合點21抵接之狀態下 ，將半導體晶片30A按壓於配線基板X’。並於按壓狀態下 ，對半導體晶片30A及凸塊電極31調節溫度以經過第1 溫度，藉此凸塊電極31之焊接材料歷經暫時熔融狀態。因 19 591765 玖、發明說明 此，經過本步驟之凸塊電極 興電極接合點21焊接接合 〇於焊接接合時，附著於凸塊雷 ^ 尾電極31之氧化防止劑54基 發。 … 5 10
於如此之晶片搭載步财，係個別地加熱半導趙晶； 观及配線基板X、隨著半導懸W加熱，其凸塊電極3 加熱至該凸塊電極31所含有之痒接材料可暫時嫁融之高於 該焊接材料之熔點之第1溫度。此時，半導趙晶片30A整 趙係對應第】溫度轉脹。另外，隨著配線基板X，加敎， 其電極接合點21係加熱至較第1溫度還低之第2溫度。此 時，配線基板X’整體係對應第2溫度而膨脹。因此，於半 導體30A及配線基板χ’之昇溫過程令，可防止配線基板 X相對於半導體晶片30A過度地膨脹。 於晶片搭載步驟中，接合凸塊電極31與電極接合點 21時’可於配線基板x’如前述適度地膨脹之狀態下，進行 15焊接接合。因此，可防止於焊接接合後冷卻至常溫之狀離
時，配線基板X，中不良之㈣或起伏，及在半導體晶片 30A及配線基板X，之間於由凸塊電極31及電極接合點η 構成之電性連接部產生應力。其結果為避免該連接部中產 生破裂或剝落，於半導體晶片3〇Α與配線基板χ，間得到高 20 連接可靠性。 此外，於晶片搭載步驟中，由於半導體晶片3〇α及增 層部20之間係間隔有分隔物12a，因此，可防止半導體晶 片30A及增層部20過度接近。自增層部2〇高起之分隔物 12a之高度，即分隔層12之厚度，係配合半導體晶片孙a 20 591765 玖、發明說明 之凸塊電極31之尺寸而決定。因此，於焊接接合之過程中 ，可防止不良之負荷作用於歷經熔融狀態之凸塊電極31， · 而適當地將半導體晶片30A搭載於配線基板X’。 - 於製造晶片搭載基板X中，接著，如第8B圖所示，
5 於核心基板10之貫通孔10c填充底膠填充劑55。底膠填 充劑55可填滿半導體晶片30A與增層部20之間，且同時 密封半導體晶片30A。如此之底膠填充劑55係具有衰減會 在由凸塊電極31及電極接合點21構成之電性連接部產生 II 之應力之機能。藉如此之衰減應力機能，可確保該以倒裝 10 晶片法封裝時之連接可靠性。 如前述，製成由配線基板X’及半導體晶片30A構成之 晶片搭載基板X。 於晶片搭載基板X中，如第10圖所示，係搭載半導 體晶片30B。半導體晶片30B係具有用以連接外部之凸塊 15 電極32。凸塊電極32整體係由焊接材料構成。或著，凸 塊電極32係由諸如銅之核心球，與包覆該核心球之焊接材 ® 料構成。半導體晶片30B可藉與前述半導體晶片30A之搭 載手法同樣之手法，搭載於晶片搭載基板X。於搭載狀態 ’ 下，凸塊電極32及電極接合點24a係熔融接合且焊接接合 - 20 〇 如此一來，可於晶片搭載基板X搭載半導體晶片30B 時，降低於半導體晶片30B與半導體晶片30A電性地接合 之處之兩晶片間之配線抗阻。這是因為兩晶片間之配線長 透過增層部20之微細配線構造設計成短。舉例來說，半導 21 591765 玖、發明說明 體晶片30A為1C晶片，且，半導體晶片30B為電容晶片 時，可藉降低兩晶片間之配線抗阻充分地防止兩晶片間之 ‘ 信號干擾。 · 於晶片搭載基板X中，如第11圖所示，可安裝散熱 5 體56。散熱體56係用以放散於半導體晶片30A產生之熱 者，係透過預定之黏著劑57接合於核心基板10及半導體 晶片30A。晶片搭載基板X具有如此之散熱體56之結構 時，會於半導體晶片30A為1C晶片之情形下特別有實際 ® 效益。1C晶片大多於驅動時發熱量大。 10 本實施形態中，在對核心材料進行蝕刻處理前已將增 層部20’全部當作假增層部藉機械研磨除去。本發明中， 亦可於核心基板10上殘留增層部20’之一部份，而將該殘 留部所含有之配線構造作為形成之晶片搭載基板X之配線 構造之一部份來利用以作替代。此時，參照第5B圖於前 15 述步驟中，不除去增層部20’全部，僅除去相當於晶片搭
載區域20a之一部份。將增層部20’之一部分除去之手法， H 例如，可採用NC切削或雷射加工。 【實施例】 β 製作本實施例之晶片搭載基板時，首先，製作核心基 - 20 板。核心基板之製作中，具體而言，係將分隔材料之電解 銅箔（厚度：7〇μιη)透過構成中間層之黏著劑之環氧樹脂層（ 商品名：ABF，曰本味之素精密科技製（Ajinomoto Fine-Techno)) 黏貼 於核心 材料之 42 合金板 （平面 尺寸： 150mmxl50mm，厚度：0.5mm )。42 合金係具有 Fe-42wt 22 591765 玖、發明說明 % Ni之組成。 製作晶片搭載基板中，其次，藉電鍍法於電解銅箔上 . 形成Ni鍍膜。然後，透過Ni鍍膜於電解銅箔上形成抗蝕 . 圖案。該抗蝕圖案係具有多數對應於下一步驟形成之電極 5 接合點之形狀之開口部。形成抗蝕圖案時，首先，將具有 感光性之乾膜（商品名：NIT-240，日本日合墨頓（日合乇一 卜>0製）貼合於電解銅箔。接著，對該光阻膜進行曝光處 理及顯像處理後，於該光阻膜形成開口部。 · 製作晶片搭載基板時，接著，於抗蝕圖案之各開口部 10 形成電極接合點。舉體而言，藉電鍍法於各開口部内部依 序形成Au鍍膜（厚度：Ιμιη)、Ni鍍膜（厚度：5μηι)、Cu鍍 膜（厚度：15μιη)，藉此形成電極接合點。形成電極接合點 後，使剝離液之3wt%氫氧化鈉水溶液作用，藉此使抗餘 圖案由電解銅箔剝離。以下，於核心基板中，使形成有該 15 電極接合點之側之面作為第1面，相對於該第1面之側之 面為第2面。 0 接著，於核心基板兩面形成絕緣層。具體而言，首先 ，使用真空疊層器壓著環氧樹脂層（平面尺寸：. ^ 200mmx200mm，厚度·· 50μπι，商品名：ABF，日本味之 - 20 素精密科技製（Ajinomoto Fine-Techno)製）。使壓著溫度為 130°C，壓著時間為2分鐘。之後，以170°C加熱30分鐘 ，藉此使環氧樹脂硬化。 然後，藉二氧化碳雷射於第1面側之絕緣層中對應前 述電極接合點之處形成多數通孔（直徑：60μηι)，使各電極 23 591765 玖、發明說明 接合點之一部份露出。 然後，藉半加性法於兩面之絕緣層上形成銅配線圖案 。此時，亦使銅堆積於第1面側之絕緣側中之通孔表面， 藉此更於該通孔形成孔。具體而言，首先，於各絕緣層表 5面及通孔表面施行除膠渣處理後，藉無電解電鍍法於絕緣 層及通孔表面形成無電解銅鍍膜。除膠渣處理係使用含有 過錳酸鹽之水溶液。接著，於無電解銅鍍膜上使光阻成膜 後，藉將其曝光及顯像，形成抗蝕圖案。該抗蝕圖案係具 · 有對應名人形成之配線圖案之圖案形狀。接著，藉電鏡法於 10抗蝕圖案沒有遮蔽之無電解鍍膜上，使無電解銅鍍膜作為 晶種層而利用其使電鍍銅堆積。然後，除去抗蝕圖案後， 餘刻除去仍未受抗蝕圖案被覆之無電解銅鍍膜。藉如此之 半加性法，於兩側之絕緣層上形成配線圖案，且於第1面 側之絕緣層之通孔形成有孔。 15 之後，將由絕緣層之積層形成至配線圖案及孔之形成 之如前述一連_之步驟，於核心基板之兩面側再重複4次 · ’藉此於核心基板兩面形成5層配線構造之增層部。 接著，藉孔版印刷及微影成像術，於第1面側之增層 ‘ 部表面形成塗刷層。於塗刷層之預定處設置開口部，以使 20增層部中最上方之配線圖案之一部份露出作為電極接合點 。之後，藉無電解電鍍法於電極接合點之露出面上，依序 形成Ni鍍膜（厚度：5μπι)及於其上之Au鍍膜（厚度： Ο.ΐμπι)。 然後，藉作為保護膜之乾膜被覆第1面側之增層部後 24 玖、發明說明 ，研磨去除第2面侧之增層部。藉此，使核心基板之核心 材料(42合金板）露出。接著’於核心材料中露出之面上形 成抗餘圖案。該抗钮圖案係於對應連接核心基板形成之前 述電極接合點之處，即對應晶片搭載區域之處具有開口部 5 〇 接著，使該抗蝕圖案作為屏蔽，對核心材料進行蝕刻 處理直至中間層露出。蝕刻液係使用氣化鐵水溶液。然後 ，藉使用氧氣之RIE，以核心材料作為屏蔽，對中間層進 灯蝕刻處理直至分隔材料（電解銅箔）露出為止。之後，於 10分隔材料中露出之面上形成抗蝕圖案。該抗蝕圖案係用以 遮蔽於分隔材料中形成分隔物之處者。 接著，使該抗蝕圖案作為屏蔽，對分隔材料進行蝕刻 處理直至第1面側之最下層之絕緣層及埋設於該絕緣層之 電極接合點充分露出為止。蝕刻液係使用氯化銅水溶液。 15藉此，於核心基板形成用以收容晶片之貫通孔，且於增層 部之核心基板側，晶片搭載區域露出。且，晶片搭載區域 上形成有分隔物。接著，將用以形成分隔物之抗蝕圖案剝 離。之後，將該基板分割成單片，即，封裝尺寸。如前述 ，形成多數用以搭載晶片之配線基板。 20 然後，將另外準備之半導體晶片以倒裝晶片法封裝於 配線基板。該半導體晶片係具有用以連接外部之凸塊電極 。該凸塊電極係對應配線基板之電極凸塊而設置，且係由 4 料（組成· Sn-3wt% Ag-0.5wt% Cu，熔點：220。〇構成。 晶片搭載步驟中，首先，將半導體晶片固定於第1加 25 591765 玖、發明說明 熱板後，藉吸著夾頭吸著第1加熱板，且，於該半導體晶 片之凸塊電極塗布氧化防止劑之乙二醇。另外，配線基板 係固定於第2加熱板。第1及第2加熱板係具有可調節溫 度之發熱機能。接著，藉第1加熱板加熱半導體晶片至 5 255°C，且，藉第2加熱板加熱配線基板至150°C。然後， 藉操作吸著夾頭，於半導體晶片之凸塊電極及配線基板之 電極接合點抵接之狀態下，按壓半導體晶片於配線基板。 於按壓狀態下，停止第1及第2加熱板所進行之加熱，使 半導體晶片及配線基板之溫度降低，並充分冷卻。藉此， 10半導體晶片之凸塊電極與配線基板之電極接合點焊接接合 〇 然後，於核心基板之貫通孔填充底膠填充劑，密封半 導體晶片。此時，底膠填充劑更填充於半導體晶片與增層 部之間。如前述，製成本實例之晶片搭載基板。 15 【圖式簡單說明】 第1A圖〜第1D圖係顯示本發明之晶片搭載基板之製 造方法中之一部份步驟。 第2A圖〜第2C圖係顯示接續第id圖之步驟。 第3A圖〜第3C圖係顯示接續第2C圖之步驟。 2〇 第4A圖〜第4B圖係顯示接續第3C圖之步驟。 第5A圖〜第5B圖係顯示接續第4B圖之步驟。 第6A圖〜第6C圖係顯示接續第5B圖之步驟。 第7A圖〜第7C圖係顯示接續第6C圖之步驟。 第8A圖〜第8B圖係顯示接續第7C圖之步驟。 26 591765 玖、發明說明 第9A圖及第9B圖係顯示將晶片搭載於配線基板之過 程。 第10圖係顯示於晶片搭載基板上更搭載有電子零件之 狀態。 5 第11圖係顯示本發明之晶片搭載基板具有散熱體之狀 態。 【圖式之主要元件代表符號表】 10…核心基板 30A…半導體晶片 10a···第一面 31,30B，32...凸塊電極 10b··.第二面 41,42,43,45,46···抗餘圖案 10c···貫通孔 41a...開口部 11...核心材料 44…保護膜 12…分隔材料 51，52…力σ熱板 12a...分隔物 53…吸著夾頭 13...中間層 54…氧化防止劑 20,20,…增層部 55...底膠填充劑 20a...晶片搭載區域 56…散熱體 21，24a…電極接合點 57...黏著劑 22,22,…絕騎 X…晶片搭載基板 22a^22a，…通孔 X，…配各_反 23,23’…孔 24,24’...g己線圖案 25···塗刷層
27

Claims (1)

  1. 拾、申請專利範圍 1β種電子零件搭載基板之製造方法，包含有·· 昇溫步驟，係將具有含有焊接材料之焊料凸塊電極 之電子零件加熱至較前述焊接材料之熔點還高之第i溫 度’且’將具有對應前述焊料凸塊電極之電極部之配 5 線基板加熱至較前述第1溫度還低之第2溫度；及 接a步驟，係使前述焊料凸塊電極抵接前述電極部 並且將前述電子零件按壓於前述配線基板上，藉此接 合前述焊料凸塊電極及前述電極部。 2·如申請專利範圍第1項之電子零件搭載基板之製造方 10 法，其中前述第2溫度係較前述焊接材料之熔點還低 〇 3·如申請專利範圍第i項之電子零件搭載基板之製造方 法其中於刖述昇溫步驟前，更包含有將乙二醇、三 甘醇或四甘醇附著於前述焊料凸塊電極上之步驟。 15 4·如申請專利範圍第1項之電子零件搭載基板之製造方 法，其中前述配線基板係具有由核心基板及增層部構 成之積層構造，前述核心基板係具有用以收容電子零 件之貫通孔，而前述增層部則具有由配線圖案與絕緣 層構成之積層構造，且具有由前述貫通孔露出之前述 20 電極部。 5· —種電子零件搭載基板之製造方法，包含有： 於具有含有核心層及分隔層之積層構造之核心基板 中之前述分隔層上，形成具有由配線圖案及絕緣層構 成之積層構造且具有連接前述分隔層之電極部的增層 28 拾、申請專利範圍 部’藉此製作配線基板之步驟； 由相對於前述增層部之側對前述核心層施行姓刻處 理，藉此除去該核心層中對應前述電極部之部份之步 驟； 由相對於前述增層部之側對前述分隔層施行姓刻處 理，藉此使前述電極部露出，且，於前述增廣部中之 電子零件搭載面上殘留形成分隔物之步驟；及 使-亥電子零件及前述增層部之間隔著前述分隔物接 合:塊電極及前述電極部，藉此將具有前述凸塊電極 之則述電子零件搭栽於前述配線基板 之步驟。
    29
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US20060051895A1 (en) 2006-03-09
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AU2003221149A1 (en) 2004-10-18
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