CN101192582B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN101192582B
CN101192582B CN2007101817965A CN200710181796A CN101192582B CN 101192582 B CN101192582 B CN 101192582B CN 2007101817965 A CN2007101817965 A CN 2007101817965A CN 200710181796 A CN200710181796 A CN 200710181796A CN 101192582 B CN101192582 B CN 101192582B
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substrate
opening
semiconductor structure
thinning
joint sheet
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CN101192582A (zh
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卢思维
李明机
陈承先
吴华书
邹觉伦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种半导体结构及其制造方法。该半导体结构包括第一基板以及接合在第一基板上的第二基板。第一基板上具有一保护层，保护层具有至少一个第一开口，所述第一开口露出第一基板上的第一接合垫。第二基板具有贯穿所述第二基板的至少一个第二开口，所述第二开口实质上对正于第一开口。

Description

半导体结构及其制造方法 
技术领域
本发明涉及半导体结构及其制造方法，且特别涉及一种接合结构(bonding structure)及其制法。 
背景技术
随着电子产品不断演进，半导体技术已广泛应用在中央处理器(CPU)、液晶显示器(LCD)、发光二极管(LED)、激光二极管等组件的制作。为了达到更高的集成度与更快的组件速度，集成电路的尺寸不断地缩小，而各种新颖的材料与技术也因运而生。为了减小晶粒(die)尺寸，目前开发出一种穿透晶片插塞(though wafer via，TWV)的新技术。 
图1A-1E显示一种公知的TWV技术。请参照图1A，在基板100上具有一包含金属层115的多层内连线结构110。接合垫(bonding pad)125形成在多层内连线结构110上方。保护层120形成在接合垫125上，并具有开口130露出部分的接合垫125。 
请参照图1B，利用耐温胶带(thermal tape)155将虚设基板(dummysubstrate)150与保护层120接合，然后对基板100进行研磨，研磨时虚设基板150当作基板100的载体(carrier)。研磨后的基板100a厚度大约150μm，如图1C所示。 
请参照图1D，在基板100a中形成穿透晶片插塞(TWV)160，作为金属层115与另一基板(未显示)的电性连接。穿透晶片插塞160通常包含一扩散阻挡层与一金属层，其中金属层通常是以化学气相沉积法(CVD)或物理气相沉积法(PVD)在约300℃的工艺温度下形成。扩散阻挡层可以是导电材料如金属氮化物，或是介电材料如氮化硅。然而，耐温胶带155无法承受如此高的工艺温度，可能因此熔化及/或失去接合效果。如此一来，虚设基板150可能会在后续的工艺中从保护层120上脱落，如图1E所示，其中后续的工艺例如是用来平坦化穿透晶片插塞160的化学机械研磨(CMP)工艺。基板100a可能因此在CMP工艺中受到损坏。
发明内容
本发明的主要目的在于提出一种半导体结构及其制作方法，特别是提出一种接合结构(bonding structure)及其制法。 
在一实施例中，本发明的半导体结构包括第一基板以及接合在第一基板上的第二基板。第一基板上具有一保护层，保护层具有至少一个第一开口，所述第一开口露出第一基板上的第一接合垫。第二基板具有贯穿所述第二基板的至少一个第二开口，所述第二开口实质上对正于第一开口。 
如上所述的半导体结构，其中该第二基板的厚度为5μm-100μm。 
如上所述的半导体结构，其中所述第二开口实质上等于或大于所述第一开口。 
如上所述的半导体结构，还包括一个第三基板，其中该第一基板设于该第三基板，且该第三基板包括至少一个第二接合垫，且所述第一接合垫通过所述第一开口与所述第二开口以焊线接合至所述第二接合垫。 
如上所述的半导体结构，其中该第一基板中还包括至少一个穿透晶片插塞，且该第二基板是以熔融接合方式接合在该保护层上。 
如上所述的半导体结构，还包括一个第四基板设置于该第二基板上，其中该第二基板作为该第四基板与该第一基板间的间隔物。 
如上所述的半导体结构，其中所述第二开口完全延伸穿过该第二基板，且至少一导电结构形成在所述第一开口与所述第二开口中，其中该导电结构以覆晶方式接合至另一基板。 
如上所述的半导体结构，其中该导电结构上还包括至少一凸块。 
如上所述的半导体结构，其中所述第二开口延伸超过所述第一开口至该第二基板的边缘。 
在一实施例中，本发明的半导体结构的制造方法包括：提供第一基板，具有一保护层于其上，保护层具有至少一个第一开口，所述第一开口露出第一基板上的第一接合垫。将一虚设基板通过熔融接合方式接合在所述第一基板上，虚设基板具有至少一个第二开口，所述第二开口实质上对正于所述第一开口且朝向第一开口。以虚设基板作为第一基板的载体，将第一基板薄化。将虚设基板薄化以从第二 开口露出第一开口。 
如上所述的半导体结构的制造方法，其中该接合步骤包括一熔融接合步骤。 
如上所述的半导体结构的制造方法，还包括形成至少一穿透晶片插塞于该薄化后的第一基板。 
如上所述的半导体结构的制造方法，还包括： 
将该薄化后的第一基板设置于第二基板上，该第二基板上具有至少一个第二接合垫；以及 
通过所述第一开口与所述第二开口进行打线接合，以连接所述第一接合垫与所述第二接合垫。 
如上所述的半导体结构的制造方法，还包括将一个第三基板设置于该薄化后的虚设基板，其中该薄化后的虚设基板作为该第三基板与该薄化后的第一基板间的间隔物。 
如上所述的半导体结构的制造方法，其中所述第二开口实质上等于或大于所述第一开口。 
因此，本发明提出的接合结构能够承受较高的工艺温度，可靠性也更高。 
为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下： 
附图说明
图1A-1E显示公知的一种形成穿透晶片插塞(TWV)的方法。 
图2A-2D为一系列剖面图，用以说明实施例中接合基板与薄化虚设基板的流程。 
图2E-2F为一系列剖面图，用以说明实施例中在图2C的薄化基板200a形成至少一穿透晶片插塞260。 
图2G-2H为一系列剖面图，用以说明实施例中形成凸块结构的流程。 
图3A-3D为一系列剖面图，用以说明实施例中将图2D的晶粒设置在基板上的流程。 
图3E为一剖面图，用以说明实施例中将图2H的晶粒进行覆晶封装。 
图3F为图3B中301区域的部分放大上视图。 
并且，上述附图中的各附图标记说明如下： 
100基板             115金属层 
110多层内连线结构   125接合垫 
120保护层           130开口 
150虚设基板         155耐温胶带 
100a薄化基板        160穿透晶片插塞 
200基板             250虚设基板 
200a薄化基板        210多层结构 
215导电层           220保护层 
225、255’接合垫    230、231、255、256开口 
250a薄化虚设基板    260穿透晶片插塞 
240导电结构         245凸块 
251顶角             370基板 
375接合垫           380、380’焊线 
390球栅阵列         301图3B的部分区域301 
370a-370c基板区     395基板 
397保护层           399接合垫 
具体实施方式
在本发明的实施例中所提到的相对用语，如“较低”、“较高”、“水平”、“垂直”、“上”、“下”、“之上”、“之下”、“顶部”、“底部”等只是用来配合附图中所呈现的方位方便说明，并非表示本发明的组件或装置必须要以一特定的方位来操作。 
图2A-2D显示本发明一实施例将薄化虚设基板接合在基板的方法。请参照图2A，基板200上具有多层结构210。基板200可为硅基板、III-V族化合物基板、显示器基板如液晶显示器(LCD)、等离子体显示器、电致发光(EL)显示器、发光二极管(LED)基板等。基板200的原始厚度约在600μm到1200μm之间。基板上形成有各种有源组件、无源组件及/或其它电路组件，其中有源组件例如是金属氧化物半导体晶体管(MOSFET)、双载子晶体管，无源组件例如是电阻、电容、电感。多层结构210可包括至少一导电层215(例如金属 层、插塞、接点、镶嵌式结构、双镶嵌结构等、或前述的组合)以及至少一介电层(未标号)(例如氧化层、氮化层、氮氧化层、低介电常数层等、或前述的组合)。多层结构210是用来作为基板200上各种二极管、晶体管、组件及/或其它电路组件的内连线。这些组件与多层结构210可以用光刻工艺、蚀刻工艺、离子注入、金属化工艺、沉积工艺、清洁工艺等各种步骤形成。 
在多层结构210上形成至少一接合垫225以电性连接至另一基板(未显示)。接合垫225可包含铜、铝、铜铝合金等或其组合。接合垫225可用化学气相沉积法、物理气相沉积法、电镀法、无电电镀法等方式形成。 
在多层结构210上还形成一保护层220，其具有至少一开口230，所述开口露出接合垫225。保护层220的材质可为氧化物、氮化物、氮氧化物、聚亚酰胺、PIQTM(Hitachi Chemical Co.，Ltd)等或其组合。保护层220可用化学气相沉积、旋转涂布等方式形成。开口230可用光刻与蚀刻技术形成，露出接合垫225后，利用打线接合(wire bonding)或覆晶接合(flip chip bonding)可连接至另一基板。在一实施例中，开口230的长度与宽度(或直径)例如约在30μm到45μm之间。 
请参照图2B，将一虚设基板250与基板200上的保护层220接合。虚设基板250包括至少一开口255，所述开口对正(或对准)于开口230且朝向开口230。开口255可为沟槽、正方形开口、矩形开口等或其组合。开口255至少在宽度、长度、及/或直径上大概等于或大于开口230。在一实施例中，开口255的长度及/或宽度大概等于开口230，而开口255的深度约10μm或更深。深度大小将取决于虚设基板250所需的最终厚度(薄化后)。在另一实施例中，开口255的长度及/或宽度大于开口230，而开口255的深度约20μm或更深。 
虚设基板250可为硅基板、III-V族化合物基板、玻璃基板等。在一实施例中，虚设基板250未含有任何集成装置、二极管及/或其它电路。虚设基板250可含有硅层、氧化层、氮化层、氮氧化层、前述的组合、或其它任何可与保护层220接合的材料。例如，虚设基板250可以是一裸硅晶片(bare siliconwafer)，而保护层220包含一氧化层如氧化硅。经过热处理及/或等离子体处理后，硅晶片表面与氧化层表面会形成悬空键(dangling bond)，经过一接合步骤后，这些悬空键可以通过例如范德华力(Van der Waals force)互相结合。 
虚设基板250可以通过各种方式接合在保护层200上，例如熔融接合(Fusion Bonding)、胶带接合(Tape Bonding)等或其组合。在胶带接合的实施例中，胶带(未显示)是设在虚设基板250与保护层200之间接合两者。由于材料本身的性质，胶带无法承受约200℃或更高温度的热工艺。在熔融接合的实施例中，先对虚设基板250及/或保护层200的表面进行等离子体处理，再以约20℃-500℃的温度将两者接合。熔融接合时由于虚设基板250与保护层200之间没有黏着层(胶带)，所得的接合结构可以承受后续的高温工艺。 
请参照图2C，虚设基板250是用来作为薄化基板200的载体。薄化的步骤可包括研磨程序，例如化学机械研磨。薄化后的基板200a则用来作为薄化虚设基板250的载体，如图2D所示。 
将虚设基板250薄化以露出开口255与230。简单的讲，薄化后的虚设基板250a露出接合垫225，使接合垫225可以跟另一基板接合，例如芯片载体(chip carrier)、有机基板、陶瓷基板、或导线架(lead frame)。如前文所述，开口255的深度约10μm或更深。薄化后的虚设基板250a厚度约5μm至100μm。在另一实施例中，开口255的深度约20μm或更深，但经过薄化后应使得开口255在虚设基板250a的最后深度为10μm或更深。虚设基板250a薄化后的厚度应控制在使其顶部角落不会影响到后续图3A的打线接合。 
图2E-2F显示在图2C薄化后的基板200a中形成至少一个穿透晶片插塞(TWV)260。 
请参照图2E，在薄化基板200a中形成穿透晶片插塞260与导电层215电性连接。形成穿透晶片插塞260的步骤可包括，例如，先在薄化基板200a中形成多个开口，露出部分导电层215，然后在开口中形成顺应性的阻挡层。接着，在阻挡层上形成金属层后，去除开口以外多余的阻挡层与金属层便可得到穿透晶片插塞260。上述开口例如可用光刻与蚀刻技术形成。阻挡层的材料可为氧化物、氮化物、氮氧化物、Ti、TiN、Ta、TaN等或其组合。阻挡层的形成方法可用化学气相沉积、物理气相沉积或其组合。金属层可为Cu、Al、AlCu等或其组合。金属层的形成方法可用化学气相沉积、物理气相沉积、电化学电镀、无电电镀等或其组合。去除阻挡层与金属层的方式可利用蚀刻步骤、化学机械研磨等或其组合。 
以无线射频(RF，radio frequency)芯片为例，导电层215可以是耦接至RF 组件射极的任何金属层(一般通称为Metal-1)。接着将穿透晶片插塞260设置在另一基板上(未显示)，使金属层215电性连接至另一基板接地。 
在穿透晶片插塞260的实施例中，图2B的接合步骤优选地是熔融接合。由于熔融接合不需要黏着层，图2E的结构可承受在200℃以上形成阻挡层及/或金属层。 
形成穿透晶片插塞260后，同样对虚设基板250进行如前文所述的薄化程序以得到图2F的结构。 
得到图2D与图2F的接合结构后，沿着切割道进行晶粒切割。切割的方式可包括钻石刀切割、激光切割、水刀切割等或其组合。切割后将所得的单一晶粒设置在另一基板上，如图3A-3E所示。 
图2G-2H为形成凸块结构(bump structure)的剖面示意图。为了制作凸块结构，先在保护层220与薄化虚设基板250a中形成开口230、231、255、256。图2G中开口231、256的形成方式跟图2A-2D中开口230、255相同。开口231、256是以阵列方式围绕着基板200a上的有源区(未显示)。 
请参照图2H，在开口230、231、255、256中形成导电结构240，然后在导电结构240与薄化虚设基板250a部分表面上形成凸块245。导电结构240可包含铜、铝、铝铜合金、锡铅(solder)等或其组合，其形成方式可用电化学电镀、化学气相沉积、物理气相沉积、无电电镀等或其组合。凸块245可包含铜、铝、铝铜合金、金、锡铅等或其组合，其形成方式可用电化学电镀、无电电镀等或其组合。此电镀步骤会在导电结构240上形成凸块245，但不会在薄化虚设基板250a上形成凸块。在一些实施例中，凸块可包含导电结构240与凸块245，视所用的工艺而定。 
在一实施例中，开口255、256的深度约50μm或更深，因此导电结构240的厚度约50μm或更厚。当凸块245与另一基板接合时，即使凸块245的厚度在50μm以下，导电结构240的厚度仍可提供所需的可靠度。由以下说明将可了解，凸块245与导电结构240的总厚度大于50μm可使其结构不易受到公知技术中应力的影响。在一些实施例中，导电结构240可高于或低于薄化虚设基板250a的上表面。 
以前述实施例的方法与结构可以形成凸块的密集阵列。在传统的凸块结构中，球形凸块的厚度至少约50μm以确保接合时的可靠度。球形凸块的宽 度约等于其厚度。如果两个接合垫的距离在50μm以内，接合垫上的球形凸块可能会互相接触。相比于传统的凸块结构，开口255、256的深度约50μm或更深，例如100μm以上，因此可以容纳厚度50μm以上的导电结构240。由于导电结构240提供了额外的厚度，导电结构240跟凸块245的总厚度大于50μm，因此即使凸块245的厚度小于50μm也不会有可靠度的问题。此外，由于凸块245的宽度仍然可以小于50μm，因此可缩小接合垫225的距离使凸块245排成致密的阵列以缩小芯片尺寸。 
图3A-3D为一系列剖面图，其显示将图2D的晶粒设置在一基板上。如图3A所示，基板200a设置在基板(芯片载体)370上，基板370上设有至少一接合垫375，底下形成有球栅阵列(BGA，ball grid array)390。利用打线接合使焊线380穿过开口230、255连接接合垫225与接合垫375以电性连接基板200a上的组件、二极管、及/或其它电路，甚或更连接基板370上的组件、二极管、及/或其它电路。基板370可为硅基板、III-V族化合物基板、显示器基板如液晶显示器(LCD)、等离子体显示器、电致发光(EL)显示器、发光二极管(LED)基板等、塑料基板、陶瓷基板、印刷电路板(PCB)等。基板200a上的组件信号可通过焊线380传递至接合垫375，再通过基板370上的导电路径(未显示)传递至球栅阵列390。 
在一实施例中，可控制薄化虚设基板250a的厚度，使薄化虚设基板250a的顶角251不至于影响到焊线接合。应注意的是，薄化虚设基板250a可以作为散热结构，在基板200a上的组件操作时帮助散热。在一实施例中，薄化虚设基板250a可包含至少一导电结构，例如穿透晶片插塞(未显示)，当另一基板设在薄化虚设基板250a上时，此导电结构可以帮助散热及/或作为电性连接。在一实施例中，薄化虚设基板250a上可另外设置一散热器(heatsinker)以增进散热效果，只要该散热器不影响焊线接合。 
在一实施例中，开口255的剖面区域大于开口230。例如，如图3B所示，开口255’可以延伸超过开口230直到薄化虚设基板250a的边缘，换句话说，晶粒200a周边(例如，切割线区域)上方焊线接合的位置没有薄化虚设基板250a。图3F显示图3B中301区域的部分放大上视图，相比于图3A，图3B具有更大的开口255’以避免焊线380’在接合时受到薄化虚设基板250a顶角的干扰。另外，此实施例可以降低焊线380的高度。 
图3C显示将图2F的晶粒(其具有穿透晶片插塞260)设置在一包括基板区370a-370c的基板层上。以RF组件为例，基板区370a-370c可包含一导线架基板。穿透晶片插塞260电性连接导电层215与基板区370b以接地。基板区370a、370c与基板区370b隔离，提供输出/输入(I/O)接合垫375的接合。图3C的结构中也可形成图3A-3B所描述的较大开口255’及/或散热器。 
请参照图3D，在薄化基板250a上设置一基板395。基板395上可包含一保护层397，其中形成有开口露出接合垫399。保护层397与接合垫399类似于图2A的保护层220与接合垫225。在一实施例中，基板395也与基板200a类似或相同。 
在一实施例中，较大开口255’的尺寸应使基板395的设置不致于影响到焊线接合。此外，薄化虚设基板250a可作为基板200a与基板395之间的间隔物(spacer)。薄化虚设基板250a的厚度最好约50μm以上，以避免基板395接触到焊线380。如前文所述，薄化虚设基板250a可包含至少一导电结构穿过其中，以提供基板200a与基板395之间的电性连接。 
图3E显示对图2H的晶粒进行覆晶封装(Flip Chip)的剖面示意图。如前文所述，图2H的结构可形成接合可靠度良好的致密凸块阵列与基板370进行覆晶封装。 
虽然本发明已以多个优选实施例公开如上，但是其并非用以限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，当可作任意的改动与修饰，因此本发明的保护范围当视后附的权利要求书所界定的范围为准。 

Claims (14)

1.一种半导体结构，包括：
第一基板，其上具有一保护层，该保护层具有至少一个第一开口，所述第一开口露出该第一基板上的第一接合垫；以及
第二基板，接合在该保护层上，该第二基板具有贯穿所述第二基板的至少一个第二开口，所述第二开口实质上对正于所述第一开口。
2.如权利要求1所述的半导体结构，其中该第二基板的厚度为5μm-100μm。
3.如权利要求1所述的半导体结构，其中所述第二开口实质上等于或大于所述第一开口。
4.如权利要求1所述的半导体结构，还包括一第三基板，其中该第一基板设于该第三基板，且该第三基板包括至少一个第二接合垫，且所述第一接合垫通过所述第一开口与所述第二开口以焊线接合至所述第二接合垫。
5.如权利要求4所述的半导体结构，其中该第一基板中还包括至少一穿透晶片插塞，且该第二基板是以熔融接合方式接合在该保护层上。
6.如权利要求4所述的半导体结构，还包括一第四基板设置于该第二基板上，其中该第二基板作为该第四基板与该第一基板间的间隔物。
7.如权利要求1所述的半导体结构，其中所述第二开口完全延伸穿过该第二基板，且至少一导电结构形成在所述第一开口与所述第二开口中，其中该导电结构以覆晶方式接合至另一基板。
8.如权利要求7所述的半导体结构，其中该导电结构上还包括至少一凸块。
9.如权利要求1所述的半导体结构，其中所述第二开口延伸超过所述第一开口至该第二基板的边缘。
10.一种半导体结构的制造方法，包括：
提供第一基板，具有一保护层于其上，该保护层具有至少一个第一开口，所述第一开口露出该第一基板上的第一接合垫；
将一虚设基板通过熔融接合方式接合在所述第一基板上，该虚设基板具有至少一个第二开口，所述第二开口实质上对正于所述第一开口且朝向所述第一开口；
以该虚设基板作为该第一基板的载体，将该第一基板薄化；以及
将该虚设基板薄化使所述第一开口从所述第二开口中露出。
11.如权利要求10所述的半导体结构的制造方法，还包括形成至少一穿透晶片插塞于该薄化后的第一基板。
12.如权利要求10所述的半导体结构的制造方法，还包括：
将该薄化后的第一基板设置于一第二基板上，该第二基板上具有至少一第二接合垫；以及
通过所述第一开口与所述第二开口进行打线接合，以连接所述第一接合垫与所述第二接合垫。
13.如权利要求12所述的半导体结构的制造方法，还包括将一第三基板设置于该薄化后的虚设基板，其中该薄化后的虚设基板作为该第三基板与该薄化后的第一基板间的间隔物。
14.如权利要求10所述的半导体结构的制造方法，其中所述第二开口实质上等于或大于所述第一开口。
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