CN1581477A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN1581477A CN1581477A CNA2004100559337A CN200410055933A CN1581477A CN 1581477 A CN1581477 A CN 1581477A CN A2004100559337 A CNA2004100559337 A CN A2004100559337A CN 200410055933 A CN200410055933 A CN 200410055933A CN 1581477 A CN1581477 A CN 1581477A
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- tantalum
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- 238000000034 method Methods 0.000 title claims description 41
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 64
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims abstract description 28
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- Physical Vapour Deposition (AREA)
Abstract
本发明提供一种半导体装置,包括:形成于半导体基板上的第一布线层;形成于该第一布线层上的层间绝缘膜;在该层间绝缘膜上形成的由金层构成的作为最上层布线层的第二布线层;在形成于上述层间绝缘膜上的层间连接用开口内,夹持在上述第一布线层与第二布线层之间的阻挡层。所述阻挡层具有与上述第一布线层接触并使接触电阻减少的第一层、与上述第二布线层接触并使接触强度提高的第二层、以及夹持在上述第一层与上述第二层之间的第三层。例如可以是一层为第一钽层、第二层为第二钽层、第三层为氮化钽层。
Description
技术领域
本发明涉及具有多层布线的半导体装置及其制造方法。
背景技术
半导体装置具有半导体基板、形成于该半导体基板的表层部上的功能元件、以及形成于该半导体基板上的多层布线结构。多层布线结构是夹持层间绝缘膜叠层多层布线的结构,不同的布线层间的连接是借助形成于层间绝缘膜上的接触孔而完成的。
作为布线材料一直使用的铝,在低电阻化中存在局限,伴随半导体装置的微细化截面积逐渐变小,其布线电阻成了问题。因此,尤其期望地线或电源线的低电阻化。
因此,例如,本发明人等在特开2002-217284号公报中提出了在最上层的布线中使用金层从而使布线低电阻化的提案。
在该现有技术中,借助接触孔电连接的铝布线层与由金层构成的最上层的布线层之间,夹持有由钛薄膜构成的阻挡层,通过该阻挡层可以防止铝的迁移。
但是,由于金是一种极易扩散的材料,例如在合金处理时的高温下长时间放置(例如400℃放置30分钟~1小时),则容易向铝布线层侧扩散。
而且,在钛薄膜中,耐腐蚀性不充分,若在PCT(Pressure Cooker Test)时的环境下使用时,存在铝腐蚀以至于破坏到半导体装置的危险。
发明内容
本发明的目的在于提供一种能够在使用由金层构成的布线的同时可以充分防止金的扩散、并且耐腐蚀性良好的半导体装置及其制造方法。
本发明的半导体装置,具有:形成于半导体基板上的第一布线层、形成于该第一布线层上的层间绝缘膜、在该层间绝缘膜上形成的由金层构成的作为最上层布线层的第二布线层、在形成于上述层间绝缘膜上的层间连接用开口内夹持在上述第一布线层与第二布线层之间的阻挡层。该阻挡层具有:与上述第一布线层接触并使接触电阻减少的第一层、与上述第二布线层接触并使接触强度提高的第二层、以及夹持在上述第一层与上述第二层之间的第三层。
优选上述第一层是第一钽层,上述第二层是第二钽层,上述第三层是氮化钽层。
根据该构成,阻挡层具有第一以及第二钽层和夹持在它们之间的氮化钽层,尤其是通过氮化钽层的作用,可以充分防止构成第二布线层的金向第一布线层扩散,并且可以实现良好的耐腐蚀性。
另外,第一钽层,例如有助于降低与由铝构成的第一布线层之间的接触电阻,第二钽层有助于提高阻挡层与由金层构成的第二布线层之间的粘接强度。即,在第一布线层由铝构成时,若使氮化钽层与该第一布线层接触,则第一布线层的表面被氮化,其电阻变高。该问题可以通过第一钽层解决。另外,金层对氮化膜没有充分的粘接力。该问题可以通过第二钽层解决。
另外,通过组合钽层与氮化钽层而使用,与单独使用钽层的情况相比,以薄的膜厚可以防止金的扩散。更具体地说,若以单独的钽层构成阻挡层,则为了防止金的扩散,需要4000左右的膜厚,但是在第一钽层与第二钽层之间夹持氮化钽层而构成阻挡层的情况下,能够以2000左右的膜厚防止金的扩散,这些都得到了本发明人试验的确认。
上述氮化钽层,优选具有的氮原子密度分布,是在上述第一钽层侧的氮原子密度比在上述第二钽层侧的氮原子密度低。根据该构成,由于第一钽层侧即第一布线层侧的氮原子密度比较低,氮原子到达第一布线层从而可以抑制或防止该第一布线层的电阻升高。
上述层间绝缘膜优选含有覆盖其整个表层部的氮化硅膜。根据该构成,通过致密并且钝化效果高的氮化硅膜的作用,可以进一步提高耐腐蚀性。
上述半导体装置,优选进一步含有覆盖上述第二布线层以及上述层间绝缘膜的聚酰亚胺树脂膜。在该构成中,由于由金层构成的第二布线层的耐腐蚀性以及阻挡层的耐腐蚀性良好,因此通过钝化效应低的聚酰亚胺树脂膜覆盖其整体,可以充分保护装置。而且,聚酰亚胺树脂膜可以通过涂布工序容易形成,因此可以使制造工序简化。
上述半导体装置,优选进一步含有覆盖上述第二布线层以及上述层间绝缘膜的氮化硅膜。根据该构成,由于能够以钝化效应高的氮化硅膜覆盖整体,因此可以很好地保护装置。
该发明的半导体装置的制造方法,是用于制造构成为借助形成于上述层间绝缘膜上的层间连接用开口对夹持层间绝缘膜而形成的第一布线层和第二布线层进行电连接的半导体装置的制造方法。该方法包括:在半导体基板上形成上述第一布线层的工序;以覆盖该第一布线层的方式形成上述层间绝缘膜的工序;在该层间绝缘膜的规定位置上形成使上述第一布线层露出的层间连接用开口的工序;在上述层间连接用开口内形成阻挡层的工序;在上述层间绝缘膜上形成与上述阻挡层接触而由金层构成的作为最上层布线层的上述第二布线层的工序。在形成上述阻挡层的工序中,形成具有与上述第一布线层接触而使接触电阻降低的第一层、与上述第二布线层接触而使粘接强度提高的第二层、以及夹持在上述第一层和第二层之间的第三层的叠层结构的阻挡层。
优选上述第一层是第一钽层,上述第二层是第二钽层,上述第三层是氮化钽层。
另外,形成上述阻挡层的工序,优选包括通过连续溅射法形成第一钽层、氮化钽层以及第二钽层的连续溅射工序。该连续溅射工序,优选包括:在处理室内通过以钽作为靶的溅射形成第一钽层的工序;之后在处理室内导入氮气在氮气气氛中进行以钽作为靶的溅射,从而形成氮化钽层的工序;之后,从处理室排除氮气并通过以钽作为靶的溅射形成第二钽层的工序。
即,在连续溅射的最初,在处理室内不导入氮气而形成钽层,之后,在处理室内导入氮气。在氮气的导入初期,在处理室内几乎不导入氮气,而是随着时间的推移处理室内的氮气浓度变高。其结果,在第一钽层侧形成氮原子密度比较低的氮化钽层。之后,通过从处理室内排除氮气,形成第二钽层。
形成上述层间绝缘膜的工序,优选包括形成覆盖其表层部整体的氮化硅膜的工序。
上述方法优选进一步包括形成覆盖上述第二布线层和上述层间绝缘膜的聚酰亚胺树脂膜的工序。形成聚酰亚胺树脂膜的工序也可以是涂布聚酰亚胺树脂的涂布工序。
上述方法,优选进一步包括形成覆盖上述第二布线层和上述层间绝缘膜的氮化硅膜的工序。
本发明中的上述以外的其它目的、特征以及效果参照附图通过以下的实施方式进行说明。
附图说明
图1是表示本发明的一实施方式的半导体装置的构成的剖面图。
图2是用于说明阻挡层构成的图。
图3是表示阻挡层的氮原子密度分布的图。
图4(a)~4(e)是依次表示上述半导体装置的制造工序的剖面图。
图5是表示本发明的其它实施方式的半导体装置的构成的剖面图。
具体实施方式
图1是表示本发明的一实施方式的半导体装置的构成的剖面图。该半导体装置在形成有场氧化膜12的硅基板11上具有由聚硅构成的布线15。
层间绝缘膜13以覆盖场氧化膜12以及聚硅布线15的方式在整个面上形成,在该层间绝缘膜13上形成作为第一布线层的铝布线层14。该铝布线层14以及层间绝缘膜13的整个面,被由USG(非掺杂硅酸盐玻璃)层16U与覆盖其整个表层部而形成的氮化硅膜16S的叠层膜构成的层间绝缘膜16覆盖。在该层间绝缘膜16上形成有作为最上层布线层的第二布线层的金布线层(由金层构成的布线层)19。该金布线层19以及层间绝缘膜16的整体被聚酰亚胺树脂膜18覆盖,该聚酰亚胺树脂膜18的表面为平整面。
在层间绝缘膜16的规定位置上,形成使铝布线层14的一部分露出的接触孔H,借助该接触孔H可以到达铝布线层14和金布线层19之间的层间连接。
在金布线层19与铝布线层14之间,在接触孔H内夹持有用于防止构成金布线层19的金扩散的阻挡层20。该阻挡层20如图2放大所示,是具有结合铝布线层14的第一钽层21、结合金布线层19的第二钽层22、以及夹持在该第一以及第二钽层21、22之间的氮化钽层23的叠层膜。
氮化钽层23内的氮原子密度,如图3所示,在与第一钽层21的界面侧低,随着向第二钽层22靠近密度逐渐增加的分布。另外,在与第二钽层22的界面侧的氮化钽层23内的氮原子密度,可以是在与第二钽层22的界面处变为零那样的急剧减小(台阶状变化),也可以是如图3中所示两点划线所示随着向金布线层19的靠近逐渐减小。此时,在氮原子密度变为零的地方作为氮化钽层23与第二钽层22的界面而被控制。
通过这种构成,在该装置的制作后的合金处理时,即使将该装置放置于高温环境下,主要通过氮化钽层23的作用,可以有效地防止构成金布线层19的金向铝布线层14侧扩散,另外,即使在PCT时的环境下,也能够显示良好的耐腐蚀性。而且,与以钽层单体构成阻挡层的情况相比,可以实现极薄的阻挡层20。
另外,对于铝布线层14氮化钽层23不直接接触,因此,可以防止铝布线层14被氮化而引起的高电阻化。而且,氮化钽层23的氮原子密度,由于越靠近铝布线层14越低,因此,可以确实确保铝布线层14为低电阻状态。
进而,在相对于氮化膜附着性低的金布线层19侧,由于配置第二钽层22,因此可以以充分的粘接强度对金布线层和阻挡层20进行接合。
图4(a)~4(e)是表示上述半导体装置的制造工序的剖面图。首先如图4(a)所示,在硅基板11的表面上形成元件分离膜12并形成元件区域,同时在该元件区域内形成由聚硅膜构成的布线15。
然后,如图4(b)所示,在该上层上形成由BPSG膜构成的层间绝缘膜13,借助未图示的接触孔形成与该聚硅布线15连接的铝布线层14。
之后,如图4(c)所示,通过CVD法等(化学气相生长法)通过沉积USG(非掺杂硅酸盐玻璃)而形成USG层16U,进而,在该上层上通过等离子CVD法形成氮化硅膜16S。由此,形成层间绝缘膜16。在该层间绝缘膜16上的规定位置上形成接触孔H。
之后,如图4(d)扩大所示,通过溅射法在整个面上形成阻挡层20。更具体地说,在处理室内配置经过图4(c)之前的工序的硅基板11,在该处理室内,通过以钽作为靶的连续溅射法,依次连续形成第一钽层21、氮化钽层23以及第二钽层22。在连续溅射的初期,在处理室内不导入氮气。由此,钽原子被输送到硅基板11上,形成第一钽层21。在该初期,钽原子与铝布线层14的表面冲突,除去表面的氧化物等。接着,在铝布线层14的被活性化的表面上附着钽原子。
之后,通过在处理室内供给氮气,在第一钽层21上输送钽原子和氮原子,形成氮化钽层23。在氮气的供给开始,在处理室内只存在极少的氮气,随着时间的推移,处理室内的氮原子数增加。因此,氮化钽层23中的氮原子密度,变成如图3所示的分布。
然后,通过排出处理室内的氮气,接着继续进行溅射,在氮化钽层23上钽原子被输送而附着,从而进行第二钽层22的形成。
接着,如图4(e)所示,在整个面上形成金的种晶层19S。该种晶层19S的形成,可以在用于形成上述阻挡层20的处理室内,通过从钽切换成金进行定标的连续溅射法来进行。
然后,以覆盖种晶层19S的方式在整个面上形成抗蚀层24。在该抗蚀层24上形成对应于金布线层19的开口24a。在该状态下通过进行金的电镀,在开口24a内生长金布线层19。
之后,剥离抗蚀层24,蚀刻除去金布线层19以外的部分种晶层19S以及阻挡层20,同时,通过涂布法例如形成由膜厚2μm的聚酰亚胺树脂膜18构成的钝化膜,则可以获得图1所示构成的半导体装置。
进而,例如也可以在聚酰亚胺树脂膜18上的金布线层19上方的规定位置上开口,用键合线连接金布线层19和外部连接端子(未图示)。
图5是用于说明该发明的其它实施方式的半导体装置的构成的剖面图。在该图5中,在对应于上述图1所示的各部的部分上付与与图1相同的标记。
在该实施方式中,代替聚酰亚胺树脂膜18,通过氮化硅膜25形成钝化膜。即,从图4(e)的状态,剥离抗蚀层24,通过蚀刻除去种晶层19S以及阻挡层20的不要部分后,例如通过在整个面上基于等离子CVD法形成氮化硅膜25,得到图5所示构成的半导体装置。
在该构成中,由于利用致密的并且钝化效应高的氮化硅膜25,因此可以提高耐腐蚀性。在通过等离子CVD法形成氮化硅膜25时,半导体装置变为被置于高温环境下,但是即使在该情况下,也不发生金从金布线层19向铝布线层14扩散的现象。
以上,对该两个实施方式进行了说明,但是本发明也可以通过其它实施方式来实现。例如,在图1的构成中,作为钝化膜使用聚酰亚胺树脂膜18,在图5的构成中,作为钝化膜使用氮化硅膜25,但是这些也均可以不设置钝化膜。即使在这种情况下,表面露出的金布线层19具有充分的耐腐蚀性,层间绝缘膜16的表面也由钝化效应高的氮化硅膜16S构成,而且阻挡层20的耐腐蚀性也良好,因此,半导体装置作为整体也可以具有充分的耐腐蚀性。
另外,作为层间绝缘膜13,除了BPSG之外,例如也可以使用PSG(掺杂磷的硅氧化膜)或USG膜。
进而,也可以在沉积的USG层16U上利用SOG(Spin On Glass)法,涂布容易形成壁厚的由硅化合物构成的有机绝缘物(有机SOG)构成的有机SOG层26(参照图1以及图5等),填埋USG层16U的上面的凹部后,通过高密度等离子CVD法形成氮化硅膜16S。
对于本发明的实施方式进行了详细的说明,但是本发明的技术内容并不限定于这些,只要不脱离本发明的技术构思,其它变更都包括在本发明之内。
本申请与2003年8月11日在日本专利局提出的申请2003-291624号对应,该申请的全部内容都包括在该申请中。
Claims (12)
1.一种半导体装置,包括:形成于半导体基板上的第一布线层;
形成于该第一布线层上的层间绝缘膜;
在该层间绝缘膜上形成的由金层构成的作为最上层布线层的第二布线层;
在形成于上述层间绝缘膜上的层间连接用开口内,夹持在上述第一布线层与第二布线层之间的阻挡层,
所述阻挡层具有与上述第一布线层接触并使接触电阻减少的第一层、与上述第二布线层接触并使粘接强度提高的第二层、以及夹持在上述第一层与上述第二层之间的第三层。
2.根据权利要求1所述的半导体装置,其中,上述第一层是第一钽层,上述第二层是第二钽层,上述第三层是氮化钽层。
3.根据权利要求2所述的半导体装置,其中,上述氮化钽层的氮原子密度分布,是在上述第一钽层侧的氮原子密度低于在上述第二钽层侧的氮原子密度。
4.根据权利要求1~3中任一项所述的半导体装置,其中,上述层间绝缘膜包括覆盖其整个表层部的氮化硅膜。
5.根据权利要求1所述的半导体装置,其中,进一步包括覆盖上述第二布线层和上述层间绝缘膜的聚酰亚胺树脂膜。
6.根据权利要求1所述的半导体装置,其中,进一步包括覆盖上述第二布线层和上述层间绝缘膜的氮化硅膜。
7.一种半导体装置的制造方法,用于制造其构成为借助形成于上述层间绝缘膜上的层间连接用开口对夹持层间绝缘膜而形成的第一布线层和第二布线层进行电连接的半导体装置,包括:
在半导体基板上形成上述第一布线层的工序;
以覆盖该第一布线层的方式形成上述层间绝缘膜的工序;
在该层间绝缘膜的规定位置上形成使上述第一布线层露出的上述层间连接用开口的工序;
在上述层间连接用开口内形成阻挡层的工序;
在上述层间绝缘膜上形成与上述阻挡层接触而由金层构成的作为最上层布线层的上述第二布线层的工序,
上述阻挡层具有与上述第一布线层接触而使接触电阻降低的第一层、与上述第二布线层接触而使粘接强度提高的第二层、以及夹持在上述第一层和第二层之间的第三层的叠层结构。
8.根据权利要求7所述的半导体装置的制造方法,其中,上述第一层是第一钽层,上述第二层是第二钽层,上述第三层是氮化钽层。
9.根据权利要求8所述的半导体装置的制造方法,其中,形成上述阻挡层的工序包括通过连续溅射法形成第一钽层、氮化钽层以及第二钽层的连续溅射工序,
该连续溅射工序,包括:在处理室内通过以钽作为靶的溅射形成第一钽层的工序;之后,在处理室内导入氮气在氮气气氛中进行以钽作为靶的溅射,从而形成氮化钽层的工序;之后,从处理室排除氮气并通过以钽作为靶的溅射形成第二钽层的工序。
10.根据权利要求7~9中任一项所述的半导体装置的制造方法,其中,形成上述层间绝缘膜的工序,包括形成覆盖其整个表层部的氮化硅膜的工序。
11.根据权利要求7所述的半导体装置的制造方法,其中,进一步包括形成覆盖上述第二布线层和上述层间绝缘膜的聚酰亚胺树脂膜的工序。
12.根据权利要求7所述的半导体装置的制造方法,其中,进一步包括形成覆盖上述第二布线层和上述层间绝缘膜的氮化硅膜的工序。
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US8552559B2 (en) * | 2004-07-29 | 2013-10-08 | Megica Corporation | Very thick metal interconnection scheme in IC chips |
US8022552B2 (en) * | 2006-06-27 | 2011-09-20 | Megica Corporation | Integrated circuit and method for fabricating the same |
US8421227B2 (en) * | 2006-06-28 | 2013-04-16 | Megica Corporation | Semiconductor chip structure |
US8592977B2 (en) * | 2006-06-28 | 2013-11-26 | Megit Acquisition Corp. | Integrated circuit (IC) chip and method for fabricating the same |
TWI460820B (zh) * | 2006-06-28 | 2014-11-11 | Qualcomm Inc | 積體電路(ic)晶片及其製程 |
US8193636B2 (en) * | 2007-03-13 | 2012-06-05 | Megica Corporation | Chip assembly with interconnection by metal bump |
JP5369544B2 (ja) * | 2008-08-29 | 2013-12-18 | 富士通株式会社 | 半導体装置およびその製造方法 |
US10199342B2 (en) * | 2017-01-23 | 2019-02-05 | Globalfoundries Singapore Pte. Ltd. | Reliable pad interconnects |
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JP2558932B2 (ja) * | 1990-07-24 | 1996-11-27 | 松下電器産業株式会社 | 化合物半導体集積回路 |
JP2811126B2 (ja) * | 1991-05-02 | 1998-10-15 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
JPH07283219A (ja) * | 1994-04-13 | 1995-10-27 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法および半導体装 置の製造装置 |
JPH08293522A (ja) | 1995-04-24 | 1996-11-05 | Mitsubishi Materials Corp | 半導体装置の耐熱電極 |
JP2000331991A (ja) | 1999-03-15 | 2000-11-30 | Sony Corp | 半導体装置の製造方法 |
US6339258B1 (en) * | 1999-07-02 | 2002-01-15 | International Business Machines Corporation | Low resistivity tantalum |
US6521532B1 (en) * | 1999-07-22 | 2003-02-18 | James A. Cunningham | Method for making integrated circuit including interconnects with enhanced electromigration resistance |
JP2001053077A (ja) | 1999-08-13 | 2001-02-23 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6376370B1 (en) * | 2000-01-18 | 2002-04-23 | Micron Technology, Inc. | Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
US6548328B1 (en) | 2000-01-31 | 2003-04-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
WO2001066832A2 (en) * | 2000-03-07 | 2001-09-13 | Asm America, Inc. | Graded thin films |
JP3954312B2 (ja) * | 2001-01-15 | 2007-08-08 | ローム株式会社 | 半導体装置の製造方法 |
US6590288B1 (en) * | 2001-06-04 | 2003-07-08 | Advanced Micro Devices, Inc. | Selective deposition in integrated circuit interconnects |
TW518680B (en) * | 2001-06-13 | 2003-01-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for fabricating the same |
JP4704633B2 (ja) | 2001-09-27 | 2011-06-15 | 株式会社デンソー | パターン形成方法および金属膜パターニング用粘着シート |
US6605874B2 (en) * | 2001-12-19 | 2003-08-12 | Intel Corporation | Method of making semiconductor device using an interconnect |
CN1200456C (zh) * | 2002-09-27 | 2005-05-04 | 上海华虹(集团)有限公司 | 基于a1材料的掺铜金属布线工艺 |
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US7372163B2 (en) | 2008-05-13 |
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