CN106560915B - 元件芯片的制造方法和电子部件安装结构体的制造方法 - Google Patents

元件芯片的制造方法和电子部件安装结构体的制造方法 Download PDF

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CN106560915B
CN106560915B CN201610865508.7A CN201610865508A CN106560915B CN 106560915 B CN106560915 B CN 106560915B CN 201610865508 A CN201610865508 A CN 201610865508A CN 106560915 B CN106560915 B CN 106560915B
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protective film
substrate
manufacturing
component
carrier
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CN106560915A (zh
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针贝笃史
置田尚吾
松原功幸
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Panasonic Intellectual Property Management Co Ltd
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Abstract

本发明提供一种元件芯片的制造方法和电子部件安装结构体的制造方法。在将在元件区域形成了元件电极露出的凸部的基板进行分割来制造多个元件芯片(10)的元件芯片的制造方法中，通过蚀刻将基板进行分割后，使元件芯片(10)暴露于第2等离子体(P2)，由此在元件芯片(10)的第2面(10b)、侧面(10c)、空隙部(S)的第1面(10a)，形成由氟碳膜构成的保护膜，接下来使元件芯片(10)暴露于第3等离子体(P3)，由此使形成于空隙部(S)的保护膜的至少一部分残留，去除形成在元件芯片(10)的第2面(10b)、侧面(10c)的保护膜。由此，通过残留的保护膜来抑制安装过程中的导电性材料的爬升。

Description

元件芯片的制造方法和电子部件安装结构体的制造方法
技术领域
本发明涉及将具有多个元件区域的基板按照每个元件区域进行分割来制造元件芯片的元件芯片的制造方法以及将该元件芯片安装于基板而成的电子部件安装结构体的制造方法。
背景技术
半导体元件等元件芯片从具有多个元件区域的晶片状的基板分割成单片来制造(例如参照专利文献1)。在该专利文献所示的现有技术中，首先在将形成了电路的晶片的表面粘贴于切割带的状态下对晶片的背面进行研磨，再进一步通过蚀刻使晶片变薄。而且之后在与元件区域相当的部分形成抗蚀剂层来进行掩蔽，通过实施等离子体蚀刻，从而将晶片分离成单片的半导体元件。
现有技术文献
专利文献
专利文献1：JP特开2002-93752号公报
发明内容
如上所述从晶片状的基板切割出的单片状的元件芯片除了实施封装来用作器件装置以外，还存在将倒装芯片等元件芯片直接送到电子部件安装工序的情况。在这样的情况下，元件芯片以使电路形成面与接合用的膏状焊料、银膏剂等导电性材料直接接触的方式进行安装。在该安装过程中，在元件芯片搭载时受压展开的导电性材料不仅触及电路形成面的接合部位，还存在浸润扩散到元件芯片的侧面、背面的情况，即产生所谓的“爬升”。这样的导电性材料的爬升会导致相邻的电极间的短路、在元件芯片的侧面形成无用的电路致使消耗电流的增大等各种不良状况的发生。为此，需要抑制这样的安装过程中的导电性材料的爬升。
因此，本发明的目的在于，提供一种能够抑制安装过程中的导电性材料的爬升的元件芯片的制造方法以及电子部件安装结构体的制造方法。
本发明的元件芯片的制造方法是将具备具有由分割区域划分的多个元件区域的第1面和与所述第1面相反一侧的第2面、并且在元件区域形成了元件电极露出的凸部的基板，按分割区域进行分割来制造多个元件芯片的元件芯片的制造方法，包括准备工序和等离子体处理工序。准备工序准备如下基板：在通过使凸部接触于载体而在第1面与载体之间形成了空隙部的状态下，基板的第1面侧被支承于所述载体，并且形成了耐蚀刻层使得覆盖与元件区域对置的第2面的区域并且使与分割区域对置的第2面的区域露出。等离子体处理工序在准备工序之后，对支承于载体的基板实施等离子体处理。等离子体处理工序包括分割工序、保护膜形成工序和保护膜去除工序。分割工序通过使第2面暴露于第1等离子体，从而将未被耐蚀刻层覆盖的区域的基板蚀刻到在该基板的深度方向上达到所述第1面来将基板分割为元件芯片，成为具备第1面、第2面以及将第1面与第2面连结的侧面的元件芯片彼此空开间隔保持在载体上的状态。保护膜形成工序在分割工序之后，在彼此空开间隔保持在载体上的状态下使元件芯片暴露于提供保护膜形成用气体的同时产生的第2等离子体，由此在元件芯片的第2面、元件芯片的侧面和空隙部的第1面形成保护膜。保护膜去除工序在保护膜形成工序之后，在彼此空开间隔保持在载体上的状态下使元件芯片暴露于提供保护膜蚀刻用气体的同时产生的第3等离子体，由此使形成于空隙部的保护膜的至少一部分残留，并去除在元件芯片的第2面以及侧面形成的保护膜。
本发明的电子部件安装结构体的制造方法是将通过上述的制造方法而形成的元件芯片的凸部与形成于印刷基板的焊盘电极进行焊料接合而成的电子部件安装结构体的制造方法，包括以下工序。即，包括：焊料膏剂供给工序，向焊盘电极提供膏剂状的焊料；搭载工序，使凸部着落于向对应的焊盘电极提供的焊料膏剂从而搭载于印刷基板；熔融工序，对印刷基板进行加热使焊料熔融来将凸部和焊盘电极进行焊料接合；和冷却工序，对印刷基板进行冷却来使熔融了的焊料固化，在熔融工序中，空隙部的保护膜抑制熔融了的焊料在所述空隙部中的扩散。
根据本发明，能够抑制安装过程中的导电性材料的爬升。
附图说明
图1A是本发明的一实施方式的元件芯片的制造方法的工序说明图，是表示分离前的基板的剖视图。
图1B是本发明的一实施方式的元件芯片的制造方法的工序说明图，是表示准备工序的剖视图。
图1C是本发明的一实施方式的元件芯片的制造方法的工序说明图，是表示进行等离子体处理对基板进行分割的工序的剖视图。
图2A是本发明的一实施方式的元件芯片的制造方法的工序说明图，是表示灰化工序的剖视图。
图2B是本发明的一实施方式的元件芯片的制造方法的工序说明图，是表示保护膜形成工序的剖视图。
图2C是本发明的一实施方式的元件芯片的制造方法的工序说明图，是表示等离子体处理工序的剖视图。
图3是在本发明的一实施方式的元件芯片的制造方法中使用的等离子体蚀刻装置的结构说明图。
图4A是本发明的一实施方式的元件芯片的制造方法中的保护膜形成的放大说明图，是表示形成了保护膜的状态的剖视图。
图4B是本发明的一实施方式的元件芯片的制造方法中的保护膜形成的放大说明图，是表示去除了保护膜的状态的剖视图。
图5是通过本发明的一实施方式的元件芯片的制造方法而制造的元件芯片的结构说明图。
图6A是本发明的一实施方式的电子部件安装结构体的制造方法的工序说明图，是表示膏剂供给工序的剖视图。
图6B是本发明的一实施方式的电子部件安装结构体的制造方法的工序说明图，是表示元件芯片的搭载工序的剖视图。
图6C是本发明的一实施方式的电子部件安装结构体的制造方法的工序说明图，是表示冷却工序的剖视图。
标号说明
1 基板
1a 第1面
1b 第2面
1c 分割区域
2 元件部
2a 元件区域
3 凸部
4 耐蚀刻层
5 载体
10 元件芯片
10a 第1面
10b 第2面
10c 侧面
12a1、12a2、12b、12c 保护膜
16 焊盘电极
17 焊料
具体实施方式
接下来参照附图对本发明的实施方式进行说明。首先参照图1A～图1C以及图2A～图2C对本实施方式的元件芯片的制造方法进行说明。在此所示的元件芯片的制造方法是如下的制造方法，即，将具备具有由分割区域划分的多个元件区域的第1面和与该第1面相反一侧的第2面、并且在元件区域形成了元件电极露出的凸部的基板，按分割区域进行分割来制造多个元件芯片。
如图1A所示，基板1是在第1面1a制成了具有元件部2的多个元件芯片10参照图1C)的晶片状的基板。在基板1中形成了元件部2的元件面即第1面1a上，设定了由分割区域1c划分的多个元件区域2a。在各个元件区域2a中，形成了连接用的元件电极露出的多个凸部3。基板1被送往用于制造元件芯片的准备工序，如以下说明的那样，进行基于载体(carrier)5的支承和掩膜形成。作为载体5，能够例示由切割架保持的切割带、在保持面5a具备粘接层的支承基板。
在该准备工序中，如图1B所示，通过使凸部3的前端面与载体5的保持面5a接触，从而在第1面1a与载体5之间形成了空隙部S的状态下，基板1的第1面1a侧被支承于载体5的保持面5a，并且在第2面1b由在等离子体切割中作为掩膜而发挥作用的抗蚀剂掩膜、表面保护膜等来形成耐蚀刻层4。即在第2面1b，形成耐蚀刻层4，使得覆盖与元件区域2a对置的第2面1b的区域并且使与分割区域1c对置的第2面1b的区域1d露出。
在这样进行了准备工序后，为了对支承于载体5的基板1实施等离子体处理，将载体5送往等离子体处理工序。参照图3对在该等离子体处理工序中使用的等离子体蚀刻装置20的结构进行说明。在图3中作为真空容器的腔室21的内部是用于进行等离子体处理的处理室21a，在处理室21a的底部配置有对支承了处理对象即基板1的载体5进行载置的台架22。在腔室21的顶部的上表面，配置有作为上部电极的天线23，天线23与第1高频电源部24电连接。处理室21a内的台架22还具有作为用于等离子体处理的下部电极的功能，台架22与第2高频电源部25电连接。
在腔室21，经由排气口21c而连接有真空排气部27，通过驱动真空排气部27，从而将处理室21a内进行真空排气。而且处理室21a经由气体导入口21b而连接有等离子体产生用气体供给部26。在本实施方式所示的等离子体蚀刻装置20中，根据等离子体处理的目的，能够选择性地提供多种等离子体产生用气体。在此，作为等离子体产生用气体的种类，能够选择第1气体26a、第2气体26b、第3气体26c以及灰化(ashing)用气体26d。
作为第1气体26a，使用SF6、C4F8等以硅为对象的蚀刻效果优异的气体。在本实施方式中，第1气体26a用于产生通过等离子体蚀刻来分割基板1的第1等离子体P1。第2气体26b是通过等离子体处理来形成皮膜的等离子体CVD用的气体，使用C4F8、C2F6、CF4、C6F6、C6F4H2、CHF3、CH2F2等氟化碳和氦的混合气体。在本实施方式中，作为在将基板1分割得到的元件芯片10的侧面、第2面1b、空隙部S内的第1面1a形成保护膜的保护膜形成用气体来使用。另外，氦的流量相对于混合气体的总流量的比率可根据气体种类的组合来适当设定。作为例示值，氦相对于混合气体的总流量的比率能够列举10％～80％。
第3气体26c是保护膜蚀刻用气体，使用氧气、氩气等物理性蚀刻效果优异的气体。在本实施方式中，用于去除前述的保护膜当中的不需要的部分的溅射用途。而且，灰化用气体26d为氧气，在本实施方式中，以去除结束掩膜功能后的耐蚀刻层4等树脂膜为目的来使用。
在基于等离子体蚀刻装置20的等离子体处理中，首先将处理对象的基板1与载体5一起载置在台架22上，驱动真空排气部27对处理室21a内进行真空排气。与此同时，通过等离子体产生用气体供给部26向处理室21a内提供与等离子体处理的目的相应的等离子体产生用气体，来维持于规定压力。然后在该状态下通过第1高频电源部24向天线23提供高频功率，由此在处理室21a内产生与所提供的等离子体产生用气体的种类相应的等离子体。此时，通过第2高频电源部25对作为下部电极的台架22施加偏置电压，由此能够对在处理室21a内产生的等离子体发挥促进向台架22的方向的入射的偏置作用，能够提高向希望的特定方向的等离子体处理效果来进行各向异性蚀刻。
在等离子体处理工序中，首先执行使用了前述的第1气体26a的第1等离子体P1的处理。如图1C所示，通过使基板1的第2面1b暴露于上述的第1等离子体P1，从而将未被耐蚀刻层4覆盖的区域1d(参照图1B)的基板1蚀刻到在该基板1的深度方向上达到第1面1a(参照箭头e)，形成将各元件芯片10隔开的蚀刻槽11(参照图2A)，将基板1分割为单片的元件芯片10。即，成为具备在基板1的状态下为第1面1a的第1面10a、为第2面1b的第2面10b以及将第1面10a和第2面10b连结的侧面10c的元件芯片10彼此空开间隔保持在载体5上的状态(分割工序)。
分割工序中的蚀刻条件能够根据基板1的材质来适当选择。在基板1为硅基板的情况下，在分割工序中的蚀刻中，能够使用所谓博世(Bosch)工艺。在博世工艺中，通过依次反复沉积膜沉积步骤、沉积膜蚀刻步骤和硅蚀刻步骤，从而能够将未被耐蚀刻层4覆盖的区域1d在基板的深度方向上垂直掘进。
作为沉积膜沉积步骤的条件，例如，作为原料气体而以150～250sccm提供C4F8的同时，将处理室内的压力调整为15～25Pa，将从第1高频电源部24向天线23的投入功率设为1500～2500W，将从第2高频电源部25向下部电极的投入功率设为0W，并将处理时间设为5～15秒即可。作为沉积膜蚀刻步骤的条件，例如，作为原料气体而以200～400sccm提供SF6的同时，将处理室内的压力调整为5～15Pa，将从第1高频电源部24向天线23的投入功率设为1500～2500W，将从第2高频电源部25向下部电极的投入功率设为100～300W，并将处理时间设为2～10秒即可。另外，sccm是表示气体的流量的单位，1sccm表示在一分钟流过1cm3的标准状态(0℃、1个大气压)的气体。
作为硅蚀刻步骤的条件，例如，作为原料气体而以200～400sccm提供SF6的同时，将处理室内的压力调整为5～15Pa，将从第1高频电源部24向天线23的投入功率设为1500～2500W，将从第2高频电源部25向下部电极的投入功率设为50～200W，并将处理时间设为10～20秒即可。然后，在这些条件下，反复进行沉积膜沉积步骤、沉积膜蚀刻步骤以及硅蚀刻步骤，由此能够以10μm/分钟的速度掘进硅基板。
之后，进行将单片的元件芯片10中覆盖了第2面10b的状态的耐蚀刻层4去除的灰化。即，如图2A所示，在等离子体蚀刻装置20中在处理室21a内产生使用了灰化用气体26d的灰化用等离子体，通过灰化来去除以树脂为主要成分的耐蚀刻层4。由此，成为分割成单片的元件芯片10的第2面10b露出的状态。
灰化的条件能够根据耐蚀刻层4的材料来适当选择。例如，在耐蚀刻层4为抗蚀剂膜的情况下，作为原料气体而以150～300sccm提供氧、以0～50sccm提供CF4的同时，将处理室内的压力调整为5～15Pa，将从第1高频电源部24向天线23的投入功率设为1500～2500W，并将从第2高频电源部25向下部电极的投入功率设为0～30W即可。在该条件下能够以1μm/分钟左右的速度去除耐蚀刻层4。
接着在上述的分割工序之后，执行保护膜形成工序。即在等离子体蚀刻装置20中，在载体5上彼此空开间隔保持的状态下，使元件芯片10暴露在处理室21a内一边提供保护膜形成用气体(氟化碳和氦的混合气体)即第2气体26b的同时一边产生的第2等离子体P2中。由此，如图4A所示，在元件芯片10的第2面10b、侧面10c，保护膜形成用气体中的氟化碳在等离子体中分解，然后沉积，从而分别形成覆膜化的保护膜12b、12c，并且在第1面10a与载体5之间的空隙部S内也形成同样的保护膜，其中保护膜12b、12c由包含氟和碳的氟碳膜构成。
即，在空隙部S当中的位于相邻的凸部3之间的空隙部S1中，在第1面10a形成保护膜12a1，此外在凸部3的侧面形成保护膜12d，进而在载体5的保持面5a形成保护膜12e。而且在空隙部S当中的位于凸部3的外侧的空隙部S2中，在第1面10a形成保护膜12a2，此外在凸部3的侧面形成保护膜12d，进而在载体5的保持面5a形成保护膜12e。
这些保护膜由于是以抑制在将元件芯片10直接与封装基板等进行接合的安装过程中的导电性材料的爬升为目的而形成的，因此期望其吸湿性小且组成致密。在本实施方式中，作为用于形成这些保护膜的第2等离子体P2的原料气体，由于使用包含氟化碳和氦的混合气体的保护膜形成用气体，因此能够形成吸湿性小、组成致密并且密接性优异的由氟碳膜构成的保护膜。另外在该保护膜形成工序中，对载置载体5的台架22(参照图3)施加高频偏置。由此，能够促进向元件芯片10的离子的入射，能够形成更致密且密接性高的保护膜。
作为保护膜的形成条件，例如，作为原料气体而以150sccm提供C4F8、以50sccm提供He的同时，将处理室内的压力调整为15～25Pa，将从第1高频电源部24向天线23的投入功率设为1500～2500W，并将从第2高频电源部25向下部电极的投入功率设为50～150W即可。通过在该条件下进行300秒处理，从而能够形成厚度3μm的保护膜。
在本实施方式中，作为原料气体而使用氟化碳和氦的混合气体，这是因为通过混合氦，从而促进在等离子体中的原料气体的分离，作为其结果，能够形成致密且密接性高的保护膜。
另外，在上述的条件例中，He流量相对于原料气体的总流量的比率为25％(＝50/(150+50)×100)。如以下说明的那样，该比率期望处于10％至80％之间。即若He流量相对于原料气体的总流量的比率大于10％，则容易促进在等离子体中的原料气体的分离，作为其结果，变得容易形成更致密且密接性高的保护膜。另一方面，若He流量相对于原料气体的总流量的比率大于80％，则由于C4F8占据原料气体的比率减少，因此有助于保护膜形成的等离子体中的成分(C、F以及它们的化合物)向基板表面的供给不足，基板表面上的保护膜的沉积速度变慢，生产性下降。
接下来执行用于去除由保护膜形成工序形成的保护膜当中的不需要的部分的保护膜去除工序。在上述的保护膜形成工序中，在元件芯片10的第1面10a、侧面10c以及第2面10b也都形成保护膜12b(参照图2B)。在本实施方式中，由于这些保护膜12b、12c并无必要，因此进行使用了用于去除这些保护膜的第3等离子体P3的等离子体处理。
即，在等离子体蚀刻装置20中，在处理室21a内，提供以氩气、氧气为成分的保护膜蚀刻用气体即第3气体26c的同时产生第3等离子体P3，如图2C所示，在载体5上彼此空开间隔保持的状态下，使元件芯片10暴露于第3等离子体P3。由此，使形成于空隙部S的保护膜的至少一部分残留，通过第3等离子体P3的蚀刻作用而将元件芯片10中露出于上表面的形成于第2面10b的保护膜12b、形成于侧面10c的保护膜12c去除。
由此，图4B所示，成为元件芯片10的第2面10b以及侧面10c露出的状态，附着于载体5的上表面的保护膜12e当中的未被元件芯片10覆盖的范围的保护膜12e也被去除。然后在空隙部S当中的位于相邻的凸部3之间的空隙部S1中，第1面10a的保护膜12a1以及凸部3的侧面的保护膜12d还残留。此外在空隙部S当中的位于凸部3的外侧的空隙部S2中，第1面10a的保护膜12a2还残留，此外在凸部3的侧面保护膜12d未被去除而残留。
作为保护膜去除的条件，例如，作为原料气体而以150～300sccm提供Ar、以0～150sccm提供O2的同时，将处理室内的压力调整为0.2～1.5Pa，将从第1高频电源部24向天线23的投入功率设为1500～2500W，并将从第2高频电源部25向下部电极的投入功率设为150～300W即可。在该条件下，能够以0.5μm/分钟左右的速度对露出于上表面的保护膜进行蚀刻。
图5示出了通过这样的制造过程而制造的元件芯片10。即，从载体5按照每个单片取出的元件芯片10在第1面10a形成有保护膜12a1、12a2，并且具有覆盖凸部3的侧面的保护膜12d，凸部3的上表面露出。另外，在图4B中，在元件芯片10所覆盖的范围的载体5的保持面5a残留的保护膜12e牢固附着于载体5的保持面5a。另一方面，在图4B中，覆盖凸部3的侧面的保护膜12d牢固附着于凸部3的侧面。
因此，在从载体5按照每个单片取出元件芯片10时，在载体5的保持面5a残留的保护膜12e从元件芯片10分离。具有这样的结构的元件芯片10在如以下说明的那样不经过树脂封装等工序而通过焊料接合直接安装于印刷基板等从而形成电子部件安装结构体的情况下，具有抑制第1面10a上的膏状焊料等导电性材料的浸润扩散，防止导电性材料的爬升这样的效果。
以下，参照图6A～C，对将通过上述的元件芯片的制造方法而形成的元件芯片10与形成于印刷基板的焊盘电极进行焊料接合而成的电子部件安装结构体的制造方法进行说明。在图6A中，在印刷基板15的上表面，对应于作为元件芯片10的连接用的元件电极的凸部3，形成了焊盘电极16。在焊盘电极16上，在元件芯片10的搭载之前，提供膏剂状的焊料17(膏剂供给工序)。
在膏剂供给工序后的印刷基板15上，搭载元件芯片10(搭载工序)。即将元件芯片10的凸部3与对应的焊盘电极16对准位置，如图6B所示，使凸部3着落于焊盘电极16上的焊料17。由此，元件芯片10被搭载于印刷基板15。
接下来搭载工序后的印刷基板15被送往回流焊工序，在此进行用于焊料接合的加热。即对印刷基板15进行加热，使焊料17熔融而将凸部3和焊盘电极16进行焊料接合(熔融工序)。然后，对印刷基板15进行冷却，使熔融的焊料冷却固化(冷却工序)。由此，如图6C所示，形成将凸部3和焊盘电极16焊料接合的焊料接合部17*。
如上所述，在空隙部S1、S2中，在第1面10a残留有保护膜12a1、12a2，因此在熔融工序中焊料17熔融后的熔融焊料与保护膜12a1、12a2。因为保护膜12a1、12a2的表面性状具有抑制熔融焊料的浸润扩散的特性，所以在熔融工序中焊料17熔融后的熔融焊料在空隙部S1、S2内不会沿着第1面10a扩散而是在凸部3和焊盘电极16的周围冷却固化，形成良好的焊料接合部17*。即，在上述的熔融工序中，空隙部S1、S2的保护膜12a1、12a2抑制熔融的焊料17在空隙部S1、S2中的扩散。
本发明的元件芯片的制造方法以及电子部件安装结构体的制造方法具有能够抑制安装过程中的导电性材料的爬升的效果，在将具有多个元件区域的基板按照每个元件区域进行分割来制造元件芯片的领域中非常有用。

Claims (4)

1.一种元件芯片的制造方法，将具备具有由分割区域划分的多个元件区域的第1面和与所述第1面相反一侧的第2面、并且在所述元件区域形成了元件电极露出的凸部的基板，按所述分割区域进行分割来制造多个元件芯片，所述元件芯片的制造方法包括：
准备工序，准备在通过使所述凸部接触于载体而在所述第1面与所述载体之间形成了空隙部的状态下，所述基板的所述第1面侧被支承于所述载体，并且形成了耐蚀刻层使得覆盖与所述元件区域对置的所述第2面的区域并且使与所述分割区域对置的所述第2面的区域露出的基板；和
等离子体处理工序，在所述准备工序之后，对支承于所述载体的所述基板实施等离子体处理，
所述等离子体处理工序包括：
分割工序，通过使所述第2面暴露于第1等离子体，从而将未被所述耐蚀刻层覆盖的区域的所述基板蚀刻到在该基板的深度方向上达到所述第1面来将所述基板分割为元件芯片，成为具备所述第1面、所述第2面以及将所述第1面与所述第2面连结的侧面的元件芯片彼此空开间隔保持在所述载体上的状态；
保护膜形成工序，在所述分割工序之后，在彼此空开间隔保持在所述载体上的状态下使所述元件芯片暴露于提供保护膜形成用气体的同时产生的第2等离子体，由此在所述元件芯片的所述第2面、所述元件芯片的所述侧面和所述空隙部处的所述第1面形成保护膜；和
保护膜去除工序，在所述保护膜形成工序之后，在彼此空开间隔保持在所述载体上的状态下使所述元件芯片暴露于提供保护膜蚀刻用气体的同时产生的第3等离子体，由此使形成于所述空隙部处的所述保护膜的至少一部分残留，并去除形成于所述元件芯片的所述第2面以及所述侧面的保护膜。
2.根据权利要求1所述的元件芯片的制造方法，所述保护膜为氟碳膜。
3.根据权利要求2所述的元件芯片的制造方法，所述保护膜形成用气体包含氟化碳。
4.一种电子部件安装结构体的制造方法，所述电子部件安装结构体将通过权利要求1至3中任一项所述的元件芯片的制造方法而形成的元件芯片的所述凸部与形成于印刷基板的焊盘电极进行焊料接合而成，所述电子部件安装结构体的制造方法包括：
焊料膏剂供给工序，向所述焊盘电极提供膏剂状的焊料；
搭载工序，使所述凸部着落于向对应的所述焊盘电极提供的焊料膏剂从而搭载于所述印刷基板；
熔融工序，对所述印刷基板进行加热使所述焊料熔融来将所述凸部与焊盘电极进行焊料接合；和
冷却工序，对所述印刷基板进行冷却来使熔融了的所述焊料固化，
在所述熔融工序中，所述空隙部的所述保护膜抑制熔融了的焊料在所述空隙部中的扩散。
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