JP2017069472A - 素子チップの製造方法および電子部品実装構造体の製造方法 - Google Patents
素子チップの製造方法および電子部品実装構造体の製造方法 Download PDFInfo
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- JP2017069472A JP2017069472A JP2015195520A JP2015195520A JP2017069472A JP 2017069472 A JP2017069472 A JP 2017069472A JP 2015195520 A JP2015195520 A JP 2015195520A JP 2015195520 A JP2015195520 A JP 2015195520A JP 2017069472 A JP2017069472 A JP 2017069472A
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- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
Description
1a 第1の面
1b 第2の面
1c 分割領域
2 素子部
2a 素子領域
3 凸部
4 耐エッチング層
5 キャリア
10 素子チップ
10a 第1の面
10b 第2の面
10c 側面
12a1,12a2,12b,12c 保護膜
16 ランド電極
17 半田
Claims (4)
- 分割領域で画定された複数の素子領域を有する第1の面と前記第1の面と反対側の第2の面とを備え、前記素子領域に素子電極が露出した凸部が形成された基板を、前記分割領域で分割して複数の素子チップを製造する素子チップの製造方法であって、
前記凸部をキャリアに接触させることにより前記第1の面と前記キャリアとの間に空隙部が形成された状態で、前記基板の前記第1の面の側が前記キャリアに支持されるとともに、前記素子領域と対向する前記第2の面の領域を覆い且つ前記分割領域と対向する前記第2の面の領域を露出させるように耐エッチング層が形成された基板を準備する準備工程と、
前記準備工程の後、前記キャリアに支持された前記基板にプラズマ処理を施すプラズマ処理工程とを含み、
前記プラズマ処理工程は、
前記第2の面を第1のプラズマに晒すことにより、前記耐エッチング層に覆われていない領域の前記基板をこの基板の深さ方向に前記第1の面に達するまでエッチングして前記基板を素子チップに分割し、前記第1の面、前記第2の面および前記第1の面と前記第2の面とを結ぶ側面を備える素子チップが前記キャリア上に互いに間隔をあけて保持された状態とする分割工程と、
前記分割工程の後、前記キャリア上に互いに間隔をあけて保持された状態で前記素子チップを保護膜形成用ガスを供給しながら発生させた第2のプラズマに晒すことにより、前記素子チップの前記第2の面と、前記素子チップの前記側面と、前記空隙部の前記第1の面に保護膜を形成する保護膜形成工程と、
前記保護膜形成工程の後、前記キャリア上に互いに間隔をあけて保持された状態で前記素子チップを保護膜エッチング用ガスを供給しながら発生させた第3のプラズマに晒すことにより、前記空隙部に形成された前記保護膜の少なくとも一部を残存させて前記素子チップの前記第2の面および前記側面に形成された保護膜を除去する保護膜除去工程と、を含む素子チップの製造方法。 - 前記保護膜がフルオロカーボン膜である、請求項1に記載の素子チップの製造方法。
- 前記保護膜形成用ガスがフッ化炭素を含む、請求項2に記載の素子チップの製造方法。
- 請求項1から3に記載の素子チップの製造方法によって形成された素子チップの前記凸部を、プリント基板に形成されたランド電極に半田接合して成る電子部品実装構造体の製造方法であって、
前記ランド電極にペースト状の半田を供給する半田ペースト供給工程と、
前記凸部を対応する前記ランド電極に供給された半田ペーストに着地させて前記プリント基板に搭載する搭載工程と、
前記プリント基板を加熱して前記半田を溶融させて前記凸部とランド電極とを半田接合する溶融工程と、
前記プリント基板を冷却して溶融した前記半田を固化させる冷却工程とを含み、
前記溶融工程において、前記空隙部の前記保護膜が、溶融した半田の前記空隙部における拡がりを抑制する、電子部品実装構造体の製造方法。
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US15/267,059 US9698052B2 (en) | 2015-10-01 | 2016-09-15 | Method of manufacturing element chip and method of manufacturing electronic component-mounted structure using plasma etch to singulate element chip |
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