JP6492288B2 - 素子チップの製造方法 - Google Patents
素子チップの製造方法 Download PDFInfo
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- JP6492288B2 JP6492288B2 JP2015195521A JP2015195521A JP6492288B2 JP 6492288 B2 JP6492288 B2 JP 6492288B2 JP 2015195521 A JP2015195521 A JP 2015195521A JP 2015195521 A JP2015195521 A JP 2015195521A JP 6492288 B2 JP6492288 B2 JP 6492288B2
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- protective film
- plasma
- substrate
- element chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
- H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Description
1a 第1の面
1b 第2の面
1c 分割領域
2 素子部
2a 素子領域
3 耐エッチング層
4 キャリア
10 素子チップ
10a 第1の面
10b 第2の面
10c 側面
12b 第2の保護膜
12c 第1の保護膜
Claims (4)
- 分割領域で画定された複数の素子領域を有する第1の面と前記第1の面と反対側の第2の面とを備える基板を、前記分割領域で分割して複数の素子チップを形成する素子チップの製造方法であって、
前記第1の面の側がキャリアに支持されるとともに、前記素子領域と対向する前記第2の面の領域を覆い且つ前記分割領域と対向する前記第2の面の領域を露出させるように耐エッチング層が形成された前記基板を準備する準備工程と、
前記準備工程の後、前記キャリアに支持された前記基板にプラズマ処理を施すプラズマ処理工程とを含み、
前記プラズマ処理工程は、
前記第2の面を第1のプラズマに晒すことにより、前記耐エッチング層に覆われていない領域の前記基板をこの基板の深さ方向に前記第1の面に達するまでエッチングして前記基板を素子チップに分割し、前記第1の面、前記第2の面および前記第1の面と前記第2の面とを結ぶ側面を備える素子チップが前記キャリア上に互いに間隔をあけて保持された状態とする分割工程と、
前記分割工程の後、前記キャリア上に互いに間隔をあけて保持された状態で前記素子チップを第2のプラズマに晒すことにより、前記素子チップの前記側面に第1の保護膜を形成するとともに、前記第2の面に第2の保護膜を形成する保護膜形成工程と、を含み、
前記保護膜形成工程において、前記第2の保護膜の厚みが前記第1の保護膜の厚みより大きくなるように保護膜形成条件を設定し、
前記分割工程と前記保護膜形成工程とが、プラズマエッチング装置が備える同じ処理室内で行われる、素子チップの製造方法。 - 前記第1の保護膜および第2の保護膜がフルオロカーボン膜である、請求項1に記載の素子チップの製造方法。
- 前記第2のプラズマを生成するための保護膜形成用ガスがフッ化炭素を含む、請求項2に記載の素子チップの製造方法。
- 前記保護膜形成工程において前記処理室の内部の圧力が5Pa以上25Pa以下に調整されるとともに、前記保護膜形成工程を開始する際の隣接する素子チップ間の溝のアスペクト比が5以上100以下である、請求項1乃至3の何れかに記載の素子チップの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015195521A JP6492288B2 (ja) | 2015-10-01 | 2015-10-01 | 素子チップの製造方法 |
US15/264,921 US9698073B2 (en) | 2015-10-01 | 2016-09-14 | Method of manufacturing element chip and element chip |
CN201610867842.6A CN106560916B (zh) | 2015-10-01 | 2016-09-29 | 元件芯片的制造方法 |
Applications Claiming Priority (1)
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JP2015195521A JP6492288B2 (ja) | 2015-10-01 | 2015-10-01 | 素子チップの製造方法 |
Publications (2)
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JP2017069473A JP2017069473A (ja) | 2017-04-06 |
JP6492288B2 true JP6492288B2 (ja) | 2019-04-03 |
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JP2015195521A Active JP6492288B2 (ja) | 2015-10-01 | 2015-10-01 | 素子チップの製造方法 |
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US (1) | US9698073B2 (ja) |
JP (1) | JP6492288B2 (ja) |
CN (1) | CN106560916B (ja) |
Families Citing this family (1)
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JP6476418B2 (ja) * | 2016-02-04 | 2019-03-06 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法および電子部品実装構造体の製造方法 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2788375B1 (fr) * | 1999-01-11 | 2003-07-18 | Gemplus Card Int | Procede de protection de puce de circuit integre |
JP3254207B2 (ja) * | 2000-09-12 | 2002-02-04 | 株式会社半導体エネルギー研究所 | 絶縁膜の作製方法 |
JP2002093752A (ja) | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | 半導体素子分離方法及び半導体素子分離装置 |
JP4508396B2 (ja) * | 2000-10-30 | 2010-07-21 | パナソニック株式会社 | チップ型半導体装置及びその製造方法 |
KR100379563B1 (ko) * | 2001-02-21 | 2003-04-10 | 앰코 테크놀로지 코리아 주식회사 | 플라즈마 에칭법을 이용한 반도체 웨이퍼 가공법 |
JP2003142475A (ja) * | 2001-11-02 | 2003-05-16 | Murata Mfg Co Ltd | 半導体装置の製造方法 |
JP3904496B2 (ja) * | 2002-09-06 | 2007-04-11 | 株式会社リコー | 半導体装置の製造方法 |
US6794230B2 (en) * | 2002-10-31 | 2004-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach to improve line end shortening |
JP3966168B2 (ja) * | 2002-11-20 | 2007-08-29 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP4013753B2 (ja) * | 2002-12-11 | 2007-11-28 | 松下電器産業株式会社 | 半導体ウェハの切断方法 |
JP3991872B2 (ja) * | 2003-01-23 | 2007-10-17 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP3915992B2 (ja) * | 2004-06-08 | 2007-05-16 | ローム株式会社 | 面実装型電子部品の製造方法 |
JP2006156539A (ja) * | 2004-11-26 | 2006-06-15 | National Institute Of Advanced Industrial & Technology | プラズマ反応用ガス |
JP4629421B2 (ja) * | 2004-12-06 | 2011-02-09 | パナソニック株式会社 | ドライエッチング方法及びドライエッチング装置 |
JP4275096B2 (ja) * | 2005-04-14 | 2009-06-10 | パナソニック株式会社 | 半導体チップの製造方法 |
JP4285455B2 (ja) * | 2005-07-11 | 2009-06-24 | パナソニック株式会社 | 半導体チップの製造方法 |
JP4783169B2 (ja) * | 2006-02-13 | 2011-09-28 | パナソニック株式会社 | ドライエッチング方法、微細構造形成方法、モールド及びその製造方法 |
JP5064985B2 (ja) * | 2006-12-05 | 2012-10-31 | 古河電気工業株式会社 | 半導体ウェハの処理方法 |
JP2008218884A (ja) * | 2007-03-07 | 2008-09-18 | Citizen Holdings Co Ltd | 半導体装置およびその製造方法 |
JP2009260272A (ja) * | 2008-03-25 | 2009-11-05 | Panasonic Corp | 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法 |
JP2010080769A (ja) * | 2008-09-26 | 2010-04-08 | Mitsumi Electric Co Ltd | 半導体装置の製造方法 |
JP2010165963A (ja) * | 2009-01-19 | 2010-07-29 | Furukawa Electric Co Ltd:The | 半導体ウェハの処理方法 |
US20110291300A1 (en) * | 2009-02-12 | 2011-12-01 | Takashi Hirano | Dicing sheet-attached film for forming semiconductor protection film, method for producing semiconductor device using the same, and semiconductor device |
US8642381B2 (en) * | 2010-07-16 | 2014-02-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die |
JP5659033B2 (ja) * | 2011-02-04 | 2015-01-28 | 株式会社東芝 | 半導体装置の製造方法 |
JP5591181B2 (ja) * | 2011-05-19 | 2014-09-17 | パナソニック株式会社 | 半導体チップの製造方法 |
US9257276B2 (en) * | 2011-12-31 | 2016-02-09 | Intel Corporation | Organic thin film passivation of metal interconnections |
US8951915B2 (en) * | 2012-09-11 | 2015-02-10 | Infineon Technologies Ag | Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements |
EP2942807B1 (en) * | 2014-05-07 | 2020-08-26 | Sensirion AG | Semiconductor package |
JP6500230B2 (ja) * | 2015-09-03 | 2019-04-17 | パナソニックIpマネジメント株式会社 | マスクパターンの形成方法および基板の加工方法ならびに素子チップの製造方法 |
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2015
- 2015-10-01 JP JP2015195521A patent/JP6492288B2/ja active Active
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2016
- 2016-09-14 US US15/264,921 patent/US9698073B2/en active Active
- 2016-09-29 CN CN201610867842.6A patent/CN106560916B/zh active Active
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Publication number | Publication date |
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US9698073B2 (en) | 2017-07-04 |
CN106560916B (zh) | 2021-11-09 |
CN106560916A (zh) | 2017-04-12 |
US20170098591A1 (en) | 2017-04-06 |
JP2017069473A (ja) | 2017-04-06 |
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