JP6524419B2 - 素子チップの製造方法 - Google Patents
素子チップの製造方法 Download PDFInfo
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- JP6524419B2 JP6524419B2 JP2016019868A JP2016019868A JP6524419B2 JP 6524419 B2 JP6524419 B2 JP 6524419B2 JP 2016019868 A JP2016019868 A JP 2016019868A JP 2016019868 A JP2016019868 A JP 2016019868A JP 6524419 B2 JP6524419 B2 JP 6524419B2
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/0005—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
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- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
Description
1a 第1の面
1b 第2の面
1c 分割領域
2 素子部
2a 素子領域
3 耐エッチング層
4 キャリア
10 素子チップ
10a 第1の面
10b 第2の面
10c 側面
12 保護膜
Claims (6)
- 分割領域で画定された複数の素子領域を有する第1の面と前記第1の面と反対側の第2の面とを備える基板を、前記分割領域で分割して複数の素子チップを形成する素子チップの製造方法であって、
前記第1の面の側がキャリアに支持されるとともに、前記素子領域と対向する前記第2の面の領域を覆い且つ前記分割領域と対向する前記第2の面の領域を露出させるように耐エッチング層が形成された前記基板を準備する準備工程と、
前記準備工程の後、前記キャリアに支持された前記基板にプラズマ処理を施すプラズマ処理工程とを含み、
前記プラズマ処理工程は、
前記第2の面を第1のプラズマに晒すことにより、前記耐エッチング層に覆われていない領域の前記基板をこの基板の深さ方向に前記第1の面に達するまでエッチングして前記基板を素子チップに分割し、前記第1の面、前記第2の面および前記第1の面と前記第2の面とを結ぶ側面を備える素子チップが前記キャリア上に互いに間隔をあけて保持された状態とする分割工程と、
前記分割工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを保護膜形成用ガスを供給しながら発生させた第2のプラズマに晒すことにより、前記素子チップの前記側面のみに保護膜を形成する保護膜形成工程とを含み、
前記保護膜形成工程において、前記第2の面と前記側面とが成す角部が、鈍角となるように削られる、素子チップの製造方法。 - 分割領域で画定された複数の素子領域を有する第1の面と前記第1の面と反対側の第2の面とを備える基板を、前記分割領域で分割して複数の素子チップを形成する素子チップの製造方法であって、
前記第2の面の側がキャリアに支持されるとともに、前記素子領域を覆い且つ前記分割領域を露出させるように耐エッチング層が形成された前記基板を準備する準備工程と、
前記準備工程の後、前記キャリアに支持された前記基板にプラズマ処理を施すプラズマ処理工程とを含み、
前記プラズマ処理工程は、
前記第1の面を第1のプラズマに晒すことにより、前記耐エッチング層に覆われていない領域の前記基板をこの基板の深さ方向に前記第2の面に達するまでエッチングして前記基板を素子チップに分割し、前記第1の面、前記第2の面および前記第1の面と前記第2の面とを結ぶ側面を備える素子チップが前記キャリア上に互いに間隔をあけて保持された状態とする分割工程と、
前記分割工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを保護膜形成用ガスを供給しながら発生させた第2のプラズマに晒すことにより、前記素子チップの前記側面のみに保護膜を形成する保護膜形成工程とを含み、
前記保護膜形成工程において、前記第1の面と前記側面とが成す角部が、鈍角となるように削られる、素子チップの製造方法。 - 前記保護膜形成工程において、前記キャリアが載置されるステージに高周波バイアスを印加する、請求項1または2に記載の素子チップの製造方法。
- 前記保護膜がフルオロカーボンを主成分とする膜である、請求項1から3のいずれかに記載の素子チップの製造方法。
- 前記保護膜形成用ガスがフッ化炭素を含む、請求項4に記載の素子チップの製造方法。
- 前記保護膜形成用ガスがアルゴンを含む、請求項1から5のいずれかに記載の素子チップの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2016019868A JP6524419B2 (ja) | 2016-02-04 | 2016-02-04 | 素子チップの製造方法 |
US15/408,703 US10475704B2 (en) | 2016-02-04 | 2017-01-18 | Method of manufacturing element chip and element chip |
CN201710053291.4A CN107039343B (zh) | 2016-02-04 | 2017-01-23 | 元件芯片的制造方法 |
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JP2016019868A JP6524419B2 (ja) | 2016-02-04 | 2016-02-04 | 素子チップの製造方法 |
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JP6524419B2 true JP6524419B2 (ja) | 2019-06-05 |
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CN107039343B (zh) | 2021-10-26 |
JP2017139371A (ja) | 2017-08-10 |
US20170229365A1 (en) | 2017-08-10 |
CN107039343A (zh) | 2017-08-11 |
US10475704B2 (en) | 2019-11-12 |
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