TWI423409B - 晶片結構及其晶片接合結構與製造方法 - Google Patents

晶片結構及其晶片接合結構與製造方法 Download PDF

Info

Publication number
TWI423409B
TWI423409B TW099112291A TW99112291A TWI423409B TW I423409 B TWI423409 B TW I423409B TW 099112291 A TW099112291 A TW 099112291A TW 99112291 A TW99112291 A TW 99112291A TW I423409 B TWI423409 B TW I423409B
Authority
TW
Taiwan
Prior art keywords
bump
wafer
bump portion
bumps
layer
Prior art date
Application number
TW099112291A
Other languages
English (en)
Other versions
TW201138035A (en
Inventor
Ching San Lin
Original Assignee
Raydium Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raydium Semiconductor Corp filed Critical Raydium Semiconductor Corp
Priority to TW099112291A priority Critical patent/TWI423409B/zh
Priority to US13/089,449 priority patent/US20110254152A1/en
Publication of TW201138035A publication Critical patent/TW201138035A/zh
Priority to US13/862,383 priority patent/US20130249086A1/en
Application granted granted Critical
Publication of TWI423409B publication Critical patent/TWI423409B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H01L2224/11622—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1355—Shape
    • H01L2224/13551—Shape being non uniform
    • H01L2224/13552—Shape being non uniform comprising protrusions or indentations
    • H01L2224/13553—Shape being non uniform comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134—Bonding interfaces of the bump connector
    • H01L2224/81345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

晶片結構及其晶片接合結構與製造方法
本發明是關於一種晶片結構及其晶片接合結構與製造方法；具體而言，本發明是關於一種可防止短路的晶片結構及其製造方法，以及使用此晶片結構的晶片接合結構及其製造方法。
隨著積體電路(integrated circuit，IC)製程的進步，現今的積體電路產品，尤其是中央處理器(CPU)、記憶體等精密度較高者，其製程技術已經達到了數十奈米(nm)的等級。近來所發布的22奈米製程中，晶圓中的單一晶粒(die)已經小到可以在指甲大小的面積中容納超過29億個電晶體元件。
運用於液晶顯示器(LCD)模組製程的玻璃覆晶(Chip On Glass，COG)技術，一般是利用異方性導電膠膜(Anisotropic Conductive Film，ACF)將驅動晶片(driver chip)與玻璃基板相接合而設置於其上。圖1為習知的晶片與玻璃基板連接的示意圖。如圖1所示，晶片1藉由異方性導電膠膜2連接玻璃基板3，其中晶片1的凸塊(bump)4藉由異方性導電膠膜2中的導電粒子5與玻璃基板3的導電膜層6電性連接。
在一般狀況下，導電粒子5僅會在相對應的凸塊4與導電膜層6之間形成電性連接。然而，在如前所述的積體電路製程朝向元件密集化發展的趨勢下，晶片1的凸塊4間的間距也相應地往越來越小的趨勢發展，因而增加了凸塊4之間藉由導電粒子5非正常的導通而造成短路的機會。如圖1所示，兩個相鄰的凸塊4之間的導電粒子5排列形成短路8。
為了解決上述由兩個相鄰凸塊4之間因導電粒子5所造成的短路問題，一般的作法是多加一個光罩製程來形成絕緣層於凸塊上，以達到兩個凸塊4之間相互絕緣的效果。然而這種作法需要多耗費一個光罩製程的時間與成本，在今日講求製程的高效率、低成本的趨勢下，並不是一個理想的作法。
本發明的目的在於提供一種晶片結構及其製造方法，利用凸塊材料本身特性與反應物進行反應而形成絕緣層，強化防止短路的效應。
本發明的另一目的在於提供一種晶片結構及其製造方法，以氧化處理的方式加強絕緣的效果，以避免其使用時產生短路。
本發明的又一個目的在於提供一種晶片接合結構及其製造方法，避免先前技術中由導電粒子所造成的短路問題，並節省製程的時間與成本，以符合今日講求製程高效率、低成本的趨勢。
本發明的晶片結構包含晶片、凸塊及絕緣層。複數個凸塊設置於晶片上，分別包含彼此相連接且具有不同的活性的第一凸塊部及第二凸塊部。本發明以對凸塊進行化學反應(例如氧化)處理的方式，使絕緣層形成於第一凸塊部與第二凸塊部中具有較高活性者的表面上，提供絕緣以避免相鄰的凸塊之間產生短路。配合異方性導電膠的使用而將使用此晶片結構的晶片設置於玻璃基板上時，可避免導電膠中的導電粒子在相鄰的凸塊之間造成短路。
本發明提供一種晶片結構及其晶片接合結構與製造方法。在較佳實施例中，本發明的晶片結構及其製造方法使用於薄膜電晶體液晶顯示器(thin film transistor liquid crystal display,TFT-LCD)製程、半導體製程等類似的製程中，本發明的晶片接合結構及其製造方法則可以配合玻璃覆晶技術使用。然而在其他實施例中，本發明的晶片結構、晶片接合結構以及其製造方法可以應用於有塑膠外殼封裝的積體電路及其連接設置。
圖2為本發明晶片結構的一實施例的示意圖。如圖2所示，此晶片結構包含晶片10、凸塊20及絕緣層30。晶片10可以為半導體晶圓的晶粒(die)或經封裝的積體電路。凸塊20設置於晶片10上，包含彼此相連接的第一凸塊部21及第二凸塊部22，其中第一凸塊部21具有比第二凸塊部22高的活性。在較佳實施例中，第一凸塊部21為柱狀體，第二凸塊部22為形成於第一凸塊部21表面的惰性金屬層。在本實施例中，第一凸塊部21採用銅材質，第二凸塊部22則採用黃金材質；然而在其他實施例中，第一凸塊部21可採用例如鋁等其他活性金屬材質，第二凸塊部22則可採用其他惰性金屬材質。絕緣層30包含第一凸塊部21及第二凸塊部22中具有較高活性的第一凸塊部21的元素，例如銅，較佳係藉由使整個凸塊20與反應物進行反應而使得絕緣層30僅形成於凸塊20的一部分，亦即活性較高的第一凸塊部21的周緣表面。絕緣層30具有一定的厚度，以達到絕緣的效果。
當使用晶圓(wafer)製程等類似的製程來製造圖2所示的晶片結構時：晶片10可藉由半導體製程來製造，因此可為晶圓上的晶粒。凸塊20的第一凸塊部21與第二凸塊部22可採用半導體製程中的晶圓處理流程的沉積(deposition)、微影(photolithography)、蝕刻(etching)等步驟形成於晶片10上。絕緣層30可以利用第一凸塊部21與第二凸塊部22活性不同的特性，以直接使凸塊20與反應物進行反應的方式形成於第一凸塊部21周緣的表面。在其他實施例中，可以僅使部分的凸塊與反應物進行反應，交錯地形成絕緣層於相鄰的凸塊上，而使相鄰的兩個凸塊之間至少有一個絕緣層可以提供絕緣(見圖4)。
在較佳實施例中，可採用氧氣作為反應物，以形成氧化膜層於第一凸塊部21表面而作為絕緣層30；然而在其他實施例中，可採用例如氮氣等其他氣體作為反應物，以形成氮化膜層等其他類型的膜層於第一凸塊部21表面而作為絕緣層30。在本實施例中，絕緣層30為形成於銅材質的第一凸塊部21表面的氧化銅層。由於氧化銅電絕緣的特性，第一凸塊部21表面的氧化銅層可達到絕緣的效果。進行氧化反應的方式可以採用在電漿製程(plasma processing)中於電漿室內通入氧氣，或採用一般常用的高溫熱處理等方式。
圖3為本發明晶片接合結構的一實施例的示意圖。如圖3所示，此晶片接合結構包含晶片10、凸塊20、絕緣層30、基板40及導電層50，其中晶片10、凸塊20及絕緣層30的結構以及彼此之間的結構關係如前所述。基板40則包含相隔設置的複數個導電膜層41，每個凸塊20對應於一個導電膜層41。導電層50連接於基板40與晶片10之間，其中包含絕緣膠材51及多個導電粒子52，使各凸塊20的第二凸塊部22藉由導電粒子52與對應的導電膜層41相互電性連接。在較佳實施例中，基板40可為玻璃材質，導電膜層41可為形成於基板40上的金屬電極層，導電層50則可採用異方性導電膠膜；然而在其他實施例中，可分別採用其他材質。
如圖3所示，即使兩個凸塊20之間的導電粒子52排列形成導通路徑53，也可以藉由形成於第一凸塊部21周緣的絕緣層30所提供的絕緣使得兩個相鄰的凸塊20的第一凸塊部21之間不會形成短路，因而避免了先前技術中兩個相鄰的凸塊20之間容易出現短路的問題。
當使用玻璃覆晶技術等類似的製程來製造圖3所示的晶片接合結構時：可提供玻璃基板作為基板40，此時導電膜層41可為形成於玻璃基板上的金屬電極層。晶片10可藉由半導體製程來製造，因此可為晶圓上的晶粒。凸塊20可採用半導體製程中的晶圓處理流程的沉積、微影、蝕刻等步驟形成於於晶片10上。絕緣層30可藉由直接使凸塊20與反應物進行反應而形成於活性較高的第一凸塊部21的周緣表面。基板40與晶片10之間可利用例如異方性導電膠膜的導電層50來相互連接，此時導電層50中所包含的導電粒子52中有一部分夾設於凸塊20與對應的導電膜層41之間，達到使兩者相互電性連接的效果。
形成於每個凸塊的第一凸塊部周緣的絕緣層所提供的絕緣使得兩個相鄰的凸塊的第一凸塊部之間不會形成短路，因而避免了先前技術中兩個相鄰的凸塊之間容易出現短路的問題，同時也節省了先前技術中多加一個光罩製程來形成絕緣層於凸塊上的時間與成本，符合今日講求製程的高效率、低成本的趨勢。
在前述實施例中，每個凸塊20上皆形成有絕緣層30；然而在其他實施例中，可以僅於部分凸塊20上形成絕緣層30。如圖4所示，可以交錯地形成絕緣層30於相鄰的凸塊20上，而使相鄰的兩個凸塊20之間至少有一個絕緣層30可以提供絕緣。此時，形成於相鄰的兩個凸塊20之間的導通路徑53同樣也不會造成短路。
本發明已由上述相關實施例加以描述，然而上述實施例僅為實施本發明的範例。必需指出的是，已揭露之實施例並未限制本發明的範圍。相反地，包含於申請專利範圍之精神及範圍之修改及均等設置均包含於本發明的範圍內。
10．．．晶片
20．．．凸塊
21．．．第一凸塊部
22．．．第二凸塊部
30．．．絕緣層
40．．．基板
41．．．導電膜層
50．．．導電層
51．．．絕緣膠材
52．．．導電粒子
53．．．導通路徑
圖1為習知的晶片與玻璃基板連接的示意圖；
圖2為本發明晶片結構的一實施例的示意圖；
圖3為本發明晶片接合結構的一實施例的示意圖；以及
圖4為本發明晶片接合結構的另一實施例的示意圖。
10．．．晶片
20．．．凸塊
21．．．第一凸塊部
22．．．第二凸塊部
30．．．絕緣層
40．．．基板
41．．．導電膜層
50．．．導電層
51．．．絕緣膠材
52．．．導電粒子
53．．．導通路徑

Claims (10)

  1. 一種晶片結構，包含：一晶片；至少一凸塊，設置於該晶片，該凸塊包含一第一凸塊部及一第二凸塊部彼此連接且具有不同的活性；以及一絕緣層，包含該第一凸塊部及該第二凸塊部中具有較高活性者的元素，並形成於該第一凸塊部及該第二凸塊部中具有較高活性者的表面。
  2. 一種晶片接合結構，包含：一基板，包含相隔設置的複數個導電膜層；一晶片，具有複數個凸塊對應於該些導電膜層；以及一導電層，連接於該基板與該晶片之間，其中該導電層包含複數個導電粒子使各該凸塊與對應的該導電膜層相互電性連接；其中，該些凸塊中的至少其中一個凸塊的一部份與一反應物形成一絕緣層於其部份表面。
  3. 如申請專利範圍第2項所述的晶片接合結構，其中該凸塊包含一第一凸塊部及一第二凸塊部彼此連接且具有不同的活性，且該絕緣層僅形成該第一凸塊部及該第二凸塊部中具有較高活性者的表面。
  4. 如申請專利範圍第3項所述的晶片接合結構，其中該第一凸塊部具有比該第二凸塊部高的活性，且該第二凸塊部包含一惰性金屬層，是藉由該些導電粒子與該導電膜層相互電性連接。
  5. 如申請專利範圍第4項所述的晶片接合結構，其中該惰性金屬層包含黃金，且該第一凸塊部包含銅。
  6. 一種晶片結構的製造方法，包含：提供一晶片；設置至少一凸塊於該晶片，其中該凸塊包含一第一凸塊部及一第二凸塊部彼此連接，且該第一凸塊部位於接近該晶片的一端，該第二凸塊部位於遠離該晶片的一端，其中該第一凸塊部具有比該第二凸塊部還高的活性；以及使該凸塊與一反應物進行反應，以形成一絕緣層僅於該第一凸塊部的表面。
  7. 一種晶片接合結構的製造方法，該方法包含下列步驟：提供一基板，包含相隔設置的複數個導電膜層；提供一晶片，具有複數個凸塊對應於該些導電膜層；使該些凸塊與一反應物進行反應，以形成一絕緣層於該些凸塊中的至少一個凸塊的一部份；以及設置一導電層，使該導電層連接於該基板與該晶片之間，其中該導電層包含複數個導電粒子使各該凸塊與對應的該導電膜層相互電性連接。
  8. 如申請專利範圍第7項所述的晶片接合結構的製造方法，其中該凸塊包含一第一凸塊部及一第二凸塊部，且該第一凸塊部及該第二凸塊部彼此連接且具有不同的活性，其中形成該絕緣層的步驟包含氧化該凸塊，使該絕緣層僅形成於該第一凸塊部及該第二凸塊部中具有較高活性者的表面。
  9. 如申請專利範圍第8項所述的晶片接合結構的製造方法，其中該第一凸塊部具有比該第二凸塊部高的活性，其中設置該導電層的步驟包含使該第二凸塊部藉由該些導電粒子與該導電膜層相互電性連接的方式來設置該導電層。
  10. 如申請專利範圍第8項所述的晶片接合結構的製造方法，其中該第二凸塊部包含黃金，且該第一凸塊部包含銅。
TW099112291A 2010-04-20 2010-04-20 晶片結構及其晶片接合結構與製造方法 TWI423409B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW099112291A TWI423409B (zh) 2010-04-20 2010-04-20 晶片結構及其晶片接合結構與製造方法
US13/089,449 US20110254152A1 (en) 2010-04-20 2011-04-19 Chip structure, chip bonding structure using the same, and manufacturing method thereof
US13/862,383 US20130249086A1 (en) 2010-04-20 2013-04-13 Chip structure, chip bonding structure using the same, and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW099112291A TWI423409B (zh) 2010-04-20 2010-04-20 晶片結構及其晶片接合結構與製造方法

Publications (2)

Publication Number Publication Date
TW201138035A TW201138035A (en) 2011-11-01
TWI423409B true TWI423409B (zh) 2014-01-11

Family

ID=44787636

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099112291A TWI423409B (zh) 2010-04-20 2010-04-20 晶片結構及其晶片接合結構與製造方法

Country Status (2)

Country Link
US (2) US20110254152A1 (zh)
TW (1) TWI423409B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5920454B2 (ja) * 2012-03-15 2016-05-18 富士電機株式会社 半導体装置およびその製造方法
ITUB20155111A1 (it) * 2015-11-04 2017-05-04 St Microelectronics Srl Dispositivo a semiconduttore e relativo procedimento
CN105655298A (zh) * 2016-01-05 2016-06-08 深圳市华星光电技术有限公司 一种tft液晶显示模组及其封装结构和封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW544875B (en) * 2000-05-01 2003-08-01 Seiko Epson Corporatoin Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic machine
CN1823410A (zh) * 2003-07-16 2006-08-23 皇家飞利浦电子股份有限公司 具有侧壁绝缘层的金属凸起和制造具有该金属凸起的芯片的方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI297205B (en) * 2006-03-01 2008-05-21 Chipmos Technologies Inc Semiconductor element and manufaturing process thereof
KR20090059504A (ko) * 2007-12-06 2009-06-11 삼성전자주식회사 반도체 장치 및 그 제조방법들

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW544875B (en) * 2000-05-01 2003-08-01 Seiko Epson Corporatoin Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic machine
CN1823410A (zh) * 2003-07-16 2006-08-23 皇家飞利浦电子股份有限公司 具有侧壁绝缘层的金属凸起和制造具有该金属凸起的芯片的方法

Also Published As

Publication number Publication date
US20110254152A1 (en) 2011-10-20
TW201138035A (en) 2011-11-01
US20130249086A1 (en) 2013-09-26

Similar Documents

Publication Publication Date Title
TWI382461B (zh) Semiconductor device and manufacturing method thereof
KR101134168B1 (ko) 반도체 칩 및 그 제조 방법과, 그를 이용한 표시 패널 및그 제조 방법
US9224622B2 (en) Semiconductor device, method of manufacturing the device, and liquid crystal display
JP2004095577A (ja) 半導体装置およびその製造方法
TWI539500B (zh) 半導體封裝
JP2008078686A (ja) 半導体装置
TWI423409B (zh) 晶片結構及其晶片接合結構與製造方法
JP4651367B2 (ja) 半導体装置および半導体装置の製造方法
JP2008135486A (ja) 半導体装置及び半導体パッケージ
JP2007123407A (ja) 半導体装置の製造方法
US8426303B2 (en) Manufacturing method of semiconductor device, and mounting structure thereof
CN102237329B (zh) 芯片结构及其芯片接合结构与制造方法
JP2003197850A (ja) 半導体装置及びその製造方法
JP2000208178A (ja) 半導体応用装置及びその製造方法
JP5466280B2 (ja) 半導体装置
JP5759029B2 (ja) 半導体装置
JP2005056985A (ja) 半導体装置の製造方法、半導体装置および電子機器
JP4585564B2 (ja) 半導体装置
JP3657596B2 (ja) 半導体集積回路の作製方法
JP4387258B2 (ja) 半導体集積回路およびその製造方法
JP3970712B2 (ja) 半導体装置の製造方法
JP5259674B2 (ja) 半導体装置
JP2005128303A (ja) デバイス、半導体デバイスの製造方法及び液晶表示素子の製造方法
JP2003318221A (ja) 半導体装置の製造方法
JP2009049188A (ja) 半導体装置及びその製造方法並びに電子デバイス

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees