WO2013136896A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2013136896A1
WO2013136896A1 PCT/JP2013/053391 JP2013053391W WO2013136896A1 WO 2013136896 A1 WO2013136896 A1 WO 2013136896A1 JP 2013053391 W JP2013053391 W JP 2013053391W WO 2013136896 A1 WO2013136896 A1 WO 2013136896A1
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Prior art keywords
semiconductor device
conductive
connection body
shape
conductive post
Prior art date
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PCT/JP2013/053391
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English (en)
French (fr)
Inventor
典弘 梨子田
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富士電機株式会社
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Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP2014504744A priority Critical patent/JP5920454B2/ja
Priority to DE112013001425.4T priority patent/DE112013001425T5/de
Priority to CN201380012403.1A priority patent/CN104205328B/zh
Publication of WO2013136896A1 publication Critical patent/WO2013136896A1/ja
Priority to US14/470,076 priority patent/US9129840B2/en

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    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the present invention relates to a semiconductor device having a semiconductor chip and a conductive post, and a manufacturing method thereof, and more particularly, to a semiconductor device in which a conductive post is bonded by metal particle bonding using metal nanoparticles and a manufacturing method thereof.
  • FIG. 6A and 6B are configuration diagrams of a conventional semiconductor device described in Patent Document 1.
  • FIG. 6A is a cross-sectional view of the main part of the whole
  • FIG. 6B is an enlarged view of part B of FIG. is there.
  • a semiconductor power module which is a conventional semiconductor device
  • a semiconductor chip 106 is bonded to a DCB (Direct Copper Bonding) substrate 104, which is an insulating substrate with a conductive pattern, by a bonding material 105 such as solder, and the electric wiring on the surface of the semiconductor chip 106 is conductive.
  • the printed circuit board 109 having the post 108 is bonded with a bonding material 107 such as solder.
  • the semiconductor chip 106 and the DCB substrate 104 are sealed with a sealing resin 111 to form a semiconductor power module.
  • the DCB substrate 104 includes a heat sink 101, an insulating substrate 102, and a circuit pattern 103.
  • FIG. 7 is a cross-sectional view of a main part of another conventional semiconductor device described in Patent Document 2.
  • a semiconductor power module that is another conventional semiconductor device is a resin-encapsulated semiconductor power module similar to that shown in FIG.
  • This Patent Document 2 describes a support plate 206 corresponding to the printed circuit board 109 of FIG. 6 and a conductive post 205 connected thereto including a manufacturing method.
  • 201 is a heat sink
  • 202 is a conductive material
  • 203 is a semiconductor chip
  • 204 is a conductive material
  • 207 is a connection substrate
  • 208 is an external lead-out terminal.
  • tip part or the whole of the electrically conductive post which is a some pin is formed in a hollow pipe shape, and the joining area of a solder junction part is formed by forming a solder fillet in the outer surface and inner surface of an electrically conductive post. It is described that the bonding strength can be improved. Further, it is described that solder failure can be prevented by mounting solder paste or solder in advance on the tip of a hollow pipe-like conductive post.
  • the surface area of the tip of the conductive post is increased and the solder joint area is increased, thereby preventing the reliability of the solder joint from being lowered. It is described that can be.
  • the semiconductor power module which is the semiconductor device of Patent Document 1
  • the semiconductor chip 106 and the DCB substrate 104 are joined, and the chip surface electrodes are collectively connected by the conductive posts 108 instead of the aluminum wires to form wiring.
  • the current paths of the DCB substrate 104, the semiconductor chip 106, and the printed circuit board 109 are formed.
  • solder is used for the bonding material 107
  • the solder is disposed at the bonding portion of the chip front and back electrodes, heated, and then cooled to complete the bonding.
  • the semiconductor power module operates at a higher temperature than before to take advantage of its features. Needed. In the operating temperature range of 200 ° C. or higher, it is difficult to use solder from the viewpoint of reliability.
  • WBG Wide Band Gap
  • SiC (silicon carbide) devices such as SiC-MOSFET (MOS field effect transistor) and SiC-SBD (Schottky barrier diode) have a small chip size (for example, a size of about 3 mm ⁇ 3 mm). .
  • the gate pad of the SiC-MOSFET is extremely small, and its size is, for example, about 200 ⁇ m ⁇ 200 ⁇ m. It is difficult to fix the conductive post to such a small gate pad with high accuracy.
  • An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above-described problems and can firmly bond a conductive post and a semiconductor chip as a member to be bonded or an insulating substrate with a conductive pattern with metal nanoparticles. It is to provide.
  • a recess is formed on a bottom surface of a conductive connection body fixed to a material to be bonded.
  • the metal nanoparticle is used for bonding to the material to be bonded.
  • the conductive connection body may be a conductive post fixed to a printed circuit board or an external lead-out terminal.
  • the shape of the tip of the conductive post may be any one selected from a taper shape, a step shape, and a shape in which the step shape and the taper shape are combined.
  • tip of the said conductive post is good in it being the shape curved spherically.
  • the material to be bonded may be a conductive pattern of a surface electrode of a semiconductor chip or an insulating substrate with a conductive pattern to which the semiconductor chip is fixed.
  • the depth of the concave portion on the bottom surface of the tip of the conductive connecting body is in the range of 10 ⁇ m to 200 ⁇ m.
  • another aspect of the present invention includes at least a conductive connector having a recess formed at a tip and a material to be bonded, and the conductive connector and the material to be bonded are provided in the recess.
  • a semiconductor device that is closely packed and bonded by sintered metal particle sintered portions is preferable.
  • the conductive connection body is a rod-shaped conductive post in which the concave portion is formed at one end, and the bonded material is a surface electrode of a semiconductor chip.
  • the conductive connection body is a rod-shaped external lead-out terminal in which the concave portion is formed at one end, and the bonded material is a conductive pattern of an insulating substrate with a conductive pattern.
  • an application step of applying a paste containing metal nanoparticles on a material to be joined and a conductive connector having a recess at the tip are prepared, so that the recess is positioned on the paste.
  • a method for manufacturing a semiconductor device comprising a sintering step of bonding between a bonding material and the recess.
  • the heating temperature in the sintering step is preferably in the range of 150 ° C. to 300 ° C.
  • the pressure is preferably in the range of 10 MPa to 50 MPa.
  • a pre-baking step of heating and evaporating the solvent contained in the paste is further provided before the sintering step.
  • the metal nanoparticle is filled in the concave portion formed at the tip of the conductive connection body, and the metal particle is bonded between the conductive connection body and the material to be bonded using the metal nanoparticle, thereby strengthening both of them. Can be joined.
  • FIG. 1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1A is a cross-sectional view of the entire main part
  • FIG. 1B is an enlarged view of a portion A in FIG. It is a planar shape figure of the bottom face of the front-end
  • FIG. 2 shows a process of bonding the conductive post 8 and the upper surface electrode 6a of the semiconductor chip 6, and (a) to (c) are principal part process cross-sectional views shown in the order of processes.
  • FIG. 3 is a cross-sectional view of the main part showing the shape of the concave portion of the bottom surface 12 at the tip of the modified example of the conductive post 8 of FIG.
  • FIG. 4A and 4B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, in which FIG. 4A is a cross-sectional view of the main part of the conductive post 21, and FIG. 4B is a plan view of the bottom surface 23 at the tip of the conductive post 21. is there.
  • FIGS. 5A and 5B are diagrams showing the shape of the tip portion of a modified example of the conductive post 21.
  • FIG. 5A is a view in which the tip is narrowed in a staircase shape
  • FIG. 5B is a combination of the staircase shape and the taper shape.
  • FIG. 5A is a view in which the tip is narrowed in a staircase shape
  • FIG. 5B is a combination of the staircase shape and the taper shape.
  • FIG. 6A and 6B are configuration diagrams of a conventional semiconductor device described in Patent Document 1, in which FIG. 6A is an overall cross-sectional view of the main part, and FIG. 6B is an enlarged view of part B of FIG.
  • FIG. 7 is a cross-sectional view of a main part of another conventional semiconductor device described in Patent Document 2.
  • FIG. 8 is a model diagram illustrating the mechanism of metal particle bonding, and (a) to (c) are diagrams sequentially illustrating steps until metal particle bonding is performed.
  • FIG. 9 is a cross-sectional view of the main part when the bottom surface 402 a at the tip of the conductive post 402 is bonded to the upper surface electrode 401 a of the semiconductor chip 401 using the metal nanoparticles 404.
  • FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1 (a) is a cross-sectional view of the entire main part, and FIG. 1 (b) is an enlarged view of part A of FIG.
  • FIG. 4C is a plan view of the bottom surface of the tip of the conductive post in FIG. FIG. 1 corresponds to the semiconductor device of FIG.
  • a DCB substrate 4 which is an insulating substrate with a conductive pattern is composed of a heat sink 1, an insulating substrate 2, and a circuit pattern 3.
  • a semiconductor chip 6 is fixed on the circuit pattern 3 of the DCB substrate 4 via a bonding material 5.
  • a conductive post 8 is fixed on the upper surface electrode 6 a of the semiconductor chip 6 through a bonding layer 7.
  • the conductive post 8 is fixed to the printed board 9.
  • External lead-out terminals 10 are fixed to the circuit pattern 3 and the printed circuit board 9.
  • the bottom surface of the heat sink 1 and the external lead-out terminal 10 are exposed and the whole is sealed with a sealing resin 11.
  • At least the bonding layer 7 of the bonding material 5 and the bonding layer 7 uses metal nanoparticles.
  • a recess is formed in the bottom surface 12 at the tip of the conductive post 8.
  • a metal particle sintered portion 7a between the upper surface electrode 6a of the semiconductor chip 6 and the bottom surface of the tip of the conductive post 8, there is a metal particle sintered portion 7a, and there is a metal particle unsintered portion 7b around it.
  • the shape of the concave portion of the bottom surface 12 is configured by a smooth curved surface having a bow shape (spherical shape), a ball shape, or a dome shape.
  • the planar shape of the bottom surface 12 at the tip of the conductive post 8 is circular in order to apply pressure uniformly.
  • the outer peripheral portion 12a of the bottom surface 12 is chamfered to avoid stress concentration and has a smooth curved surface.
  • the cross-sectional shape of the conductive post 8 is not limited to a circle, and may be a polygon such as a quadrangle or a hexagon.
  • the conductive post 8 and the upper surface electrode 6a of the semiconductor chip 6 that is a member to be joined are formed of a metal particle sintered portion 7a formed by sintering metal nanoparticles (for example, silver nanoparticles or copper nanoparticles). Bonding is performed by the bonding layer 7.
  • the bonding layer 7 is obtained by pressing and sintering metal nanoparticles while heating, and this bonding method is called metal particle bonding.
  • the member to be joined is a circuit pattern (not shown) of the circuit pattern 3 of the DCB substrate 4 or the printed board 9, and the circuit pattern 3 and the external lead terminal 10 are joined, or the circuit pattern of the printed board 9 and the external lead terminal 10 are not shown.
  • This bonding can also be performed using metal nanoparticles.
  • the bottom surface of the tip of the external lead-out terminal 10 is preferably concave.
  • FIG. 2 shows a process of bonding the conductive post 8 and the upper surface electrode 6a of the semiconductor chip 6, and FIGS. 2A to 2C are cross-sectional views of essential parts shown in the order of the processes.
  • the metal nanoparticle paste 13 in which metal nanoparticles are dispersed and mixed is applied to the upper surface electrode 6a of the semiconductor chip 6 by, for example, a screen printing method ((a) in the figure).
  • the metal nanoparticles are made of at least one metal selected from copper, silver, platinum, or the like, and the particle size thereof is 1 nm to several hundred nm. You may mix and use the metal nanoparticle of a different material.
  • the metal nanoparticle paste 13 includes, for example, metal nanoparticles, an organic dispersion added so that metal fine particles do not condense during storage or during the manufacturing process, and an organic dispersion that reacts with the organic dispersion during bonding.
  • the dispersion auxiliary substance that removes water is mixed with an organic binder (solvent) to form a paste.
  • the thickness of the coated metal nanoparticle paste 13 is preferably 100 ⁇ m to 500 ⁇ m.
  • the upper surface electrode 6a is subjected to a plating process such as copper, gold, silver, or nickel on the surface.
  • a plating process such as copper, gold, silver, or nickel on the surface.
  • the conductive post 8 having a concave bottom surface 12 is placed on the applied metal nanoparticle paste 13 so that the tip thereof is positioned.
  • the conductive post 8 is formed by molding copper or a copper alloy, or by plating the surface of these members with gold, silver, nickel or the like.
  • the paste 13 is heated as a pre-bake to evaporate the solvent and form an agglomerated metal nanoparticle layer 13a ((b) in the figure). Furthermore, by applying pressure to the metal nanoparticle layer 13a through the recesses of the conductive posts 8 and heating the metal nanoparticles, the metal nanoparticles are sintered and the metal particle sintered portion 7a is formed as the strong bonding layer 7 (see FIG. (C)).
  • the concave portion of the bottom surface 12 at the tip of the conductive post 8 is spherically curved, and its depth T is in the range of 10 ⁇ m to 200 ⁇ m. Moreover, about 100 micrometers is preferable.
  • the depth T is less than 10 ⁇ m, the amount of metal nanoparticles to be pushed out increases, and the strong bonding layer 7 is not formed.
  • the thickness exceeds 200 ⁇ m, the metal nanoparticles do not sufficiently enter the concave portions, and the transmission of the applied pressure to the metal nanoparticles is not performed well. As a result, the strong bonding layer 7 is not formed.
  • the heating temperature at the time of the pre-baking varies depending on the solvent contained in the paste 13, but is preferably in the range of 100 ° C to 150 ° C, for example.
  • the temperature at which the metal nanoparticles are sintered is in the range of 150 ° C. to 300 ° C., preferably about 200 ° C. This is because if the temperature during sintering is less than 150 ° C., the temperature is too low and the metal nanoparticles do not become a bulk (sintered layer).
  • the temperature at the time of sintering exceeds 300 ° C., the evaporation of the solvent is too early and the metal nanoparticles are quickly aggregated to join the conductive post 8 and the upper surface electrode 6a of the semiconductor chip 6 which is the material to be joined. This is because the bonding layer 7 is not formed.
  • the pressure F applied to the metal nanoparticle layer 13a is in the range of 10 MPa to 50 MPa, preferably about 30 MPa. At 10 MPa, the applied pressure F is too low to form a sintered layer. On the other hand, if the pressure exceeds 50 MPa, the applied pressure is too high and defects such as cracks are introduced into the material to be joined by the stress at the end of the conductive post 8.
  • the atmosphere at the time of prebaking has preferable nitrogen atmosphere.
  • the atmosphere during sintering is preferably a reduced pressure atmosphere.
  • the metal nanoparticle layer 13a is formed so as to be densely filled in the concave portion formed on the bottom surface 12 at the tip of the conductive post 8, so that the metal nanoparticle is given from the conductive post 8 to the metal nanoparticle.
  • the applied pressure F is applied so as to converge in the direction of the central axis of the conductive post 8 in the direction of the arrow f shown in the drawing. Therefore, the metal nanoparticles are less likely to flow outward from the bottom surface 12 of the conductive post 8. Moreover, by pressurizing the metal nanoparticle layer 13a by the concave portion, the pressurizing force F necessary for sintering is effectively transmitted to the metal nanoparticles without being dispersed. As a result, the sintering proceeds reliably, and the metal particle sintered portion 7 a can be formed as the strong bonding layer 7.
  • the metal nanoparticle layer 13a to which the pressing force F is not applied becomes the metal particle unsintered portion 7b and does not participate in the joining. Therefore, a fillet is not formed unlike solder bonding.
  • the sintering itself of the metal particle sintered portion 7 a is strong, so that the conductive post 8 and the upper surface electrode 6 a are fixed through the strong bonding layer 7.
  • the planar shape of the bottom surface of the conductive post 8 is made circular so that the applied pressure F is uniformly transmitted to the metal nanoparticles. Further, since the outer peripheral portion 12a of the bottom surface 12 of the conductive post 8 is chamfered and smooth, stress concentration at this location is prevented. This can prevent not only stress concentration at the time of bonding but also stress concentration at the time of element operation after bonding.
  • the above joining method can also be applied to joining between the external lead-out terminal 10 and the circuit pattern 3 by using the external lead-out terminal 10 having a recess formed on the bottom surface of the tip.
  • the external lead-out terminal 10 and the circuit pattern 3 are made of, for example, copper or a copper alloy, and the base material may be plated with nickel or the like.
  • FIG. 3 is a cross-sectional view of the main part showing the shape of the concave portion different from the shape of the concave portion of the bottom surface 12 at the tip of the modified example of the conductive post 8 of FIG. 1, and FIG.
  • the figure in the case of being formed with four planes, (b) is a figure in the case where the shape of the recess is formed with many planes.
  • the recess in FIG. 3A is a pyramid shape
  • the recess in FIG. 3B is a combination of two different pyramid shapes.
  • FIG. 4A is a sectional view of the main part of the conductive post 21, and FIG. FIG.
  • the main part sectional view of the whole semiconductor device of the second embodiment is the same as the whole main part sectional view of the semiconductor device of the first example (FIG. 1A) except for the differences described below. Therefore, the overlapping description is omitted below.
  • the difference between the conductive post 21 of the semiconductor device of this embodiment and the conductive post 8 shown in FIGS. 1B and 1C is the shape of the tip 22 of the conductive post 21.
  • the conductive post 21 has a tapered shape in which the diameter of the distal end portion 22 decreases toward the bottom surface 23 where the concave portion is formed.
  • the conductive post 21 has a substantially cylindrical outer shape and the bottom surface 23 of the conductive post 21 can be made smaller than the conductive post 8 having the same diameter up to the tip.
  • the diameter of the end portion of the distal end portion 22 is, for example, about 100 ⁇ m.
  • the conductive post 21 can be bonded to the upper surface electrode 6a (particularly, for example, a gate pad) of a small semiconductor chip 6 such as a WBG semiconductor device with high positional accuracy.
  • a metal particle sintered portion is formed as a strong bonding layer 7 in the recess.
  • the electrode 6a can be reliably joined.
  • FIGS. 5A and 5B are diagrams showing the shape of the tip portion of a modified example of the conductive post 21.
  • FIG. 5A is a view of the tip portion 24 that is thin in a staircase shape
  • FIG. 5B is a step shape and a taper. It is the figure of the front-end
  • the planar shape of the bottom surface 23 at the tip of the conductive post 21 is the same as that in FIG. In either case, the cross-sectional shape of the shaft of the conductive post 21 is circular, but it may be a polygon such as a quadrangle or a hexagon. (Reference example) In the conventional semiconductor device shown in FIG.
  • metal nanoparticles such as Ag (silver) nanoparticles are used as the bonding materials 105 and 107 to bond the semiconductor chip 106 to the DCB substrate 104 or the conductive post 108 (referred to as metal particle bonding). ) Will be described.
  • the bonding materials 105 and 107 are in the form of a paste, and there is a process of pre-baking after applying to the bonded portion and heating to remove the solvent. In this state, the metal nanoparticles remain solid particles. Thereafter, in order to obtain sufficient bonding strength, bonding is performed by pressurizing and sintering the metal nanoparticles as the bonding member while heating.
  • FIG. 8 is a model diagram illustrating the mechanism of metal particle bonding
  • FIGS. 8A to 8C are diagrams sequentially illustrating steps until metal particle bonding is performed.
  • metal nanoparticles 302 are dispersed in a solvent 301 (active solvent) and applied as a paste 303 on a member 304 to be joined (for example, an upper electrode of a semiconductor chip) (FIG. 1A).
  • the solvent 301 is evaporated by heating, and the metal nanoparticle layer 305 (the layer in which the metal nanoparticles 302 are aggregated into nanoporous) is left on the member 304 to be joined.
  • a pressure G is applied to the metal nanoparticle layer 305 at the bottom surface 306a at the tip of the conductive post 306 in a state where the temperature is higher than that of pre-baking ((b) in the figure).
  • the metal nanoparticles 302 that come into contact with are sintered.
  • a strong bonding layer 307 is formed between the member to be bonded 304 and the conductive post 306 ((c) in the figure).
  • the pressed metal nanoparticles 302 form the bonding layer 307, but the non-pressurized metal nanoparticles 302 pushed out of the conductive posts 306 do not form the bonding layer 307. Therefore, a fillet such as solder joint is not formed.
  • FIG. 9 is a cross-sectional view of the main part when the bottom surface 402 a at the tip of the conductive post 402 is bonded to the upper surface electrode 401 a of the semiconductor chip 401 using the metal nanoparticles 404.
  • the metal nanoparticles 404 contacting the flat bottom surface 402a of the conductive post 402 are pushed out of the conductive post 402, and the thickness under the bottom surface 402a of the conductive post 402 is several ⁇ m. And extremely thin. Further, the extruded metal nanoparticle layer 403 is rolled up to become an unsintered layer 403a.
  • the thickness P of the bonding layer 405 (the layer in which the metal nanoparticle layer 403 is sintered) under the conductive post 402 is as thin as several ⁇ m
  • the roughness is the same as the roughness of the bottom surface 402a and the top electrode 401a of the conductive post 402.
  • the applied pressure H is not effectively transmitted to the metal nanoparticle layer 403. Therefore, the strong bonding layer 405 cannot be obtained.
  • FIG. 9 shows the case where the bottom surface 402a at the tip of the conductive post 402 is flat and further tapered, the same applies to a straight conductive post having a flat bottom surface, and it becomes difficult to form a strong bonding layer. .
  • the concave portions are formed on the bottom surfaces 12 and 23 of the conductive posts 8 and 21 fixed to the semiconductor chip 6, and the concave portions are filled closely.
  • a strong bonding layer 7 can be formed as metal particle bonding.
  • connection reliability can be improved against thermal stress generated at the joint between the semiconductor chip and the conductive post during operation.
  • the application of metal particle bonding realizes high-temperature operation of the semiconductor element as compared with solder bonding, and can be applied not only to silicon devices but also to WBG devices.
  • the present invention is also effective when the material to be bonded is not a semiconductor chip but an insulating substrate with a conductive pattern (DCB substrate).

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Abstract

　導電ポスト８と被接合部材である半導体チップ６や導電パターン付絶縁基板４を金属ナノ粒子を用いて金属粒子接合する場合に、導電ポスト８の先端の底面１２を凹状にすることで、強固な接合層を得ることができる。

Description

半導体装置およびその製造方法
　この発明は、半導体チップを搭載し導電ポストを有する半導体装置およびその製造方法に関し、特に、導電ポストの接合を金属ナノ粒子を用いた金属粒子接合で行う半導体装置およびその製造方法に関する。
　図６は、特許文献１に記載の従来の半導体装置の構成図であり、同図（ａ）は全体の要部断面図、同図（ｂ）は同図（ａ）のＢ部拡大図である。従来の半導体装置である半導体パワーモジュールは、半導体チップ１０６を導電パターン付絶縁基板であるＤＣＢ（Ｄｉｒｅｃｔ　Ｃｏｐｐｅｒ　Ｂｏｎｄｉｎｇ）基板１０４に半田等の接合材１０５により接合し、半導体チップ１０６表面の電気配線は導電ポスト１０８を有するプリント基板１０９に半田等の接合材１０７で接合する構造をしている。この構造では上記半導体チップ１０６およびＤＣＢ基板１０４を封止樹脂１１１により封止することで半導体パワーモジュールを形成する。
　前記のＤＣＢ基板１０４は放熱板１０１、絶縁基板１０２および回路パターン１０３で構成される。
　図７は、特許文献２に記載の従来の別の半導体装置の要部断面図である。従来の別の半導体装置である半導体パワーモジュールは、図６と同様の樹脂封止型半導体パワーモジュールである。この特許文献２では、図６のプリント基板１０９にあたる支持板２０６とそれに接続されている導電ポスト２０５に関して、製造方法も含め記述されている。尚、図中の符号の２０１は放熱板、２０２は導電性材料、２０３は半導体チップ、２０４は導電性材料、２０７は接続基板および２０８は外部導出端子である。
　また、特許文献３では、複数のピンである導電ポストの少なくとも先端部あるいは全体を中空パイプ状に形成し、半田フィレットを導電ポストの外面と内面に形成することにより、半田接合部の接合面積が増大され、接合強度を向上することができることが記載されている。また、中空パイプ状の導電ポストの先端部に予めソルダペーストあるいは半田を付けて実装することにより、半田不良を防止することができることが記載されている。また、導電ポストの先端に球状あるいは半球状の球部を形成することにより、導電ポストの先端部の表面積が大きくなって半田接合面積が大きくなり、半田接合部の信頼性の低下を防止することができることが記載されている。
特開２００９－６４８５２号公報 特開２０１１－１１４０４０号公報 特開平７－１０６４９１号公報
　特許文献１の半導体装置である半導体パワーモジュールでは、半導体チップ１０６とＤＣＢ基板１０４を接合するとともに、アルミワイヤに代わり導電ポスト１０８によりチップ表面電極を一括接続し、配線を形成する。これにより、ＤＣＢ基板１０４、半導体チップ１０６、プリント基板１０９の電流経路が形成される。接合材１０７に半田を使用する場合、チップ表裏電極の接合部分に半田を配置し、加熱した後、冷却することで接合が完了する。
　しかしながら、ＳｉＣ（炭化珪素）デバイスやＧａＮ（窒化ガリウム）等のＷＢＧ（ワイドバンドギャップ；Ｗｉｄｅ　Ｂａｎｄ　Ｇａｐ）半導体デバイスの搭載を考慮した場合、その特長を生かすために半導体パワーモジュールは従来より高温動作が必要とされる。２００℃以上の動作温度範囲になると、信頼性の観点から半田の使用は困難である。
　また、ＳｉＣ－ＭＯＳＦＥＴ（ＭＯＳ型電界効果トランジスタ）やＳｉＣ－ＳＢＤ（ショットキーバリアダイオード；Ｓｃｈｏｔｔｋｙ　ｂａｒｒｉｅｒ　ｄｉｏｄｅ）などのＳｉＣ（炭化珪素）デバイスはチップサイズが小さい（例えば、大きさが３ｍｍ×３ｍｍ程度）。そのため、ＳｉＣ－ＭＯＳＦＥＴのゲートパッドは極めて小さく、その大きさは、例えば、２００μｍ×２００μｍ程度である。このような小さなゲートパッドに導電ポストを精度よく固着することは困難である。
　特許文献１～３に記載された半導体装置の導電ポストとその接合方法によってはこれらの課題を解決することは困難である。
　この発明の目的は、前記の課題を解決して、導電ポストと被接合部材である半導体チップや導電パターン付絶縁基板を金属ナノ粒子でそれぞれ強固に接合することができる半導体装置およびその製造方法を提供することにある。
　前記の目的を達成するために、本発明の一態様は、半導体チップと導電接続体を有する半導体装置において、被接合材に固着される導電接続体の先端の底面に凹部を形成し、該凹部において金属ナノ粒子を用いて被接合材と接合する構成とする。
　また、前記導電接続体が、プリント基板に固着される導電ポストまたは外部導出端子であるとよい。
　また、前記導電ポストの先端の形状が、テーパー状、階段状および階段状とテーパー状とを組み合わせた形状から選ばれるいずれかであるとよい。
　また、前記導電ポストの先端の底面の凹部の形状が、球状に湾曲した形状であるとよい。
　また、前記被接合材が、半導体チップの表面電極もしくは該半導体チップを固着した導電パターン付絶縁基板の導電パターンであるとよい。
　また、前記導電接続体の先端の底面を凹部の深さが、１０μｍ～２００μｍの範囲であるとよい。
　前記の目的を達成するために、本発明の別の態様は、先端に凹部が形成された導電接続体と、被接合材とを少なくとも備え、前記導電接続体および被接合材が、前記凹部に密に充填され、焼結された金属粒子焼結部により接合されている半導体装置が好ましい。
　また、前記導電接続体が、一端に前記凹部が形成された棒状の導電ポストであり、前記被接合材が、半導体チップの表面電極であるとよい。
　また、前記導電接続体が、一端に前記凹部が形成された棒状の外部導出端子であり、前記被接合材が、導電パターン付絶縁基板の導電パターンであるとよい。
　また、本発明の別の態様は、被接合材上に金属ナノ粒子入りのペーストを塗布する塗布工程と、先端に凹部を備える導電接続体を用意し、前記凹部が前記ペースト上に位置するように前記導電接続体を載置する載置工程と、前記金属ナノ粒子を加熱するとともに、前記導電接続体により前記金属ナノ粒子に圧力を加えることにより、前記金属ナノ粒子を焼結し、前記被接合材と前記凹部の間を接合する焼結工程とを含むことを特徴とする半導体装置の製造方法とする。
　また、前記焼結工程における加熱の温度は、１５０℃～３００℃の範囲であり、前記圧力は、１０ＭＰａ～５０ＭＰａの範囲であるとよい。
　また、前記焼結工程の前に、さらに、前記ペーストに含まれる溶剤を加熱し、蒸発させるプリベーク工程を有するとよい。
　この発明によると、導電接続体の先端に形成した凹部に金属ナノ粒子を充填し、この金属ナノ粒子を用いて導電接続体と被接合材の間を金属粒子接合することにより、両者を強固に接合することができる。
図１は、この発明の第１実施例である半導体装置の構成図であり、（ａ）は全体の要部断面図、（ｂ）は（ａ）のＡ部拡大図、（ｃ）は（ｂ）の導電ポストの先端の底面の平面形状図である。 図２は、導電ポスト８と半導体チップ６の上面電極６ａを接合する工程を示し、（ａ）～（ｃ）は工程順に示した要部工程断面図である。 図３は、図１の導電ポスト８の変形例の先端の底面１２の凹部の形状と別の凹部の形状を示している要部断面図であり、（ａ）は凹部の形状が４つの平面で形成された場合の図、（ｂ）は凹部の形状が多数の平面で形成された場合の図である。 図４は、この発明の第２実施例の半導体装置の構成図であり、（ａ）は導電ポスト２１の要部断面図、（ｂ）は導電ポスト２１の先端の底面２３の平面形状図である。 図５は、導電ポスト２１の変形例の先端部の形状を示す図であり、（ａ）は階段状に先端が細くなっている場合の図、（ｂ）は階段形状とテーパー形状を組み合わせた場合の図である。 図６は、特許文献１に記載の従来の半導体装置の構成図であり、（ａ）は全体の要部断面図、（ｂ）は（ａ）のＢ部拡大図である。 図７は、特許文献２に記載の従来の別の半導体装置の要部断面図である。 図８は、金属粒子接合のメカニズムを説明したモデル図であり、（ａ）～（ｃ）は金属粒子接合ができるまでの工程を順に示す図である。 図９は、半導体チップ４０１の上面電極４０１ａに導電ポスト４０２の先端の底面４０２ａを金属ナノ粒子４０４を用いて接合した場合の要部断面図である。
　実施の形態を以下の実施例で説明する。
＜実施例１＞
　図１は、この発明の第１実施例である半導体装置の構成図であり、同図（ａ）は全体の要部断面図、同図（ｂ）は同図（ａ）のＡ部拡大図、同図（ｃ）は同図（ｂ）の導電ポストの先端の底面の平面形状図である。この図１は、図６の半導体装置に相当する図である。
　同図（ａ）において、導電パターン付絶縁基板であるＤＣＢ基板４は放熱板１、絶縁基板２および回路パターン３で構成される。このＤＣＢ基板４の回路パターン３上に接合材５を介して半導体チップ６を固着する。この半導体チップ６の上面電極６ａ上に接合層７を介して導電ポスト８を固着する。この導電ポスト８はプリント基板９に固着する。回路パターン３とプリント基板９には外部導出端子１０が固着している。放熱板１の底面と外部導出端子１０を露出させて全体を封止樹脂１１で封止する。接合材５および接合層７ののうちの少なくとも接合層７は金属ナノ粒子を用いている。
　同図（ｂ）において、導電ポスト８の先端の底面１２には凹部が形成されている。半導体チップ６の上面電極６ａと導電ポスト８の先端の底面との間には金属粒子焼結部７ａがあり、その周りには金属粒子未焼結部７ｂがある。底面１２の凹部の形状は弓状（球状）、ボール状またはドーム状の滑らかな曲面で構成されている。
　同図（ｃ）において、導電ポスト８の先端の底面１２の平面形状は加圧を均一に行うために円形にしている。底面１２の外周部１２ａは応力集中を避けるために面取りされており、滑らかな曲面になっている。また、導電ポスト８の断面形状は円形に限ることはなく、四角形や六角形など多角形としても構わない。
　この導電ポスト８と被接合部材である半導体チップ６の上面電極６ａは、金属ナノ粒子（例えば、銀ナノ粒子や銅ナノ粒子など）の焼結により形成された金属粒子焼結部７ａからなる強固な接合層７によって接合される。この接合層７は金属ナノ粒子を加熱しながら加圧して焼結することで得られ、この接合法は金属粒子接合といわれるものである。
　尚、被接合部材をＤＣＢ基板４の回路パターン３やプリント基板９の図示しない回路パターンとし、この回路パターン３と外部導出端子１０の接合や、プリント基板９の図示しない回路パターンと外部導出端子１０の接合も、金属ナノ粒子を用いて行うことができる。これらの場合も外部導出端子１０の先端の底面を凹状にするとよい。
　図２は、導電ポスト８と半導体チップ６の上面電極６ａを接合する工程を示し、同図（ａ）～同図（ｃ）は工程順に示した要部工程断面図である。
　金属ナノ粒子が分散、混合された金属ナノ粒子ペースト１３を半導体チップ６の上面電極６ａに、例えばスクリーン印刷法により、塗布する（同図（ａ））。
　金属ナノ粒子は、銅、銀または白金等から選ばれる少なくとも一種の金属からなり、それらの粒径は１ｎｍ～数百ｎｍである。異なる材料の金属ナノ粒子を混合して用いてもよい。金属ナノ粒子ペースト１３は、例えば、金属ナノ粒子と、保存時や製造工程の途中で金属微粒子同士が凝縮しないように添加される有機分散材と、接合時に有機分散材と反応して有機分散材を除去する分散補助物質とが、有機バインダー（溶剤）と混合させてペースト状に構成されたものである。塗布した金属ナノ粒子ペースト１３の厚さは１００μｍ～５００μｍが好ましい。
　また、上面電極６ａには、表面に銅、金、銀、ニッケルなどのめっき処理を施しておくことが望ましい。
　次に、塗布した金属ナノ粒子ペースト１３の上に、底面１２が凹形状をしている導電ポスト８を、その先端が位置するように載置する。導電ポスト８は、銅もしくは銅合金を成型したもの、または、これらの部材の表面に金、銀、ニッケルなどのめっき処理を施したものである。
　その後、プリベークとしてペースト１３を加熱して溶剤を蒸発させ、凝集した金属ナノ粒子層１３ａを形成する（同図（ｂ））。さらに、金属ナノ粒子層１３ａに導電ポスト８の凹部により圧力を加え、加熱することにより、金属ナノ粒子が焼結され、強固な接合層７として金属粒子焼結部７ａが形成される（同図（ｃ））。
　前記の導電ポスト８の先端の底面１２の凹部は球状に湾曲しており、その深さＴは、１０μｍ～２００μｍの範囲である。また、好ましくは１００μｍ程度がよい。この深さＴが１０μｍ未満になると、金属ナノ粒子が押し出される量が多くなり、強固な接合層７が形成されない。一方、２００μｍ超になると凹部に十分に金属ナノ粒子が入り込まず、金属ナノ粒子への加圧力の伝達が良好に行なわれない。その結果、強固な接合層７が形成されなくなる。
　また、前記のプリベーク時の加熱温度は、ペースト１３に含まれる溶剤によって異なるが、例えば１００℃～１５０℃の範囲が好ましい。金属ナノ粒子を焼結する時の温度は１５０℃～３００℃の範囲であり、好ましくは２００℃程度がよい。これは、焼結する時の温度が１５０℃未満では温度が低過ぎて金属ナノ粒子がバルク（焼結層）にならないからである。また、焼結する時の温度が３００℃を超えると溶剤の蒸発が早すぎて金属ナノ粒子同士が素早く凝集し導電ポスト８や被接合材である半導体チップ６の上面電極６ａを接合する強固な接合層７が形成されないからである。
　また、金属ナノ粒子層１３ａに加える加圧力Ｆは、１０ＭＰａ～５０ＭＰａの範囲であり、好ましくは３０ＭＰａ程度がよい。これは、１０ＭＰａでは加圧力Ｆが低すぎて焼結層にならない。また、５０ＭＰａを超えると加圧力が高すぎて導電ポスト８の端部の応力で被接合材にクラックなどの欠陥が導入される。
　また、被接合材（特に銅の場合）の酸化を抑制するため、プリベーク時の雰囲気は窒素雰囲気が好ましい。金属ナノ粒子層１３ａと導電ポスト８の先端底面が接触する際に凹部に残存する空気を除くため、焼結時の雰囲気は減圧雰囲気が好ましい。
　図２（ｂ）に示すように、導電ポスト８先端の底面１２に形成された凹部に密に充填されように金属ナノ粒子層１３ａが形成されるため、導電ポスト８から金属ナノ粒子に与えられる加圧力Ｆは、図に示す矢印ｆの方向に下に向かって導電ポスト８の中心軸方向に収束するように与えられる。そのため、金属ナノ粒子は導電ポスト８の底面１２から外側に向かって流れることが少なくなる。また、凹部により金属ナノ粒子層１３ａを加圧することにより、焼結に必要な加圧力Ｆも分散しないで効果的に金属ナノ粒子に伝わる。その結果、確実に焼結が進み、強固な接合層７として、金属粒子焼結部７ａを形成することができる。
　図２（ｃ）に示すように、加圧力Ｆが加わらない金属ナノ粒子層１３ａは金属粒子未焼結部７ｂとなり、接合には関与しない。そのため、半田接合のようにフィレットは形成されない。しかし、金属粒子焼結部７ａの焼結自体が強固であり、そのため導電ポスト８と上面電極６ａは強固な接合層７を介して固着される。
　導電ポスト８底面の平面形状を円形にすることで、加圧力Ｆが均一に金属ナノ粒子に伝達される。また、導電ポスト８の底面１２の外周部１２ａが面取りされて滑らかなため、この箇所での応力集中が防止される。これは、接合時の応力集中ばかりでなく、接合後の素子動作時の応力集中を防止することもできる。
　上記の接合方法は、先端の底面に凹部を形成した外部導出端子１０を用いることにより、外部導出端子１０と回路パターン３の間の接合にも適用できる。外部導出端子１０および回路パターン３は、例えば銅や銅合金からなり、これらの母材にニッケル等のめっき処理を施してもよい。
　ＳｉＣデバイスのようなＷＢＧ半導体デバイスにおいては、小型化、高温動作が可能となり、金属粒子接合は最適な接合手段である。
　図３は、図１の導電ポスト８の変形例の先端の底面１２の凹部の形状とは別の凹部の形状を示している要部断面図であり、同図（ａ）は凹部の形状が４つの平面で形成された場合の図、同図（ｂ）は凹部の形状が多数の平面で形成された場合の図である。例えば、図３（ａ）の凹部はピラミッド形状であり、図３（ｂ）の凹部は２つの異なるピラミッド形状を組み合わせたものである。いずれの場合も底面１２が凹形状となっていることで、導電ポスト８から金属ナノ粒子層１３ａ中の金属ナノ粒子へ効果的に加圧力Ｆが伝達されて強固な接合層が得られる。
＜実施例２＞
　図４は、この発明の第２実施例の半導体装置の構成図であり、同図（ａ）は導電ポスト２１の要部断面図、同図（ｂ）は導電ポスト２１の先端の底面２３の平面形状図である。第２実施例の半導体装置の全体の要部断面図は、次に述べる違いを除いて、第１実施例の半導体装置の全体の要部断面図（図１（ａ））と同じである。したがって、以下では重複する説明を省略する。本実施例の半導体装置の導電ポスト２１の、図１（ｂ），（ｃ）に示した導電ポスト８との違いは、導電ポスト２１の先端部２２の形状である。この導電ポスト２１は、凹部が形成された底面２３に向かって先端部２２の径が小さくなるテーパー形状となっている。導電ポスト２１は、外形が略円柱で先端まで同一径の導電ポスト８と比較して、導電ポスト２１の底面２３を小さい面積にできる。先端部２２の端部の直径は、例えば１００μｍ程度である。導電ポスト２１は、ＷＢＧ半導体デバイス等の小さな半導体チップ６の上面電極６ａ（特に、例えば、ゲートパッドなど）へ位置精度よく接合できる。導電ポスト２１の先端の底面２３を図１の場合と同様に凹部を形成することで、凹部の中に強固な接合層７として、金属粒子焼結部を形成し、小さな面積の底面２３と上面電極６ａを確実に接合できる。
　図５は、導電ポスト２１の変形例の先端部の形状を示す図であり、同図（ａ）は階段状に細くなっている先端部２４の図、同図（ｂ）は階段形状とテーパー形状を組み合わせた先端部２５の図である。導電ポスト２１の先端の底面２３の平面形状は図４（ｂ）と同じである。いずれも、導電ポスト２１の軸の断面形状は円形であるが、四角形や六角形などの多角形であっても構わない。
（参考例）
　図６に示した従来の半導体装置において、接合材１０５、１０７としてＡｇ（銀）ナノ粒子などの金属ナノ粒子を用いて半導体チップ１０６とＤＣＢ基板１０４や導電ポスト１０８の接合（金属粒子接合と称す）を形成した例を説明する。
　この接合材１０５、１０７はペースト状であり、接合部分に塗布した後、加熱し溶剤等をとばす工程がある（プリベーク）。この状態では金属ナノ粒子は固体粒子のままである。その後、十分な接合強度を得るために、加熱しながら接合部材である金属ナノ粒子を加圧して焼結することで接合を行う。
　図８は、金属粒子接合のメカニズムを説明したモデル図であり、同図（ａ）～同図（ｃ）は金属粒子接合ができるまでの工程を順に示す図である。
　まず、溶剤３０１（活性溶媒）に金属ナノ粒子３０２を分散させてペースト３０３にして被接合部材３０４（例えば、半導体チップの上面電極など）上に塗布する（同図（ａ））。
　つぎに、加熱して溶剤３０１を蒸発させ、金属ナノ粒子層３０５（金属ナノ粒子３０２がナノポーラスに凝集した層）を接合する被接合部材３０４上に残留させる。プリベークよりも温度を上げた状態で導電ポスト３０６の先端の底面３０６ａでこの金属ナノ粒子層３０５に加圧力Ｇを加える（同図（ｂ））。加熱しながら加圧することにより、被接合部材３０４と導電ポスト３０６の間で金属ナノ粒子同士接触する金属ナノ粒子３０２、被接合部材３０４に接触する金属ナノ粒子３０２および導電ポスト３０６の先端の底面３０６ａに接触する金属ナノ粒子３０２を焼結する。この焼結によって被接合部材３０４と導電ポスト３０６の間には強固な接合層３０７が形成される（同図（ｃ））。
　この金属粒子接合においては加圧された金属ナノ粒子３０２が接合層３０７を形成するが、導電ポスト３０６の外側に押し出された加圧されない金属ナノ粒子３０２は接合層３０７を形成しない。そのため、半田接合のようなフィレットは形成されない。
　図９は、半導体チップ４０１の上面電極４０１ａに導電ポスト４０２の先端の底面４０２ａを金属ナノ粒子４０４を用いて接合した場合の要部断面図である。
　金属ナノ粒子層４０３に加わる加圧力Ｈで、導電ポスト４０２の平坦な底面４０２ａに接触する金属ナノ粒子４０４が導電ポスト４０２の外側へ押し出されて、導電ポスト４０２の底面４０２ａ下の厚みは数μｍと極めて薄くなる。また、押し出された金属ナノ粒子層４０３は巻き上がり未焼結層４０３ａとなる。
　このように導電ポスト４０２下の接合層４０５（金属ナノ粒子層４０３が焼結した層）の厚さＰが数μｍと薄くなると、導電ポスト４０２の底面４０２ａおよび上面電極４０１ａの粗さと同じ程度となり金属ナノ粒子層４０３に加圧力Ｈが効果的に伝達されなくなる。そのため、強固な接合層４０５が得られなくなる。
　図９では、導電ポスト４０２の先端の底面４０２ａが平坦でさらにテーパー状の場合を示したが、ストレートで底面が平坦な導電ポストの場合も同様であり、強固な接合層の形成は困難になる。
　この参考例に対し、実施例１および実施例２で説明した半導体装置においては、半導体チップ６に固着する導電ポスト８，２１の底面１２，２３に凹部を形成し、この凹部に密に充填した金属ナノ粒子を加熱しながら加圧し、焼結することにより、金属粒子接合として強固な接合層７を形成できる。これにより、ワイヤボンディングレス構造である導電ポスト接続型のパワー半導体モジュールにおいて、動作時における半導体チップと導電ポストの接合部に生じる熱応力に対し、接続信頼性を向上させることができる。また、金属粒子接合の適用により、半田接合と比較し、半導体素子の高温動作も実現され、シリコンデバイスばかりでなくＷＢＧデバイスへの適用ができる。
　また、本発明は被接合材を半導体チップではなく導電パターン付絶縁基板（ＤＣＢ基板）にした場合も有効である。
　　　１　　放熱板
　　　２　　絶縁基板
　　　３　　回路パターン
　　　４　　ＤＣＢ基板
　　　５　接合材
　　　６　　半導体チップ
　　　６ａ　上面電極
　　　７　接合層
　　　７ａ　金属粒子焼結部
　　　７ｂ　金属接合未焼結部
　　　８，２１　導電ポスト
　　　９　　プリント基板
　　１０　　外部導出端子
　　１１　　封止樹脂
　　１２、２３　導電ポストの底面
　　１２ａ、１３ａ　導電ポスト底面の外周部
１３　　金属ナノ粒子ペースト　１３ａ　金属ナノ粒子層　　２２、２４、２５　先端部

Claims (12)

  1. 　半導体チップと導電接続体を有する半導体装置において、被接合材に固着される導電接続体の先端の底面に凹部を形成し、該凹部において金属ナノ粒子を用いて被接合材と接合することを特徴とする半導体装置。
  2. 　前記導電接続体が、プリント基板に固着される導電ポストまたは外部導出端子であることを特徴とする請求項1に記載の半導体装置。
  3. 　前記導電ポストの先端の形状が、テーパー状、階段状および階段状とテーパー状とを組み合わせた形状から選ばれるいずれかであることを特徴とする請求項２に記載の半導体装置。
  4. 　前記導電ポストの先端の底面の凹部の形状が、球状に湾曲した形状であることを特徴とする請求項２に記載の半導体装置。
  5. 　前記被接合材が、半導体チップの表面電極もしくは該半導体チップを固着した導電パターン付絶縁基板の導電パターンであることを特徴とする請求項１に記載の半導体装置。
  6. 　前記導電接続体の先端の底面を凹部の深さが、１０μｍ～２００μｍの範囲であることを特徴とする請求項１に記載の半導体装置。
  7. 　先端に凹部が形成された導電接続体と、被接合材とを少なくとも備え、前記導電接続体および被接合材が、前記凹部に密に充填され、焼結された金属粒子焼結部により接合されていることを特徴とする半導体装置。
  8. 　前記導電接続体が、一端に前記凹部が形成された棒状の導電ポストであり、前記被接合材が、半導体チップの表面電極である、ことを特徴とする請求項７に記載の半導体装置。
  9. 　前記導電接続体が、一端に前記凹部が形成された棒状の外部導出端子であり、前記被接合材が、導電パターン付絶縁基板の導電パターンである、ことを特徴とする請求項７に記載の半導体装置。
  10. 　被接合材上に金属ナノ粒子入りのペーストを塗布する塗布工程と、
    　先端に凹部を備える導電接続体を用意し、前記凹部が前記ペースト上に位置するように前記導電接続体を載置する載置工程と、
    　前記金属ナノ粒子を加熱するとともに、前記導電接続体により前記金属ナノ粒子に圧力を加えることにより、前記金属ナノ粒子を焼結し、前記被接合材と前記凹部の間を接合する焼結工程と
    を含むことを特徴とする半導体装置の製造方法。
  11. 　前記焼結工程における加熱の温度は、１５０℃～３００℃の範囲であり、前記圧力は、１０ＭＰａ～５０ＭＰａの範囲であることを特徴とする請求項１０に記載の半導体装置の製造方法。
  12. 　前記焼結工程の前に、さらに、前記ペーストに含まれる溶剤を加熱し、蒸発させるプリベーク工程を有することを特徴とする請求項１０に記載の半導体装置の製造方法。
     
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