CN104205328B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN104205328B
CN104205328B CN201380012403.1A CN201380012403A CN104205328B CN 104205328 B CN104205328 B CN 104205328B CN 201380012403 A CN201380012403 A CN 201380012403A CN 104205328 B CN104205328 B CN 104205328B
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recess
semiconductor device
conductive pole
conduction connector
metal nanoparticle
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CN201380012403.1A
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CN104205328A (zh
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梨子田典弘
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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Abstract

在使用金属纳米粒子对导电柱(8)和被接合构件即半导体芯片(6)或带导电图案的绝缘基板(4)进行金属粒子接合的情况下，通过将导电柱(8)的前端的底面(12)形成为凹状，从而能获得牢固的接合层。

Description

半导体装置及其制造方法
技术领域
本发明涉及搭载半导体芯片且具有导电柱的半导体装置及其制造方法，尤其涉及以利用金属纳米粒子的金属粒子接合来进行导电柱的接合的半导体装置及其制造方法。
背景技术
图6是专利文献1所记载的现有的半导体装置的结构图，图6(a)是整体的主要部分剖视图，图6(b)是图6(a)的B部放大图。现有的半导体装置即半导体功率模块具有如下结构：利用焊料等接合材料105将半导体芯片106与作为带导电图案的绝缘基板的DCB(DirectCopper Bonding：直接铜接合)基板104相接合，半导体芯片106表面的电路布线利用焊料等接合材料107与具有导电柱108的印刷基板109相接合。在该结构中，通过利用密封树脂111对上述半导体芯片106以及DCB基板104进行密封，从而形成半导体功率模块。
所述DCB基板104由散热板101、绝缘基板102以及电路图案103构成。
图7是专利文献2所记载的现有的其它半导体装置的主要部分剖视图。作为现有的其它半导体装置的半导体功率模块是与图6相同的树脂密封型半导体功率模块。该专利文献中还记载了与图6的印刷基板109相接触的支承板206和与其相连接的导电柱205的制造方法。另外，图中的标号201是散热板、202是导电性材料、203是半导体芯片、204是导电性材料、207是连接基板，208是外部导出端子。
此外，专利文献3中具有如下记载：多个销即导电柱的至少前端部或者整体形成为中空管状，通过在导电柱的外表面和内表面形成焊角，来增大焊料接合部的接合面积，从而能提高接合强度。此外，记载有通过预先在中空管状的导电柱的前端部粘贴焊膏或者焊料来进行安装，能防止焊料不良。还记载有通过在导电柱的前端形成球状或者半球状的球部，导电柱的前端部的表面积变大，焊料接合面积变大，从而能防止焊料接合部的可靠性降低。
现有技术文献
专利文献
专利文献1：日本专利特开2009-64852号公报
专利文献2：日本专利特开2011-114040号公报
专利文献3：日本专利特开平7-106491号公报
发明内容
发明所要解决的技术问题
在作为专利文献1的半导体装置的半导体功率模块中，对半导体芯片106和DCB基板104进行接合，并且利用导电柱108来代替铝线对芯片表面电极进行统一连接，并形成布线。由此，形成DCB基板104、半导体芯片106、印刷布线板109的电路路径。在接合材料107使用焊料的情况下，在芯片表面及背面电极的接合部分配置焊料，加热后冷却来完成接合。
然而，在考虑搭载SiC(碳化硅)器件、GaN(氮化镓)等WBG(宽带隙：Wide Band Gap)半导体器件的情况下，为了运用其特长，需要使半导体功率模块在比以往更高的温度下工作。若工作温度范围变为200℃以上，则从可靠性的观点来看难以使用焊料。
此外，SiC-MOSFET(MOS型场效应晶体管)、SiC-SBD(肖特基势垒二极管；Schottkybarrier diode)等SiC(碳化硅)器件的芯片尺寸较小(例如大小为3mm×3mm左右)。因此，SiC-MOSFET的栅极垫极小，其大小为例如200μm×200μm左右。将导电柱高精度地固定于这样小的栅极垫上是较为困难的。
用专利文献1～3所记载的半导体装置的导电柱和其接合方法来解决这些问题是较为困难的。
本发明的目的在于解决上述问题，提供一种能利用金属纳米粒子将导电柱与被接合构件即半导体芯片或带导电图案的绝缘基板分别牢固地相接合的半导体装置及其制造方法。
解决技术问题的技术方案
为了达到上述目的，本发明的一个方式为如下结构：在具有半导体芯片和导电连接体的半导体装置中，在固定于被接合材料的导电连接体的前端的底面形成有凹部，在该凹部中使用金属纳米粒子来与被接合材料相接合。
所述导电连接体可以是固定于印刷基板的导电柱或者外部导出端子。
所述导电柱的前端的形状可以是从锥形状、阶梯状、以及阶梯状与锥形状组合而成的形状中任选的一种。
所述导电柱的前端的底面的凹部形状可以是弯曲成球状的形状。
所述被接合材料可以是半导体芯片的表面电极或者是固定了该半导体芯片的带导电图案的绝缘基板的导电图案。
所述导电连接体的前端的底面的凹部深度可以在10μm～200μm的范围内。
为了达到上述目的，本发明的其它方式中，优选该半导体装置至少包括：前端形成有凹部的导电连接体、以及被接合材料，所述导电连接体以及被接合材料通过密集地填充在所述凹部中的烧结后的金属粒子烧结部来进行接合。
所述导电连接体可以是一端形成有所述凹部的棒状的导电柱，所述被接合材料可以是半导体芯片的表面电极。
所述导电连接体可以是一端形成有所述凹部的棒状的外部导出端子，所述被接合材料可以是带导电图案的绝缘基板的导电图案。
本发明的其它方式为半导体装置的制造方法，其特征在于，包括如下工序：涂布工序，在该涂布工序中，将含有金属纳米粒子的糊料涂布在被接合材料上；放置工序，在该放置工序中，准备前端具备凹部的导电连接体，以所述凹部位于所述糊料上的方式放置所述导电连接体；以及烧结工序，在该烧结工序中，对所述金属纳米粒子进行加热，并且通过所述导电连接体对所述金属纳米粒子加压，从而对所述金属纳米粒子进行烧结，使所述被接合材料与所述凹部之间相接合。
所述烧结工序中的加热温度可以在150℃～300℃的范围内，所述压力可以在10MPa～50MPa的范围内。
在所述烧结工序之前还具有预烘干工序，在该预烘干工序中，对所述糊料所含有的溶剂进行加热，使其蒸发。
发明效果
根据本发明，通过在形成于导电连接体的前端的凹部中填充金属纳米粒子，并利用该金属纳米粒子对导电连接体和被接合材料之间进行金属粒子接合，从而能牢固地使两者相接合。
附图说明
图1是本发明的实施例1的半导体装置的结构图，图1(a)是整体的主要部分剖视图，图1(b)是图1(a)的A部放大图，图1(c)是图1(b)的导电柱的前端的底面的平面形状图。
图2表示导电柱8和半导体芯片6的上表面电极6a相接合的工序，图2(a)～图2(c)是以工序步骤表示的主要部分工序剖视图。
图3是表示图1的导电柱8的变形例的前端的底面12的不同凹部形状的主要部分剖视图，图3(a)是凹部形状由4个平面形成的情况的图，图3(b)是凹部形状由多个平面形成的情况的图。
图4是本发明的实施例2的半导体装置的结构图，图4(a)是导电柱21的主要部分剖视图，图4(b)是导电柱21的前端的底面23的平面形状图。
图5是表示导电柱21的变形例的前端部形状的图，图5(a)是前端呈阶梯状变细的情况的图，图5(b)是将阶梯形状与锥形形状组合后的情况的图。
图6是专利文献1所记载的现有的半导体装置的结构图，图6(a)是整体的主要部分剖视图，图6(b)是图6(a)的B部放大图。
图7是专利文献2所记载的现有的其它半导体装置的主要部分剖视图。
图8是对金属粒子接合的机理进行说明的模型图，图8(a)～图8(c)是依次表示到金属粒子接合完成为止的工序的图。
图9是利用金属纳米粒子404将导电柱402的前端的底面402a与半导体芯片401的上表面电极401a相接合时的主要部分剖视图。
具体实施方式
利用以下实施例来说明实施方式。
<实施例1>
图1是本发明的实施例1的半导体装置的结构图，图1(a)是整体的主要部分剖视图，图1(b)是图1(a)的A部放大图，图1(c)是图1(b)的导电柱的前端的底面的平面形状图。该图1是相当于图6的半导体装置的图。
图1(a)中，带导电图案的绝缘基板即DCB基板4由散热板1、绝缘基板2、以及电路图案3构成。经由接合材料5将半导体芯片6固定于该DCB基板4的电路图案3上。经由接合层7将导电柱8固定于该半导体芯片6的上表面电极6a上。该导电柱8固定于印刷基板9。外部导出端子10固定于电路图案3和印刷基板9。以密封树脂11对整体进行密封并使散热板1的底面和外部导出端子10露出。接合材料5以及接合层7中至少接合层7使用金属纳米粒子。
图1(b)中，在导电柱8的前端的底面12形成有凹部。在半导体芯片6的上表面电极6a和导电柱8的前端的底面之间具有金属粒子烧结部7a，其周围具有金属粒子未烧结部7b。底面12的凹部形状由弓状(球状)、球状或者圆顶状的光滑曲面构成。
图1(c)中，为了均匀地进行加压，导电柱8的前端的底面12的平面形状为圆形。为了避免应力集中，对底面12的外周部12a进行倒角，成为光滑的曲面。此外，导电柱8的截面形状不限于圆形，也可以是四边形、六边形等多边形。
该导电柱8和被接合构件即半导体芯片6的上表面电极6a利用牢固的接合层7相接合，该接合层7由通过金属纳米粒子(例如银纳米粒子、铜纳米粒子等)的烧结而形成的金属粒子烧结部7a构成。该接合层7通过在对金属纳米粒子进行加热的同时进行加压来烧结而成，该接合法被称为金属粒子接合。
另外，也可以将被接合构件设为DCB基板4的电路图案3或印刷基板9的未图示的电路图案，该电路图案3和外部导出端子10的接合、印刷基板9的未图示的电路图案和外部导出端子10的接合也能利用金属纳米粒子来进行。在这些情况下，也可以将外部导出端子10的前端的底面设为凹状。
图2表示导电柱8和半导体芯片6的上表面电极6a相接合的工序，图2(a)～图2(c)是以工序步骤表示的主要部分工序剖视图。
利用例如丝网印刷法将分散、混合有金属纳米粒子的金属纳米粒子糊料13涂布到半导体芯片6的上表面电极6a上(图2(a))。
金属纳米粒子由从铜、银、或铂等中选择的至少一种金属构成，它们的粒径为1nm～几百nm。也可以混合不同材料的金属纳米粒子来使用。金属纳米粒子糊料13例如将金属纳米粒子、在保存时或制造工序的中途为了不使金属微粒子彼此凝缩而添加的有机分散材料、接合时与有机分散材料进行反应从而去除有机分散材料的分散辅助物质与有机粘合剂(溶剂)进行混合而构成为糊状。涂布的金属纳米粒子糊料13的厚度优选为100μm～500μm。
此外，优选对于上表面电极6a，事先在表面实施铜、金、银、镍等的镀敷处理。
接着，将底面12呈凹形状的导电柱8以其前端位于所涂布的金属纳米粒子糊料13上的方式进行放置。导电柱8通过对铜或者铜合金进行成形而得，或者通过对这些构件的表面实施金、银、镍等镀敷处理而得。
之后，作为预烘干，对糊料13进行加热使溶剂蒸发，来形成凝聚的金属纳米粒子13a(图2(b))。并且，通过导电柱8的凹部对金属纳米粒子层13a施加压力，并对其进行加热，从而对金属纳米粒子进行烧结，形成金属粒子烧结部7a作为牢固的接合层7(图2(c))。
上述导电柱8的前端的底面12的凹部弯曲成球状，其深度T在10μm～200μm的范围内。此外，优选为100μm左右。若该深度T小于10μm，则按压出的金属纳米粒子的量较多，不会形成牢固的接合层7。另一方面，若该深度T超过200μm，则金属纳米粒子不能充分地进入凹部，无法很好地将加压力传递到金属纳米粒子。其结果是，无法形成牢固的接合层7。
此外，上述预烘干时的加热温度因糊料13中所包含的溶剂的不同而不同，优选例如在100℃～150℃的范围内。对金属纳米粒子进行烧结时的温度在150℃～300℃的范围内，优选为200℃左右。这是由于若烧结时的温度小于150℃，则温度过低，金属纳米粒子无法形成块状(烧结层)。此外还由于，若烧结时的温度超过300℃，则溶剂的蒸发过快，金属纳米粒子彼此迅速凝聚，无法形成对导电柱8、被接合材料即半导体芯片6的上表面电极6a进行接合的牢固的接合层7。
施加于金属纳米粒子层13a的加压力F在10MPa～50MPa的范围内，优选为30MPa左右。这是由于，若为10MPa，则加压力F过低无法形成烧结层。若超过50MPa，则加压力过高，导电柱8的端部的应力会使被接合材料产生裂纹等缺陷。
此外，为了抑制被接合材料(特别是铜的情况)的氧化，优选预烘干时的气体氛围为氮气气氛。为了在金属纳米粒子层13a与导电柱8的前端底面相接触时去除凹部中所残留的空气，优选烧结时的气体氛围为减压气氛。
如图2(b)所示，为了形成金属纳米粒子层13a使其密集地填充于导电柱8前端的底面12所形成的凹部中，由导电柱8提供给金属纳米粒子的加压力F以沿如图所示的箭头标记f的方向朝向下方且向导电柱8的中心轴方向收敛的方式来提供。因此，金属纳米粒子从导电柱8的底面12向外侧流动的情况变少。此外，通过利用凹部来对金属纳米粒子层13a进行加压，烧结所需的加压力F也会不分散地有效传递到金属纳米粒子。其结果是，能可靠地进行烧结，能形成金属粒子烧结部7a作为牢固的接合层7。
如图2(c)所示，未施加加压力F的金属纳米粒子层13a成为金属粒子未烧结部7b，不参与接合。因此，不会像焊料接合那样形成焊角。然而，金属粒子烧结部7a的烧结本身就很牢固，因此导电柱8和上表面电极6a经由牢固的接合层7来固定。
通过使导电柱8底面的平面形状呈圆形，从而加压力F均匀地传递到金属纳米粒子。对导电柱8的底面12的外周部12a进行倒角而使其光滑，因此能防止在该部位产生应力集中。这不仅能防止接合时的应力集中，也能防止接合后元件动作时的应力集中。
上述接合方法对于使用在前端的底面形成有凹部的外部导出端子10来将外部导出端子10和电路图案3接合的情况也一样适用。外部导出端子10以及电路图案3例如由铜、铜合金构成，也可以对它们的母材实施镍等镀敷处理。
SiC器件那样的WBG半导体器件能实现小型化、高温动作，因此金属粒子接合是最合适的接合方法。
图3是表示图1的导电柱8的变形例的前端的底面12的不同凹部形状的主要部分剖视图，图3(a)是凹部形状由4个平面形成的情况的图，图3(b)是凹部形状由多个平面形成的情况的图。例如，图3(a)的凹部为金字塔形状，图3(b)的凹部由2个不同的金字塔形状组合而成。任一种情况均能通过使底面12呈凹形状，将加压力F从导电柱8有效地传递到金属纳米粒子层13a中的金属纳米粒子，来获得牢固的接合层。
<实施例2>
图4是本发明的实施例2的半导体装置的结构图，图4(a)是导电柱21的主要部分剖视图，图4(b)是导电柱21的前端的底面23的平面形状图。实施例2的半导体装置的整体的主要部分剖视图除了以下所述的不同点以外，与实施例1的半导体装置的整体的主要部分剖视图(图1(a))相同。因此，下面省略重复的说明。本实施例的半导体装置的导电柱21与图1(b)、图1(c)所示的导电柱8的不同之处在于导电柱21的前端部22的形状。该导电柱21呈前端部22的直径朝着形成有凹部的底面23逐渐变小的锥形形状。导电柱21与外形大致呈圆柱且到前端为止直径相同的导电柱8相比，能使导电柱21的底面23为较小面积。前端部22的端部直径为例如100μm左右。导电柱21能高精度地与WBG半导体器件等较小的半导体芯片6的上表面电极6a(尤其例如栅极垫等)相接合。与图1的情况同样地对导电柱21的前端的底面23形成凹部，从而在凹部中作为牢固的接合层7形成金属粒子烧结部，能使较小面积的底面23与上表面电极6a可靠地接合。
图5是表示导电柱21的变形例的前端部形状的图，图5(a)是呈阶梯状变细的前端部24的图，图5(b)是将阶梯形状与锥形形状组合后的前端部25的图。导电柱21的前端的底面23的平面形状与图4(b)相同。任一个导电柱21的轴的截面形状均为圆形，但也可以是四边形、六边形等多边形。
(参考例)
在图6所示的现有的半导体装置中，对如下示例进行说明：作为接合材料105、107使用Ag(银)纳米粒子等金属纳米粒子来使半导体芯片106和DCB基板104或导电柱108接合(称为金属粒子接合)。
该接合材料105、107为糊状，在涂布到接合部分后，有对其进行加热使溶剂等蒸发的工序(预烘干)。在该状态下，金属纳米粒子维持固体粒子的状态不变。之后，为了获得足够的接合强度，边加热边对接合构件即金属纳米粒子加压，通过烧结进行接合。
图8是对金属粒子接合的机理进行说明的模型图，图8(a)～图8(c)是依次表示到金属粒子接合完成为止的工序的图。
首先，将金属纳米粒子302分散到溶剂301(活性溶媒)中，作为糊料303涂布在被接合构件304(例如，半导体芯片的上表面电极等)上(图8(a))。
接着，进行加热使溶剂301蒸发，金属纳米粒子层305(金属纳米粒子302凝聚成纳米多孔结构的层)残留在要进行接合的被接合构件304上。在温度上升到比预烘干高的状态下，利用导电柱306的前端的底面306a对该金属纳米粒子层305施加加压力G(图8(b))。通过边加热边加压，在被接合构件304和导电柱306之间金属纳米粒子彼此接触的金属纳米粒子302、与被接合构件304相接触的金属纳米粒子302以及与导电柱306的前端的底面306a相接触的金属纳米粒子302进行烧结。通过该烧结，在被接合构件304和导电柱306之间形成牢固的接合层307(图8(c))。
在该金属粒子接合中，被加压的金属纳米粒子302形成接合层307，被按压到导电柱306的外侧而没有被加压的金属纳米粒子302不形成接合层307。因此，不像焊料接合那样形成焊角。
图9是利用金属纳米粒子404将导电柱402的前端的底面402a与半导体芯片401的上表面电极401a相接合时的主要部分剖视图。
以施加于金属纳米粒子层403的加压力H将与导电柱402的平坦的底面402a相接触的金属纳米粒子404按压到导电柱402的外侧，导电柱402的底面402a下的厚度变得极薄，为几nm。按压出的金属纳米粒子层403向上卷，成为未烧结层403a。
由此，若导电柱402下的接合层405(金属纳米粒子层403烧结后的层)的厚度P变薄至几μm，则导电柱402的底面402a以及上表面电极401a的粗糙度变为相同程度，加压力H无法有效地传递到金属纳米粒子层403。因此，不能得到牢固的接合层405。
图9中示出了导电柱402的前端的底面402a为平坦并且锥形状的情况，但笔直且底面平坦的导电柱的情况也相同，难以形成牢固的接合层。
相对于该参考例，实施例1及实施例2所说明的半导体装置中，在固定于半导体芯片6的导电柱8、21的底面12、23中形成有凹部，通过对密集地填充在该凹部中的金属纳米粒子边加热边加压，来进行烧结，从而能通过金属粒子接合形成牢固的接合层7。由此，在作为无引线接合结构的导电柱连接型的功率半导体模块中，对于动作时在半导体芯片与导电柱的接合部产生的热应力，能提高连接可靠性。此外，与焊料接合相比，通过应用金属粒子接合也能实现半导体元件的高温动作，不仅能应用于硅器件也能应用于WBG器件。
此外，本发明在被接合材料不是半导体芯片而是带导电图案的绝缘基板(DCB基板)的情况下也是有效的。
标号说明
1 散热板
2 绝缘基板
3 电路图案
4 DCB基板
5 接合材料
6 半导体芯片
6a 上表面电极
7 接合层
7a 金属粒子烧结部
7b 金属接合未烧结部
8、21 导电柱
9 印刷基板
10 外部导出端子
11 密封树脂
12、23 导电柱的底面
12a、13a 导电柱底面的外周部
13 金属纳米粒子糊料
13a 金属纳米粒子层
22、24、25 前端部

Claims (14)

1.一种半导体装置，具有半导体芯片和导电连接体，其特征在于，
在固定于被接合材料的导电连接体的前端的底面形成有凹部，在该凹部中使用金属纳米粒子来与被接合材料相接合。
2.如权利要求1所述的半导体装置，其特征在于，
所述导电连接体是固定于印刷基板的导电柱或者外部导出端子。
3.如权利要求2所述的半导体装置，其特征在于，
所述导电柱的前端的形状是从锥形状、阶梯状、以及阶梯状与锥形状组合而成的形状中任选的一种。
4.如权利要求2所述的半导体装置，其特征在于，
所述导电柱的前端的底面的凹部形状是弯曲成球状的形状。
5.如权利要求1所述的半导体装置，其特征在于，
所述被接合材料是半导体芯片的表面电极、或者是固定有该半导体芯片的带导电图案的绝缘基板的导电图案。
6.如权利要求1所述的半导体装置，其特征在于，
所述导电连接体的前端的底面的凹部深度在10μm～200μm的范围内。
7.如权利要求2或4所述的半导体装置，其特征在于，
所述凹部构造成使施加于所述金属纳米粒子的加压力向所述导电连接体的中心轴方向收敛。
8.如权利要求7所述的半导体装置，其特征在于，
对所述导电连接体的底面的外周部进行倒角。
9.一种半导体装置，其特征在于，
该半导体装置至少包括：前端形成有凹部的导电连接体、以及被接合材料，
所述导电连接体以及被接合材料通过在所述凹部中高密度地填充后进行烧结而成的金属粒子烧结部来进行接合。
10.如权利要求9所述的半导体装置，其特征在于，
所述导电连接体是一端形成有所述凹部的棒状的导电柱，所述被接合材料是半导体芯片的表面电极。
11.如权利要求9所述的半导体装置，其特征在于，
所述导电连接体是一端形成有所述凹部的棒状的外部导出端子，所述被接合材料是带导电图案的绝缘基板的导电图案。
12.一种半导体装置的制造方法，其特征在于，包括：
涂布工序，在该涂布工序中，将含有金属纳米粒子的糊料涂布在被接合材料上；
放置工序，在该放置工序中，准备前端具备凹部的导电连接体，以所述凹部位于所述糊料上的方式放置所述导电连接体；以及
烧结工序，在该烧结工序中，对所述金属纳米粒子进行加热，并且通过所述导电连接体对所述金属纳米粒子施加压力，从而对所述金属纳米粒子进行烧结，使所述被接合材料与所述凹部之间相接合。
13.如权利要求12所述的半导体装置的制造方法，其特征在于，
所述烧结工序中的加热温度在150℃～300℃的范围内，所述压力在10MPa～50MPa的范围内。
14.如权利要求12所述的半导体装置的制造方法，其特征在于，
在所述烧结工序之前还具有预烘干工序，在该预烘干工序中，对所述糊料所含有的溶剂进行加热，使其蒸发。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7912835B2 (en) * 2004-05-14 2011-03-22 Oracle International Corporation Compile time opcodes for efficient runtime interpretation of variables for database queries and DML statements
WO2013136896A1 (ja) 2012-03-15 2013-09-19 富士電機株式会社 半導体装置およびその製造方法
US9312231B2 (en) * 2013-10-31 2016-04-12 Freescale Semiconductor, Inc. Method and apparatus for high temperature semiconductor device packages and structures using a low temperature process
JP6682235B2 (ja) * 2014-12-24 2020-04-15 日東電工株式会社 加熱接合用シート、及び、ダイシングテープ付き加熱接合用シート
JP6507874B2 (ja) * 2015-06-17 2019-05-08 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2017022346A (ja) 2015-07-15 2017-01-26 富士電機株式会社 半導体装置及び半導体装置の製造方法
JP6809294B2 (ja) * 2017-03-02 2021-01-06 三菱電機株式会社 パワーモジュール
JP2020051962A (ja) * 2018-09-28 2020-04-02 横河電機株式会社 センサユニット、センサユニットを備えた伝送器、センサユニットの製造方法、および、センサユニットを備えた伝送器の製造方法
JP7413668B2 (ja) * 2019-07-19 2024-01-16 富士電機株式会社 半導体装置及びその製造方法
JP7351134B2 (ja) * 2019-08-08 2023-09-27 富士電機株式会社 半導体装置及び半導体装置の製造方法
CN111243967A (zh) * 2020-02-26 2020-06-05 通富微电子股份有限公司 一种堆叠式封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1438698A (zh) * 2002-02-13 2003-08-27 恩益禧电子股份有限公司 半导体器件
CN101369547A (zh) * 2002-07-23 2009-02-18 精工爱普生株式会社 半导体器件的制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3333300B2 (ja) * 1993-01-28 2002-10-15 松下電器産業株式会社 凹凸面を有するバンプの形成方法およびそのバンプを有する半導体装置の実装方法および半導体ユニット
US5545589A (en) 1993-01-28 1996-08-13 Matsushita Electric Industrial Co., Ltd. Method of forming a bump having a rugged side, a semiconductor device having the bump, and a method of mounting a semiconductor unit and a semiconductor device
JPH07106491A (ja) 1993-09-30 1995-04-21 Toshiba Corp ピングリッドアレイ部品とその実装方法
US6107109A (en) * 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
JPH11326379A (ja) * 1998-03-12 1999-11-26 Fujitsu Ltd 電子部品用コンタクタ及びその製造方法及びコンタクタ製造装置
US7118389B2 (en) * 2004-06-18 2006-10-10 Palo Alto Research Center Incorporated Stud bump socket
JP4539980B2 (ja) * 2005-03-23 2010-09-08 富士電機システムズ株式会社 半導体装置およびその製造方法
JP4770533B2 (ja) * 2005-05-16 2011-09-14 富士電機株式会社 半導体装置の製造方法および半導体装置
JP5241177B2 (ja) * 2007-09-05 2013-07-17 株式会社オクテック 半導体装置及び半導体装置の製造方法
JP5082924B2 (ja) * 2008-02-27 2012-11-28 富士通株式会社 可動型コネクタ
CN102668051A (zh) * 2009-10-19 2012-09-12 住友电木株式会社 电子装置的制造方法、电子装置以及制造电子装置的设备
JP5581043B2 (ja) * 2009-11-24 2014-08-27 イビデン株式会社 半導体装置及びその製造方法
US8318596B2 (en) * 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
TWI423409B (zh) * 2010-04-20 2014-01-11 Raydium Semiconductor Corp 晶片結構及其晶片接合結構與製造方法
JP2012169591A (ja) * 2011-01-24 2012-09-06 Ngk Spark Plug Co Ltd 多層配線基板
WO2013136896A1 (ja) 2012-03-15 2013-09-19 富士電機株式会社 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1438698A (zh) * 2002-02-13 2003-08-27 恩益禧电子股份有限公司 半导体器件
CN101369547A (zh) * 2002-07-23 2009-02-18 精工爱普生株式会社 半导体器件的制造方法

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