JP2012169591A - 多層配線基板 - Google Patents
多層配線基板 Download PDFInfo
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- JP2012169591A JP2012169591A JP2011262096A JP2011262096A JP2012169591A JP 2012169591 A JP2012169591 A JP 2012169591A JP 2011262096 A JP2011262096 A JP 2011262096A JP 2011262096 A JP2011262096 A JP 2011262096A JP 2012169591 A JP2012169591 A JP 2012169591A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
【解決手段】少なくとも1層の樹脂絶縁層の表面上において、この表面から突出するようにして形成された導電性パッドの上面の中央部を凹ませ、この導電性パッドの上面において、上面の外周縁部によって画定される表面レベルよりも、表面全体が上方に位置するようにしてはんだ層を形成する。
【選択図】図4
Description
導体層及び樹脂絶縁層が交互に積層されてなるビルドアップ層と、
前記樹脂絶縁層の表面から突出して形成され、上面の中央部が凹んでなる導電性パッドと、
前記導電性パッドの前記上面において、前記中央部よりも外周側に位置する外周縁部によって画定される表面レベルに対し、上方に位置して形成されたはんだ層と、
を備えることを特徴とする、多層配線基板に関する。
(多層配線基板)
図1及び図2は、本実施形態における多層配線基板の平面図であり、図1は、前記多層配線基板を上側から見た場合の状態を示し、図2は、前記多層配線基板を下側から見た場合の状態を示している。また、図3は、図1及び2に示す前記多層配線基板をI−I線に沿って切った場合の断面の一部を拡大して示す図であり、図4は、図3に示す導電性パッドの近傍を拡大して示す断面図である。
次に、図1〜図4に示す多層配線基板10の製造方法について説明する。図6〜図15は、本実施形態における多層配線基板10の製造方法における工程図である。
(多層配線基板)
図16は、本実施形態における多層配線基板の断面の一部を拡大して示す図であり、図17は、図16に示す導電性パッドの近傍を拡大して示す断面図である。なお、図16及び図17は、それぞれ第1の実施形態の多層配線基板の図3及び図4に相当する。また、本実施形態の多層配線基板10’は平面視した場合の形態は、第1の実施形態の多層配線基板10の図1及び図2に示すような形態となる。
本実施形態の多層配線基板10’の製造方法は、第1の実施形態の場合と同様に、図1〜図15に示すような工程を経て積層体10bを形成した後、この積層体10bの第1の導電性パッド61が露出するような開口部41を有する第1のレジスト層41を形成し、さらに、第2の導電性パッド62の全体を覆うようにしてバリアメタル層63をメッキ法によって形成し、次いで、はんだ層64を形成することにより、図16及び図17に示すような多層配線基板10’を得る。
11 支持基板
13 プリプレグ
14 剥離シート
15 マスクパターン
21 第1の樹脂絶縁層
22 第2の樹脂絶縁層
31 第1の導体層
32 第2の導体層
41 第1のレジスト層
42 第2のレジスト層
51,52,53 ビア導体
61 第1の導電性パッド
62 第2の導電性パッド
62A 第1の導電性パッドの上面
62A−1 第1の導電性パッドの上面における中心部
62A−2 第1の導電性パッドの上面における外周縁部
62B 第1の導電性パッドの側面
63 バリアメタル層
64 はんだ層
Claims (4)
- 導体層及び樹脂絶縁層が交互に積層されてなるビルドアップ層と、
前記樹脂絶縁層の表面から突出して形成され、上面の中央部が凹んでなる導電性パッドと、
前記導電性パッドの前記上面において、前記中央部よりも外周側に位置する外周縁部によって画定される表面レベルに対して、上方に位置して形成されたはんだ層と、
を備えることを特徴とする、多層配線基板。 - 前記導電性パッドの前記上面は、連続した曲面を構成していることを特徴とする、請求項1に記載の多層配線基板。
- 前記はんだ層は、前記導電性パッドの側面を被覆して形成されたことを特徴とする、請求項1又は2に記載の多層配線基板。
- 前記導電性パッドと前記はんだ層との間に、前記導電性パッドの全面を被覆して形成されたバリアメタル層を備え、
前記はんだ層は、前記導電性パッドの全面を被覆するバリアメタル層を介して前記導電性パッドを覆い、
前記導電性パッドの前記樹脂絶縁層側に位置する側端面上に形成された前記バリアメタル層の被覆厚みは、該側端面よりも上部に位置する前記導電性パッドの表面上に形成された前記バリアメタル層の被覆厚みよりも大きいことを特徴とする、請求項3に記載の多層配線基板。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011262096A JP2012169591A (ja) | 2011-01-24 | 2011-11-30 | 多層配線基板 |
TW101102501A TWI500360B (zh) | 2011-01-24 | 2012-01-20 | 多層配線板 |
KR1020120006559A KR20120085673A (ko) | 2011-01-24 | 2012-01-20 | 다층 배선기판 |
US13/355,916 US8866025B2 (en) | 2011-01-24 | 2012-01-23 | Multilayer wiring board |
CN201210021585.6A CN102612263B (zh) | 2011-01-24 | 2012-01-30 | 多层配线基板 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011011889 | 2011-01-24 | ||
JP2011011889 | 2011-01-24 | ||
JP2011262096A JP2012169591A (ja) | 2011-01-24 | 2011-11-30 | 多層配線基板 |
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Publication Number | Publication Date |
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JP2012169591A true JP2012169591A (ja) | 2012-09-06 |
Family
ID=46529316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2011262096A Pending JP2012169591A (ja) | 2011-01-24 | 2011-11-30 | 多層配線基板 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8866025B2 (ja) |
JP (1) | JP2012169591A (ja) |
KR (1) | KR20120085673A (ja) |
CN (1) | CN102612263B (ja) |
TW (1) | TWI500360B (ja) |
Cited By (4)
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---|---|---|---|---|
JP2015032594A (ja) * | 2013-07-31 | 2015-02-16 | 京セラサーキットソリューションズ株式会社 | 配線基板 |
JP2016122776A (ja) * | 2014-12-25 | 2016-07-07 | イビデン株式会社 | バンプ付きプリント配線板およびその製造方法 |
JP2016184619A (ja) * | 2015-03-25 | 2016-10-20 | 大日本印刷株式会社 | 多層配線構造体 |
JP2017011013A (ja) * | 2015-06-18 | 2017-01-12 | 日本特殊陶業株式会社 | 検査用配線基板及び検査用配線基板の製造方法 |
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JP5530955B2 (ja) * | 2011-02-21 | 2014-06-25 | 日本特殊陶業株式会社 | 多層配線基板 |
JP5920454B2 (ja) * | 2012-03-15 | 2016-05-18 | 富士電機株式会社 | 半導体装置およびその製造方法 |
KR102029484B1 (ko) | 2013-11-29 | 2019-10-07 | 삼성전기주식회사 | 인쇄회로기판 및 이를 포함하는 칩 패키지 |
JP2016076533A (ja) * | 2014-10-03 | 2016-05-12 | イビデン株式会社 | バンプ付きプリント配線板およびその製造方法 |
TWI554174B (zh) * | 2014-11-04 | 2016-10-11 | 上海兆芯集成電路有限公司 | 線路基板和半導體封裝結構 |
US20210035818A1 (en) * | 2019-07-30 | 2021-02-04 | Intel Corporation | Sacrificial pads to prevent galvanic corrosion of fli bumps in emib packages |
JP2022161250A (ja) * | 2021-04-08 | 2022-10-21 | イビデン株式会社 | プリント配線板およびプリント配線板の製造方法 |
KR20230040817A (ko) * | 2021-09-16 | 2023-03-23 | 엘지이노텍 주식회사 | 회로기판 및 이를 포함하는 패키지 기판 |
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- 2012-01-20 KR KR1020120006559A patent/KR20120085673A/ko not_active Application Discontinuation
- 2012-01-23 US US13/355,916 patent/US8866025B2/en not_active Expired - Fee Related
- 2012-01-30 CN CN201210021585.6A patent/CN102612263B/zh not_active Expired - Fee Related
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JP2017011013A (ja) * | 2015-06-18 | 2017-01-12 | 日本特殊陶業株式会社 | 検査用配線基板及び検査用配線基板の製造方法 |
Also Published As
Publication number | Publication date |
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CN102612263A (zh) | 2012-07-25 |
CN102612263B (zh) | 2015-11-25 |
TWI500360B (zh) | 2015-09-11 |
TW201251523A (en) | 2012-12-16 |
US8866025B2 (en) | 2014-10-21 |
KR20120085673A (ko) | 2012-08-01 |
US20120186863A1 (en) | 2012-07-26 |
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