JP4981712B2 - 配線基板の製造方法及び半導体パッケージの製造方法 - Google Patents
配線基板の製造方法及び半導体パッケージの製造方法 Download PDFInfo
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- JP4981712B2 JP4981712B2 JP2008050910A JP2008050910A JP4981712B2 JP 4981712 B2 JP4981712 B2 JP 4981712B2 JP 2008050910 A JP2008050910 A JP 2008050910A JP 2008050910 A JP2008050910 A JP 2008050910A JP 4981712 B2 JP4981712 B2 JP 4981712B2
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Description
前記半導体チップ実装面と前記半導体チップとの間に樹脂を充填する樹脂充填工程とを有することを特徴とする。
図3は、本発明の第1の実施の形態に係るビルドアップ配線層を有する集合配線基板10を例示する平面図である。図4は、本発明の第1の実施の形態に係るビルドアップ配線層を有する集合配線基板10を例示する断面図である。
本発明の第1の実施の形態の変形例では、ビルドアップ配線層を有する集合配線基板10及び配線基板10aの、本発明の第1の実施の形態とは異なる製造方法について例示する。本発明の第1の実施の形態の変形例では、支持基板11の上面に凹部13を形成せず、平坦な支持基板11の上面に第1配線層17を形成する。なお、支持基板11、剥離層15等の材料や厚さ等は、本発明の第1の実施の形態の場合と同様であるため、その説明は省略する。
本発明の第2の実施の形態では、ビルドアップ配線層を有する集合配線基板10及び配線基板10aの、本発明の第1の実施の形態とは異なる製造方法について例示する。本発明の第2の実施の形態に係る方法で製造された集合配線基板及び配線基板を、便宜上、集合配線基板30及び配線基板30aとする。集合配線基板10及び配線基板10aと集合配線基板30及び配線基板30aは製造方法が異なるが、物としては同一である。
本発明の第3の実施の形態では、ビルドアップ配線層を有する集合配線基板10及び配線基板10aの、本発明の第1の実施の形態とは異なる製造方法について例示する。本発明の第3の実施の形態に係る方法で製造された集合配線基板及び配線基板を、便宜上、集合配線基板40及び配線基板40aとする。集合配線基板10及び配線基板10aと集合配線基板40及び配線基板40aは製造方法が異なるが、物としては同一である。
図36は、本発明の第4の実施の形態に係るビルドアップ配線層を有する集合配線基板50を例示する底面図である。図37は、本発明の第4の実施の形態に係るビルドアップ配線層を有する集合配線基板50を例示する断面図である。図36及び図37において、図3及び図4と同一部品については、同一符号を付し、その説明は省略する場合がある。図36及び図37において、59は補強枠、Cは半導体チップが実装される領域(以下、「半導体チップ実装領域C」とする)を示している。
図38は、本発明の第5の実施の形態に係るビルドアップ配線層を有する集合配線基板60を例示する断面図である。なお、本発明の第5の実施の形態に係るビルドアップ配線層を有する集合配線基板60を例示する平面図は、図3と同一であるため、図示及び説明は省略する。但し、集合配線基板60において、支持基板11、第1金属層64及び剥離層65は除去しておいても構わない。
本発明の第6の実施の形態では、本発明に係る配線基板に半導体チップを実装した半導体パッケージの形態、及び、本発明に係る半導体パッケージの製造方法について例示する。
10a,60a,100 配線基板
11,41,111 支持基板
12,62,19 レジスト膜
12x,19x,27x,62x,77x,270x 開口部
13,63 凹部
14,34,64 第1金属層
15,35,65 剥離層
16,66,160 第1絶縁層
16x,66x,160x 第1ビアホール
17,67,170 第1配線層
18,68 第2金属層
20,70,200 第2配線層
21,71,210 第2絶縁層
21x,71x,210x 第2ビアホール
22,72 第3金属層
23,73,230 第3配線層
24,74,240 第3絶縁層
24x,74x,240x 第3ビアホール
25,75 第4金属層
26,76,260 第4配線層
27,77,270 ソルダーレジスト
28 補助基板
29 スタンパー
29a 凸形状
41a 貫通電極
59 補強枠
78 第5金属層
80,90,110,800 半導体パッケージ
81,810 半導体チップ
82,820 ボール状端子
83,830 アンダーフィル樹脂
290 はんだバンプ
A ビルドアップ配線層形成領域
B 切断位置
C 半導体チップ実装領域
H1 高さ
P1 第1配線層170のピッチ
P2 ボール状端子820のピッチ
P3 第1配線層17のピッチ
P4 第5金属層78のピッチ
Claims (12)
- 支持基板上に配線層及び絶縁層を積層する工程と、前記支持基板を除去する工程とを含む工程により製造される、半導体チップが実装される半導体チップ実装面を有する配線基板の製造方法であって、
前記半導体チップを構成する半導体基板と同等の熱膨張率を有する材料からなる支持基板の上面に凹部を形成する工程、前記凹部が形成された前記支持基板の上面に金属層を形成する工程、及び前記金属層上に剥離層を形成する工程を含む剥離層形成工程と、
前記剥離層上に第1絶縁層を形成する第1絶縁層形成工程と、
前記凹部に対応する位置の前記金属層が露出するように、前記剥離層及び前記第1絶縁層を貫通する貫通穴を形成する貫通穴形成工程と、
前記金属層をシード層として、前記貫通穴内に露出した前記金属層上に第1配線層を形成する第1配線層形成工程と、
前記第1配線層及び前記第1絶縁層上に更に配線層及び絶縁層を積層する積層工程と
前記剥離層に所定の処理を施すことにより、前記支持基板を除去する支持基板除去工程とを有することを特徴とする配線基板の製造方法。 - 前記貫通穴は、前記貫通穴に対応する凸形状が形成された面を有するスタンパーを用いて、前記凸形状を転写することにより形成されることを特徴とする請求項1記載の配線基板の製造方法。
- 前記第1配線層は、前記半導体チップの対応する電極と電気的に接続される電極パッドとして機能することを特徴とする請求項1又は2記載の配線基板の製造方法。
- 前記剥離層は、熱エネルギーを付与すると粘着力が低下する部材を貼り付けることにより形成され、前記所定の処理は、前記熱エネルギーを付与する処理であることを特徴とする請求項1乃至3の何れか一項記載の配線基板の製造方法。
- 前記剥離層は、光エネルギーを付与すると粘着力が低下する部材を貼り付けることにより形成され、前記所定の処理は、前記光エネルギーを付与する処理であることを特徴とする請求項1乃至3の何れか一項記載の配線基板の製造方法。
- 前記剥離層は、溶剤に溶解すると粘着力が低下する部材を貼り付けることにより形成され、前記所定の処理は、前記溶剤に溶解する処理であることを特徴とする請求項1乃至3の何れか一項記載の配線基板の製造方法。
- 前記剥離層は、SiO2から構成され、前記所定の処理は、前記SiO2をエッチングにより除去する処理であることを特徴とする請求項1乃至3の何れか一項記載の配線基板の製造方法。
- 更に、前記支持基板除去工程よりも前に、前記半導体チップ実装面の反対側の面に補助基板を配設する補助基板配設工程を有することを特徴とする請求項1乃至7の何れか一項記載の配線基板の製造方法。
- 更に、前記半導体チップ実装面の前記半導体チップが実装される領域の外縁部に補強枠を配設する補強枠配設工程を有することを特徴とする請求項1乃至8の何れか一項記載の配線基板の製造方法。
- 前記支持基板の、少なくとも前記半導体チップ実装面の前記半導体チップが実装される領域に対応する領域は、シリコンから構成されていることを特徴とする請求項1乃至9の何れか一項記載の配線基板の製造方法。
- 前記支持基板の、少なくとも前記半導体チップ実装面の前記半導体チップが実装される領域に対応する領域は、硼珪酸ガラスから構成されていることを特徴とする請求項1乃至9の何れか一項記載の配線基板の製造方法。
- 請求項1乃至11の何れか一項記載の製造方法で製造された配線基板の、前記半導体チップ実装面に前記半導体チップを実装する半導体チップ実装工程と、
前記半導体チップ実装面と前記半導体チップとの間に樹脂を充填する樹脂充填工程とを有することを特徴とする半導体パッケージの製造方法。
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