TWI437677B - 半導體組件、半導體元件及其製法 - Google Patents

半導體組件、半導體元件及其製法 Download PDF

Info

Publication number
TWI437677B
TWI437677B TW099118671A TW99118671A TWI437677B TW I437677 B TWI437677 B TW I437677B TW 099118671 A TW099118671 A TW 099118671A TW 99118671 A TW99118671 A TW 99118671A TW I437677 B TWI437677 B TW I437677B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
copper
pad region
semiconductor
Prior art date
Application number
TW099118671A
Other languages
English (en)
Other versions
TW201128750A (en
Inventor
Yi Jen Lai
Chih Kang Han
Chien Pin Chan
Chih Yuan Chien
Huai Tei Yang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201128750A publication Critical patent/TW201128750A/zh
Application granted granted Critical
Publication of TWI437677B publication Critical patent/TWI437677B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

半導體組件、半導體元件及其製法
本發明係有關於無鉛焊料層(lead-free solder)，且特別是有關於一種使用無鉛焊料層之半導體元件與半導體組件(assembly)。
現今之積體電路係由實質上數百萬個主動元件所組成，其中主動元件例如電晶體與電容。這些元件初始彼此絕緣，但藉由後續連接該些元件，以形成一功能性電路。典型的內連線結溝包括水平(laternal)內連線結構(例如金屬線)與垂直內連線(例如導通孔(vias)與接觸插塞(contacts))。對現今積體電路(IC)而言，內連線結構對於其性能與密度之極限的影響日益重要。接合墊(bond pad)會形成於內連線結構的最上層，並暴露於相對應晶片之表面上。藉由接合墊將晶片電性連接到封裝基材或另一晶粒上。接合墊亦使用於打線接合(wire bonding)與覆晶接合(flip-chip bonding)。晶圓級晶片尺寸封裝(wafer level chip scale packaging,WLCSP)是目前廣泛被使用的一種封裝方法，其成本低且製程簡單。於一般的晶圓級晶片尺寸封裝(WLCSP)中，內連線結構形成於金屬層之上，接著形成凸塊底層金屬(under-bump metallurgy,UBM)與焊料球(solder ball)。
覆晶封裝(flip-chip packaging)會利用凸塊電性連接晶片輸入/輸出墊(I/O pad)與基材或封裝之導線架(lead frame)。就結構上而言，凸塊實質上包括凸塊本身與介於凸塊與輸入/數出墊(I/O pad)之間的凸塊底層金屬(under-bump metallurgy,UBM)。一凸塊底層金屬(UBM)一般會包括黏著層(adhesion layer)、阻障層(barrier layer)與濕潤層(wetting layer)，並依此順序排列於輸入/輸出墊(I/O pad)上。凸塊依據自身材料的不同，區分成焊料凸塊(solder bump)、金凸塊(gold bump)、銅柱凸塊(copper pillar bumps)與具有混合金屬之凸塊。近年來，內連線銅柱技術(copper interconnect post technology)被提出，取代焊料凸塊之使用，電子元件藉由銅柱(copper post)連接到基材上。內連線銅柱技術(copper interconnect post technology)因其凸塊橋接的可能性最小而可達到較細的間距(finer pitch)，對於電路可降低電容承載(capacitance load)，且可於高頻下操作電子元件。然而，仍然需要焊料合金(solder alloy)蓋住凸塊結構與接合用的電子元件。
一般而言，焊料合金的材料即是所謂的錫-38質量%鉛(Sn-38 mass % Pb)之錫鉛共晶焊料(Sn-Pb eutectic solder)。最近幾年，實際應用亟需使用無鉛焊料(Pb-free solder)。以二元錫銀合金(binary Sn-Ag alloy)作為無鉛焊料，其具有2.0~4.5重量%之銀，其熔點為約240~260℃。對於無鉛元件的迴焊製程(reflow soldering process)與設備皆與習知之共晶焊料類似。為了使用共熔點(eutectic point)以避免熱傷害，焊料合金的發展紛紛朝向使合金的成分盡量接近合金的共晶組成。然而，無鉛焊料材料的熔點(melting point)高於習知之錫鉛共晶焊料，因此，當TCB測試時，會產生裂縫(crack)與應力(stress)可靠度的問題，特別對於大尺寸晶粒而言，此問題更為嚴重。即使應用內連線銅柱技術(copper interconnect post technology)，使用無鉛焊料材料作為覆晶組合(flip-chip assembly)之蓋層(cap)，由於晶粒邊緣/基材介面的應力，仍然會引起裂縫(crack)的問題。
本發明提供一種半導體元件，包括：一半導體基材；一墊區域(pad region)，位於該半導體基材上；以及一凸塊結構(bump structure)，位於該墊區域之上且電性連接該墊區域，其中該凸塊結構包括一銅層與位於該銅層之上的一錫銀合金層(SnAg layer)，且該錫銀合金層(SnAg layer)中之銀含量小於1.6重量百分比。
本發明另提供一種半導體組件(assembly)，包括：一第一基材；一第二基材；以及一接合結構(joint structure)設置於該第一基材與該第二基材之間；其中該接合結構包括介於該第一基材與該第二基材之間的一凸塊結構，與介於該凸塊結構與該第二基材之間的一焊料層(solder layer)；以及其中該焊料層包括銀(silver,Ag)，且該焊料層中的銀含量小於3.0重量百分比。
於該銅柱之上，其中該無鉛焊料層包括銀，且銀含量小於1.6重量百分比；以及於溫度240℃-280℃之間回焊(reflow)該無鉛焊料層。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明提供一種控制銀含量與迴焊(reflow)溫度之無鉛焊料(lead-free solder)，其使用於具有銅柱(copper post)、保護層後內連線(post passivation interconnects)、焊料凸塊、及/或矽導通孔(through-silicon vias,TSVs)形成於其中之半導體元件，且可應用於覆晶組合(flip-chip assembly)、晶圓級晶片尺寸封裝(wafer level chip scale packaging,WLCSP)、三維積體電路堆疊(3D-IC stack)、及/或先進的封裝技術領域中。於後續的敘述中，會詳述特定的細節以充分了解本發明。然而，熟知本領域之人士應能了解的是，不需要特定的細節亦能實行本發明。於一些實施例中，不再詳述已知的結構與製程，以避免混淆本發明。說明書中提及的”一實施例”意指與此實施例相關之特定的結構特徵、結構或特性包括於至少一實施例中。因此，於各處出現的”一實施例”一詞，並非意指相同的實施例。再者，特定的結構特徵、結構或特性可以以適合的方式結合於一或多個實施例中。須注意的是，下述圖示並非依據實際比例繪製，這些圖示僅用於舉例說明使用。
此處，第1圖顯示一半導體元件於銅柱結構(copper post structure)之上具有無鉛焊料的實施例。
使用於銅柱內連線製程之基材10之例子，可包括應用於半導體積體電路製程之一半導體基材與形成於其中及/或之上的積體電路。半導體基材意指任何包括半導體材料之結構，包括，但不限於，塊狀矽(bulk silicon)、半導體晶圓(semiconductor wafer)、絕緣層上覆矽基材(silicon-on-insulator,SOI)或矽鍺(silicon germanium)基材。也可使用包括IIIA族、IVA族、VA族元素之其他半導體材料。此處所謂之積體電路意指電子電路具有多種獨立的電路元件，例如電晶體(transistors)、二極體(diodes)、電阻器(resistors)、電容(capacitors)、電感(inductors)及其他主動與被動半導體元件。基材10尚包括層間介電層(inter-layer dielectric layers)與金屬結構(metallization structure)位於積體電路之上。於金屬結構之中的層間介電層包括低介電常數(low-k)介電材料、未摻雜之矽酸鹽玻璃(un-doped sislicate glass,USG)、氮化矽、氮氧化矽、或其他常用的材料。低介電常數(low-k)介電材料之介電常數值(k值)小於約3.9，或小於約2.8。於金屬結構之中的金屬線可由銅或銅合金所組成。熟知此技術之人士應能了解金屬層之形成細節。
導電區域12是形成於最上層間介電層(top-level inter-layer dielectric layer)之中的頂部金屬層，其為導電線路的一部分，且藉由一平坦化製程(例如化學機械研磨製程(chemical mechanical polishing,CMP))處理後具有一暴露之表面。適合用於導電區域12之材料可包括，但不限於，例如銅、鋁、銅合金或其他通訊導電材料(mobile conductive materials)。於一實施例中，導電區域12為一墊區域12，其使用於接合製程(bonding process)，以將各自晶片中的積體電路連接到外部結構特徵。
形成保護層14於基材10之上並圖案化之，以部分覆蓋墊區域12。保護層14具有一開口15，藉以暴露墊區域12之一部分。保護層14由非有機材料所組成，包括末摻雜之矽酸鹽玻璃(un-doped silicate glass,USG)、氮化矽、氮氧化矽、氧化矽或上述之組合。另外，保護層14亦可由高分子層所組成，例如環氧樹脂(epoxy)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO)或類似材料。亦可使用其他相對較軟之材料，通常是有機或介電材料。
一凸塊底層金屬(under-bump-metallurgy,UBM)層16包括一擴散阻障層16a與一晶種層16b形成於保護層14之一部分上，且透過開口15電性連接到墊區域12。如圖中所示，凸塊底層金屬(UBM)層16直接接觸墊區域12暴露之部分，且襯墊於(lines)開口15之側壁與底部間。擴散阻障層16a亦稱為膠著層(glue layer)，其用以覆蓋開口15之側壁與底部。擴散阻障層16a可由氮化鉭(tantalum nitride)所組成，亦可由其他材料所組成，例如氮化鈦(titanium nitride)、鉭(tantalum)、鈦(titanium)或類似之材料。形成之方法包括物理氣相沉積法或濺鍍。晶種層16b可以是形成於擴散阻障層16a之上的銅晶種層。晶種層16b可以由銅合金所組成，銅合金中包括銀(silver)、鉻(chromium)、鎳(nickel)、錫(tin)、金(gold)或上述之組合。於一實施例中，凸塊底層金屬(UBM)層16為一銅/鈦(Cu/Ti)層。
銅柱(copper post)18形成於凸塊底層金屬(UBM)層16之上。如說明書中所述”銅柱(copper post)”意指實質存在的黏貼層(post)，其包括純元素銅、含有無可避免不純物之銅、或含少量其他元素之銅合金，其他元素包括鉭(tantalum)、銦(indium)、錫(tin)、鋅(zinc)、錳(manganese)、鉻(chromium)、鈦(titanium)、鍺(germanium)、鍶(strontium)、鉑(platinum)、鎂(magnesium)、鋁(aluminum)或鋯(zirconium)。形成之方法包括濺鍍(sputtering)、印刷(printing)、電鍍(electro plating)、無電鍍(electroless plating)與一般常使用之化學氣相沉積法(chemical vapor deposition,CVD)。例如，進行電化學電鍍(electro-chemcial plating,ECP)以形成厚度大於40μm的銅柱。於其他實施例中，銅柱的厚度為約40-70μm，其厚度也可以更大或更小。
蓋層(cap layer)20形成於銅柱18之上表面。蓋層20可作為一阻障層，用以避免銅柱18中的銅擴散到接合材料中，其中接合材料(例如焊料合金)用以接合基材10到外部結構特徵。銅擴散之避免可以增加封裝的可靠度與接合強度。蓋層20可包括鎳(nickel)、錫(tin)、錫鉛合金(tin-lead,SnPb)、金(gold,Au)、銀(silver)、鈀(palladium,Pd)、銦(In)、鎳鈀金合金(nickel-palladium-gold,NiPdAu)、鎳金合金(nickel-gold,NiAu)或其他類似之材料或合金。於一實施例中，蓋層20為厚度約1-5μm之鎳層。
無鉛焊料層(lead-free solder layer)22形成於蓋層20之上。因此，無鉛焊料層22、蓋層20與銅柱18形成於墊區域12之上，合稱為凸塊結構25。無鉛焊料層22可藉由電鍍與迴焊製程形成。於一實施例中，無鉛焊料層22為焊料球狀(solder ball)，形成於蓋層20之上。於另一實施例中，無鉛焊料層22為一電鍍錫層，位於蓋層20之上。對於無鉛焊料層系統而言，焊料層22是錫銀合金(SnAg alloy)，其中銀含量控制在低於1.6重量百分比。於迴焊製程中，調整無鉛焊料層22的熔點為約240℃~280℃。於一實施例中，無鉛焊料層22之銀含量為約1.2重量百分比-約1.6重量百分比。於另一實施例中，無鉛焊料層22之銀含量為約1.5重量百分比。使用無鉛焊料合金之封裝製程的可靠度與下列因素相關，包括：凸塊硬度、金屬間化合物(intermetallic compounds,IMCs)以及孔洞(voids)的形成有關，這些因素可能會於焊料接點(solder joint)上造成裂縫或造成熱-機械應力。如第2圖所示，當無鉛凸塊中的銀含量較低時，凸塊硬度會隨之降低。較軟的凸塊可以消除由於熱應力所引起的裂縫問題。掃描式電子顯微鏡(SEM)的資料顯示具有銀含量較低的無鉛凸塊較能避免裂縫問題。相反的，當無鉛凸塊中的銀含量增加時，在一開始就會觀察到金屬間化合物(intermetallic compounds,IMCs)、孔洞(voids)與裂縫之形成。然而，於迴焊製程之冷卻步驟期間，如果無鉛凸塊中的銀含量降到1.2重量百分比時，只有一部分的焊料凸塊會從熔融態變成固態，因此，熱應力會集中於這些凸塊而造成裂縫。關於無鉛焊料層22於迴焊製程時之迴焊溫度，調整為約240℃~280℃，不但可避免形成不完整的球型，且能抑制金屬間化合物(IMCs)與孔洞(voids)之產生。
第3A圖與第3B圖為一系列剖面圖，其用以敘述具有無鉛焊料之封裝組合的示範實施例。
基材10可被割開並封裝至一封裝基材、或另一晶粒、或具有焊料球(solder ball)或銅柱(copper post)黏著於結合墊上之封裝基材或晶粒。第1圖之結構反轉向下且附著到位於底部的另一基材100。基材100可以是一封裝基材、基板(例如印刷電路板(print circuit board,PCB))或另一合適的基材。連接結構102利用各種導電黏著點(conductive attachment points)接觸基材100，例如，位於接觸墊104及/或導電線(conductive trace)上之前-焊料層(pre-solder layer)106。前-焊料層(pre-solder layer)106可以是共晶焊料材料(eutectic solder material)，其包括錫(tin)、鉛(lead)、銀(silver)、銅(copper)、鎳(nickel)、鉍(bismuth)或上述組合之合金。使用一系列耦合製程(coupling process)，包括助焊劑應用(flux application)、晶片置換(chip replacement)、焊料接點之迴焊(reflowing of melting solder joints)與殘餘助焊劑之清潔(cleaning of flux residue)等，使接合焊料結構(joint-solder structure)108形成於基材10與基材100之間。於組合製程之後，接合焊料結構(joint-solder structure)108包含混合前-焊料層(pre-solder layer)106之無鉛焊料，其中接合焊料結構108之銀含量小於3.0重量百分比。基材10、接合焊料層(joint-solder layer)108與另一基材100合稱為封裝組合(packaging assembly)，或於本實施例中稱為覆晶組合(flip-chip assembly)。
對於晶圓級晶片尺寸封裝(wafer level chip scale packaging,WLCSP)之應用，第4圖顯示銅柱結構位於保護層後內連線(post pasivation interconnect line,PPI line)26之上之示範實施例的剖面圖，其中與第1圖~第3圖相同或類似的部分在此不再贅述。
第1圖中銅柱18與凸塊底層金屬層(UBM layer)16形成於墊區域12之上，與第1圖相比，晶圓級晶片尺寸封裝(WLCSP)製程形成一保護層後內連線(PPI line)26位於凸塊底層金屬層16與保護層14之下，與位於另一保護層24之上。保護層後內連線(PPI line)26的一末端電性連接至墊區域12(未顯示於第4圖中)，而另一末端電性連接至凸塊底層金屬層16與銅柱18。於一實施例中，於保護層14中暴露保護層後內連線(PPI line)26，而凸塊底層金屬層16直接形成於暴露的位置上。保護層24可由非有機材料所組成，包括未摻雜之矽酸鹽玻璃(un-doped silicate glass,USG)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、氧化矽(silicon oxide)或上述之組合。另外，保護層24亦可由高分子層所組成，例如環氧樹脂(epoxy)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO)或類似材料。亦可使用其他相對較軟之材料，通常是有機或介電材料。保護層後內連線(PPI line)26可包括，但不限於，例如銅、鋁、銅合金或其他可通訊導電材料(mobile conductive material)。保護層後內連線(PPI line)26尚可包括一含鎳層(圖中未顯示)於一頂部含銅層上。保護層後內連線(PPI line)26形成之方法包括電鍍(electro plating)、無電鍍(electroless plating)、濺鍍(sputtering)、化學氣相沉積法(chemical vapor deposition,CVD)或類似之方法。保護層後內連線(PPI line)26亦可作為電源線(power lines)、重新分佈線(re-distribution lines,RDL)、電感(inductors)、電容(capacitors)或任何被動元件。保護層後內連線(PPI line)26之厚度為小於約30 μm，例如為約2μm~25μm。
第5圖顯示一焊料凸塊結構之實施例之剖面圖，其中與第1圖~第3圖相同或類似的部分在此不再贅述。
與第1圖相比，銅柱18被薄銅層18a所取代，於焊料凸塊製程中接著形成蓋層20a與無鉛焊料層22a。薄銅層18a之厚度相對小於銅柱18。薄銅層18a之厚度為小於10μm。於一實施例中，薄銅層18a之厚度為約1~10μm，例如為約4~6μm，其厚度也可以更大或更小。薄銅層18a之形成方法包括濺鍍(sputtering)、印刷(printing)、電鍍(electro plating)、無電鍍(electroless plating)、與一般常使用之化學氣相沉積法(chemical vapor deposition,CVD)。無鉛焊料層22a被迴焊作為焊料球。因此，無鉛焊料層22a、蓋層20a與銅層18a合稱為一焊料凸塊結構25a。焊料層22a是錫銀合金(SnAg alloy)，其中銀含量控制在低於1.6重量百分比，其熔點為約240℃~280℃。於一實施例中，無鉛焊料層22a之銀含量為約1.2重量百分比-約1.6重量百分比。於另一實施例中，無鉛焊料層22a之銀含量為約1.5重量百分比。
第6圖顯示第5圖半導體元件之封裝組件之實施例的剖面圖，其中與第1圖~第3圖相同或類似的部分在此不再贅述。於組合製程之後，基材10、接合焊料層108與另一基材100可合稱為一封裝組件，或於本實施例中，稱為覆晶組件(flip-chip assembly)。接合焊料層108包括混合前焊料之無鉛焊料，其中接合焊料層108之銀含量小於3.0重量百分比。
對於晶圓級晶片尺寸封裝(wafer level chip scale packaging,WLCSP)之應用，第7圖顯示焊料凸塊結構位於銅製保護層後內連線(Cu PPI)之上之示範實施例的剖面圖，其中與第1圖~第6圖相同或類似的部分在此不再贅述。與第5圖相比，晶圓級晶片尺寸封裝(WLCSP)製程形成一保護層後內連線(PPI line)26位於凸塊底層金屬層16與保護層14之下，與位於另一保護層24之上。保護層後內連線(PPI line)26的一末端電性連接至墊區域12(未顯示於第7圖中)，而另一末端電性連接至凸塊底層金屬層16。於一實施例中，於保護層14中暴露保護層後內連線(PPI line)26，而凸塊底層金屬層16直接形成於暴露的位置上。
第8A~8C圖顯示使用無鉛焊料製作垂直堆疊元件之實施例的剖面圖。長期以來(long-awaited goal)，三維(3D)晶圓對晶圓(wafer-to-wafer)、晶粒對晶圓(die-to-wafer)、或晶粒對晶粒(die-to-die)垂直堆疊技術的目標在於，垂直堆疊很多層主動元件(例如處理器(processors)、程式化元件(programmable devices)與記憶體元件(memory devices))，以縮短平均線長(average wire lengths)，進而減少內連線RC延遲(RC delay)並增加系統的性能表現。
三維(3D)內連線於單一晶圓或於晶粒對晶圓垂直堆疊之主要挑戰在於，如何製造好的矽導通孔(through-silicon via,TSV)，此矽導通孔提供一訊號路徑，使高阻抗訊號從晶圓之一側穿過另一側。一般製備矽導通孔(through-silicon via,TSV)的目的在於，使填滿導電材料之矽導通孔能完全地穿過所在的該層，並連接與接觸另一接合層之矽導通孔與導體。
請參見第8A圖，提供一晶圓200，其包括一基材210。基材210之實施例可包括應用於半導體積體電路製程之一半導體基材與形成於其中及/或之上的積體電路。基材210具有第一表面210a與相對於第一表面210a之第二表面210b。第一表面210a可以作為前側(frontside)，且位於積體電路之上，其中積體電路包括形成主動與被動元件(例如電晶體、電阻器、電容、二極體、電感或類似之元件)，這些元件用以連接接合墊(bond pads)及/或其他內連線結構(interconnection structures)。電路可以是任何適用於特殊應用的電路。功能可包括記憶體結構(memory structures)、製程結構(process structures)、感測器(sensors)、放大器(amplifiers)、配電系統(power distribution)、輸入/輸出電路(input/output circuitry)或類似之結構。第二表面210b作為後側(backside)，其將會被薄化與製程化以形成接合墊及/或其他內連線結構於其中。
第一介電層214形成於第一表面210a，其中形成接觸插塞(contacts)以電性連接至各自的元件。一般而言，第一介電材料214可由，例如低介電常數(low-k)介電材料、氧化矽(silicon oxide)、矽磷酸鹽玻璃(phosphosilicate glass,PSG)、硼磷酸鹽玻璃(borophosphosilicate glass,BPSG)、氟酸化矽酸鹽玻璃(fluorinated silicate glass,FSG)、或類似之材料所組成，由本領域所熟知之適合的方法所形成。亦可使用其他材料或其他製程。
複數個導通孔(through vias)216穿過至少一部分基材210。導通孔216是一種填充導體之插塞(conductor-filled plug)，其從第一表面210a延伸到第二表面210b，且達到預定之深度(intended depth)。此外，一絕緣層形成於導通孔216之側壁與底部，且導通孔216與基材210絕緣。導通孔216可由任何合適的導電材料所組成，較佳由高導電、低電阻金屬、元素金屬、過渡金屬(transition metal)或類似之材料所組成。於一實施例中，導通孔216為溝槽填充由銅(Cu)、鎢(W)、銅合金(Cu alloy)或類似之材料所組成之導電層。由鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或上述之組合所組成之導電阻障層(conductive barrier layer)形成於溝槽中且圍繞導電層。絕緣層由一般使用之介電材料所組成，例如氮化矽、氧化矽(例如四乙氧基矽酸鹽(tetra-ethyl-ortho-silicate oxide,TEOS))或類似之材料。
第一內連線結構218包括金屬間介電層、位於積體電路上之金屬層(metallization structure)、第一介電層214與導通孔216。位於金屬層之中的金屬間介電層包括低介電常數(low-k)介電材料、未摻雜之矽酸鹽玻璃(un-doped silicate glass,USG)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)或其他一般常使用的材料。低介電常數(low-k)介電材料之介電常數值(k)可小於約3.9，或小於約2.8。金屬層包括金屬線與導通孔，其可由銅或銅合金所組成，且可利用已知之鑲嵌製程(damascene processes)形成。熟知此領域之人士應能了解金屬層之形成細節。
保護層220形成於第一內連線結構218之上。保護層220由例如氧化矽、氮化矽、未摻雜之矽酸鹽玻璃(un-doped silicate glass,USG)、聚亞醯胺(polyimide)、及/或上述之多層結構所組成。金屬墊(metal pad)222形成於保護層220之上。金屬墊222可由鋁(aluminum)、銅(copper)、銀(silver)、金(gold)、鎳(nickel)、鎢(tungsten)、上述合金、及/或上述之多層所組成。金屬墊可電性連接至元件與導通孔216，例如穿過底下的第一內連線結構218。介電緩衝層(dielectric buffer layer)224形成於金屬墊之上，且被圖案化以提供凸塊形成視窗(bump formation window)。介電緩衝層(dielectric buffer layer)224可由高分子組成，例如環氧樹脂(epoxy)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO)或類似材料。亦可使用其他相對較軟之材料，通常是有機或介電材料。凸塊結構226接著形成於金屬墊222之上且電性連接至金屬墊222。凸塊結構224請參見第1、4、5與7圖之結構25、25a，因此細節在此不再贅述。
請參見第8B圖，晶圓200藉由一黏著層(adhesive layer)302黏著至載板(carrier)300且接著翻轉(flip)此接合結構(bonded structure)。既然接合結構被翻轉，因此之後對第二表面210b進行薄化製程(thinning process)，例如研磨及/或蝕刻(grinding and/or etching)，以移除大部分的基材210，以達到最後所需之厚度，得到薄化基材210”，其中薄化基材210”之預定厚度視所選擇之半導體封裝的目的而定。熟知此領域之人士應能了解的是，亦可使用其他薄化製程，例如研磨製程(包括濕式研磨(化學機械研磨(CMP))與乾式研磨)、電漿蝕刻製程、濕式蝕刻製程或類似之製程。於一實施例中，暴露導通孔216之末端216a，且於薄化製程之後，導通孔216之末端216a從薄化基材210”之第二表面210b”延伸突出。接著，處理薄化基材210”之第二表面210b”，以形成一第二內連線結構228電性連接至導通孔216。例如，第二內連線結構228包括電性連接及/或其他形成於薄化基材210”表面210b”上之其他結構(例如重新分佈層、接合墊、焊料凸塊或銅凸塊)。後側研磨與內連線結構之形成方法詳述於美國專利申請案12/332,934中，發明名稱為”後側連線至具有重新分佈線之導通孔”(Backside Connection to TSVs having Redistribution Lines)，與美國專利申請案12/347,742，發明名稱為”接合墊連接至具有漸尖輪廓之重新分佈線”(Bond pad Connection to Redistribution Lines Having Tapered Profiles)，這些申請案在此作為參考案，因此，不再詳述製作的細節。
接著，晶粒400接合至薄化基材210”。晶粒400可以是記憶體晶片(memory chips)、無線射頻(radio frequency,RF)、邏輯晶片(logic chips)或其他晶片。每一個晶粒400包括凸塊結構402用以電性連接至薄化晶圓210”之第二內連線結構228。凸塊結構402包括一銅層404、於銅層404之上視需要而設之蓋層406、與於銅層404上之一無鉛焊料層408。銅層404可以是厚度為約0.5~1.0μm之薄銅層，或者是厚度為約40~70μm之厚銅層。視需要而設之蓋層406可包括鎳(nickel)、金(gold,Au)、銀(silver)、鈀(palladium,Pd)、銦(indium,In)、鎳-鈀-金合金(nickel-palladium-gold,NiPdAu)、鎳金合金(NiAu)或類似之材料或合金。無鉛焊料層408可以是電鍍層或迴焊後作為焊料球。無鉛焊料層408為錫銀合金，其中銀含量控制在小於1.6重量百分比(wt%)。於迴焊製程中，無鉛焊料層408之熔化溫度可調整控制在溫度240℃~280℃間。於一實施例中，無鉛焊料層408之銀含量介於約1.2重量百分比~1.6重量百分比。於其他實施例中，無鉛焊料層408之銀含量為約1.5重量百分比。
請參見第8C圖，晶粒400經由凸塊結構402接合至第二內連線結構228，形成晶粒對晶圓堆疊(die-to-wafer)500。使用一系列耦合製程(coupling process)，包括助焊劑應用(flux application)、晶片置換(chip replacement)、焊料接點之迴焊(reflowing of melting solder joints)與殘餘助焊劑之清潔(cleaning of flux residue)等，使接合結構(joint structure)502形成於晶圓210”與晶粒400之間。接合結構502包括凸塊結構402、第二內連線結構228、與接合於其中的無鉛焊料層408。因此，載板300從薄化晶圓210”中脫附(detached from)，接著，使用常用的方法沿著切割線(cutting lines)切割晶粒對晶圓堆疊500，以將晶粒對晶圓堆疊分離成獨立的積體電路堆疊(IC stacks)，且之後封裝至一封裝基材上，其中封裝基材具有焊料凸塊或銅凸塊鑲嵌於封裝基材之接合墊(pad)上。於一些實施例中，封裝基材被其他晶粒所取代。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．基材
12．．．導電區域
14．．．保護層
15．．．開口
16．．．凸塊底層金屬(UBM)
16a．．．擴散阻障層
16b．．．晶種層
18、18a．．．銅柱(copper post)
20、20a．．．蓋層
22、22a．．．無鉛焊料層(lead-free solder layer)
24．．．保護層
25．．．凸塊結構
25a．．．焊料凸塊結構
26．．．保護層後內連線(PPI line)
100．．．基材
102．．．連接結構
104．．．接觸墊
106．．．前焊料層
108．．．接合焊料結構
200．．．晶圓
210．．．基材
210”．．．薄化基材
210a．．．第一表面
210b．．．第二表面
210b”．．．薄化基材之第二表面
214．．．第一介電層
216．．．導通孔
216a．．．導通孔之末端
218．．．第一內連線結構
220．．．保護層
222．．．金屬墊
224．．．介電緩衝層
226．．．凸塊結構
228．．．第二內連線結構
300．．．載板
302．．．黏著層
400．．．晶粒
402．．．凸塊結構
404．．．銅層
406．．．蓋層
408．．．無鉛焊料層
500．．．晶粒對晶圓(die-to-wafer)堆疊
502．．．接合結構
第1圖為一剖面圖，用以說明本發明一半導體元件之實施例，其中半導體元件具有無鉛焊料位於銅柱結構之上。
第2圖為一關係圖，用以說明本發明無鉛焊料中的銀含量與凸塊硬度之關係。
第3A~3B圖為一系列剖面圖，用以說明本發明具有無鉛焊料之封裝組件(package assembly)之實施例。
第4圖為一剖面圖，用以說明對於晶圓級晶片尺寸封裝(WLCSP)，本發明之銅柱結構位於銅製保護層後內連線(Cu PPI)上之實施例。
第5圖為一剖面圖，用以說明焊料凸塊結構之實施例。
第6圖為一剖面圖，用以說明具有焊料凸塊結構之封裝組件。
第7圖為一剖面圖，用以說明對於晶圓級晶片尺寸封裝(WLCSP)，本發明之焊料凸塊結構位於銅製保護層後內連線(Cu PPI)上之實施例。
第8A~8C圖為一系列剖面圖，用以說明使用無鉛焊料製作垂直堆疊元件之實施例。
10．．．基材
12．．．導電區域
14．．．保護層
15．．．開口
16．．．凸塊底層金屬(UBM)
16a．．．擴散阻障層
16b．．．晶種層
18．．．銅柱(copper post)
20．．．蓋層
22．．．無鉛焊料層(lead-free solder layer)
25．．．凸塊結構

Claims (12)

  1. 一種半導體元件，包括：一半導體基材；一墊區域(pad region)，位於該半導體基材上；一保護層，位於該半導體基材上及該墊區域之至少一部分上，該保護層具有一開口以露出該墊區域之至少另一部分；以及一凸塊結構(bump structure)，位於該墊區域之上且透過該開口電性連接該墊區域，其中該凸塊結構包括一銅層與位於該銅層之上的一錫銀合金層(SnAg layer)，該錫銀合金層之熔點在介於240℃~280℃之間，且該錫銀合金層(SnAg layer)中之銀含量大於1.2重量百分比且小於1.6重量百分比。
  2. 如申請專利範圍第1項所述之半導體元件，其中該錫銀合金層(SnAg layer)中之銀含量大於1.5重量百分比。
  3. 如申請專利範圍第1項所述之半導體元件，其中該銅層為厚度大於40微米(μm)之一銅柱(copper post)。
  4. 如申請專利範圍第1項所述之半導體元件，其中該銅層之厚度小於10微米(μm)。
  5. 如申請專利範圍第1項所述之半導體元件，尚包括：一鎳層(nickel layer)介於該銅層與該錫銀合金層(SnAg layer)之間。
  6. 如申請專利範圍第1項所述之半導體元件，尚包 括：一導通孔(through via)穿過該半導體基材且電性連接該墊區域，其中該導通孔包括銅。
  7. 一種半導體組件(assembly)，包括：一第一基材；一墊區域(pad region)，位於該第一基材上；一保護層，位於該第一基材上及該墊區域之至少一部分上，該保護層具有一開口以露出該墊區域之至少另一部分；一第二基材；以及一接合結構(joint structure)設置於該第一基材與該第二基材之間且透過該開口電性連接該墊區域；其中該接合結構包括介於該第一基材之該墊區域與該第二基材之間的一凸塊結構，與介於該凸塊結構與該第二基材之間的一焊料層(solder layer)；以及其中該焊料層包括銀(silver,Ag)，且該焊料層中的銀含量小於3.0重量百分比，其中該第一基材與該第二基材至少之一為一半導體基材，且該半導體基材包括一導通孔(through via)由該半導體基材之一第一表面延伸穿過該半導體基材至該半導體基材之一第二表面且電性連接該凸塊結構。
  8. 如申請專利範圍第7項所述之半導體組件，其中該凸塊結構包括厚度大於40微米(μm)之一銅柱(copper post)。
  9. 如申請專利範圍第7項所述之半導體組件，其中 該凸塊結構包括一銅層以及一含鎳層位於該銅層之上。
  10. 如申請專利範圍第7項所述之半導體組件，其中該凸塊結構包括厚度小於10微米(μm)之一銅層。
  11. 一種半導體元件之製法，包括以下步驟：提供一半導體基材；形成一墊區域(pad region)位於該半導體基材之上；形成一保護層位於該半導體基材上及該墊區域之至少一部分上，該保護層具有一開口以露出該墊區域之至少另一部分；形成一銅柱(copper post)位於該墊區域之上，該銅柱透過該開口電性連接該墊區域；形成一無鉛焊料層(lead-free solder layer)位於該銅柱之上，其中該無鉛焊料層包括銀，該無鉛焊料層之熔點在介於240℃~280℃之間，且銀含量小於1.6重量百分比；以及回焊(reflow)該無鉛焊料層。
  12. 如申請專利範圍第11項所述之半導體元件之製法，其中該無鉛焊料層之銀含量大於1.2重量百分比。
TW099118671A 2010-02-09 2010-06-09 半導體組件、半導體元件及其製法 TWI437677B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/702,636 US8610270B2 (en) 2010-02-09 2010-02-09 Semiconductor device and semiconductor assembly with lead-free solder

Publications (2)

Publication Number Publication Date
TW201128750A TW201128750A (en) 2011-08-16
TWI437677B true TWI437677B (zh) 2014-05-11

Family

ID=44353045

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099118671A TWI437677B (zh) 2010-02-09 2010-06-09 半導體組件、半導體元件及其製法

Country Status (3)

Country Link
US (2) US8610270B2 (zh)
CN (1) CN102148211B (zh)
TW (1) TWI437677B (zh)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009363A (ja) * 2009-06-24 2011-01-13 Nec Corp 半導体装置及びその製造方法並びにこれを用いた複合回路装置
US8232643B2 (en) * 2010-02-11 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Lead free solder interconnections for integrated circuits
US8259464B2 (en) * 2010-06-24 2012-09-04 Maxim Integrated Products, Inc. Wafer level package (WLP) device having bump assemblies including a barrier metal
US20120211884A1 (en) * 2011-02-23 2012-08-23 Frank Stepniak Wafer chip scale package connection scheme
US8912649B2 (en) * 2011-08-17 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy flip chip bumps for reducing stress
CN102270590A (zh) * 2011-09-01 2011-12-07 苏州晶方半导体科技股份有限公司 晶圆级封装结构及封装方法
TWI449141B (zh) * 2011-10-19 2014-08-11 Richtek Technology Corp 晶圓級晶片尺度封裝元件以及其製造方法
CN102543766A (zh) * 2012-01-17 2012-07-04 南通富士通微电子股份有限公司 一种柱状凸点封装工艺
US9159686B2 (en) * 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer
JP2013187423A (ja) * 2012-03-08 2013-09-19 Elpida Memory Inc 半導体チップ及びその製造方法
CN102543783B (zh) * 2012-03-28 2015-06-24 上海交通大学 一种使用铟和微针锥结构的热压缩芯片低温互连方法
US8741691B2 (en) * 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit
TWI484610B (zh) * 2012-07-09 2015-05-11 矽品精密工業股份有限公司 半導體結構之製法與導電凸塊
TWI490994B (zh) * 2012-09-03 2015-07-01 矽品精密工業股份有限公司 半導體封裝件中之連接結構
US9053990B2 (en) * 2012-10-25 2015-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bump interconnection techniques
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
US8803337B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure having dies with connectors
US9691745B2 (en) * 2013-06-26 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure for forming a package on package (PoP) structure and method for forming the same
US9252076B2 (en) 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US20150048499A1 (en) * 2013-08-16 2015-02-19 Macrotech Technology Inc. Fine-pitch pillar bump layout structure on chip
CN104576323B (zh) * 2013-10-15 2017-12-01 中航（重庆）微电子有限公司 一种金属图形化结构及方法
JP6267229B2 (ja) * 2013-11-20 2018-01-24 株式会社日立製作所 鉛フリーはんだ箔および半導体装置
CN104064545A (zh) * 2014-02-24 2014-09-24 南通富士通微电子股份有限公司 半导体封装结构
US9806046B2 (en) * 2014-03-13 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and manufacturing method
US9779969B2 (en) * 2014-03-13 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method
US20150262952A1 (en) * 2014-03-13 2015-09-17 Taiwan Semiconductor Manufacturing Co., Ltd Bump structure and method for forming the same
US9935081B2 (en) * 2014-08-20 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid interconnect for chip stacking
US9564409B2 (en) * 2015-01-27 2017-02-07 Semiconductor Components Industries, Llc Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
US9847310B2 (en) 2015-07-18 2017-12-19 Semiconductor Components Industries, Llc Flip chip bonding alloys
US10115716B2 (en) * 2015-07-18 2018-10-30 Semiconductor Components Industries, Llc Die bonding to a board
KR102430984B1 (ko) 2015-09-22 2022-08-09 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10636767B2 (en) * 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
KR20180136148A (ko) * 2017-06-14 2018-12-24 에스케이하이닉스 주식회사 범프를 구비하는 반도체 장치
KR102588125B1 (ko) * 2018-02-02 2023-10-11 삼성전자주식회사 반도체 장치
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN111106073B (zh) * 2018-10-26 2022-08-05 株洲中车时代半导体有限公司 一种功率半导体器件的低应力薄膜结构
DE102020130638A1 (de) * 2019-12-11 2021-06-17 Infineon Technologies Ag Lotmaterial, schichtstruktur, chipgehäuse, verfahren zum bilden einer schichtstruktur, verfahren zum bilden eines chipgehäuses, chipanordnung und verfahren zum bilden einer chipanordnung
TWI760726B (zh) * 2020-04-14 2022-04-11 矽品精密工業股份有限公司 電子封裝件及其製法與導電結構
JP7484663B2 (ja) * 2020-10-29 2024-05-16 株式会社デンソー 接合構造体、電子装置、接合構造体の製造方法

Family Cites Families (146)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6701136A (zh) 1967-01-25 1968-07-26
FI61588C (fi) 1980-08-01 1982-08-10 Lohja Ab Oy Foerfarande foer utfoerande av elektriskt ledande genomfoeringar i tunnfilmer
US4720740A (en) 1985-11-26 1988-01-19 Clements James R Electronic device including uniaxial conductive adhesive and method of making same
US5134460A (en) 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
JP3078646B2 (ja) 1992-05-29 2000-08-21 株式会社東芝 インジウムバンプの製造方法
JPH0637143A (ja) 1992-07-15 1994-02-10 Toshiba Corp 半導体装置および半導体装置の製造方法
JP3057130B2 (ja) 1993-02-18 2000-06-26 三菱電機株式会社 樹脂封止型半導体パッケージおよびその製造方法
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
JP3296400B2 (ja) 1995-02-01 2002-06-24 東芝マイクロエレクトロニクス株式会社 半導体装置、その製造方法およびＣｕ製リード
US6464895B2 (en) 1995-03-24 2002-10-15 Rhodia Chimie Reagent and process which are useful for grafting a substituted difluoromethyl group onto a compound containing at least one electrophilic function
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6232563B1 (en) 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3654485B2 (ja) 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
JP2000094181A (ja) * 1998-09-24 2000-04-04 Sony Corp はんだ合金組成物
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
JP4131595B2 (ja) 1999-02-05 2008-08-13 三洋電機株式会社 半導体装置の製造方法
JP3667184B2 (ja) 1999-02-26 2005-07-06 住友ベークライト株式会社 半導体装置
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6544880B1 (en) 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
KR100313706B1 (ko) 1999-09-29 2001-11-26 윤종용 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6387793B1 (en) 2000-03-09 2002-05-14 Hrl Laboratories, Llc Method for manufacturing precision electroplated solder bumps
TW502424B (en) 2000-04-19 2002-09-11 Advanced Interconnect Tech Ltd Method of forming lead-free bump interconnections
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP2002050647A (ja) 2000-08-01 2002-02-15 Sharp Corp 半導体装置及びその製造方法
TW464927B (en) 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
JP3700563B2 (ja) 2000-09-04 2005-09-28 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US6426556B1 (en) 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6869831B2 (en) 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
US6853076B2 (en) 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
EP1472730A4 (en) 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6805974B2 (en) * 2002-02-15 2004-10-19 International Business Machines Corporation Lead-free tin-silver-copper alloy solder composition
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
KR20040111395A (ko) 2002-03-12 2004-12-31 페어차일드 세미컨덕터 코포레이션 웨이퍼 레벨의 코팅된 구리 스터드 범프
JP4034107B2 (ja) 2002-04-17 2008-01-16 株式会社ルネサステクノロジ 半導体装置
AU2003269066A1 (en) 2002-05-16 2003-12-02 Agency For Science, Technology And Research Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip
US6596619B1 (en) 2002-05-17 2003-07-22 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
US6590295B1 (en) 2002-06-11 2003-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic device with a spacer redistribution layer via and method of making the same
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US7012333B2 (en) 2002-12-26 2006-03-14 Ebara Corporation Lead free bump and method of forming the same
US7008867B2 (en) 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
US7271497B2 (en) 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US7078796B2 (en) 2003-07-01 2006-07-18 Freescale Semiconductor, Inc. Corrosion-resistant copper bond pad and integrated device
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US20060278982A1 (en) 2003-07-16 2006-12-14 Koninklijke Philips Electronics N.V. Metal bump with an insulation for the side walls and method of fabricating a chip with such a metal bump
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7462942B2 (en) 2003-10-09 2008-12-09 Advanpack Solutions Pte Ltd Die pillar structures and a method of their formation
JP3794403B2 (ja) 2003-10-09 2006-07-05 セイコーエプソン株式会社 半導体装置
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005175128A (ja) * 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP3981089B2 (ja) 2004-02-18 2007-09-26 株式会社東芝 半導体装置とその製造方法
US7309904B2 (en) 2004-03-24 2007-12-18 Yamaha Corporation Semiconductor device, magnetic sensor, and magnetic sensor unit
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
TWI240977B (en) 2004-07-23 2005-10-01 Advanced Semiconductor Eng Structure and formation method for conductive bump
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060043603A1 (en) * 2004-08-31 2006-03-02 Lsi Logic Corporation Low temperature PB-free processing for semiconductor devices
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
TWI242867B (en) 2004-11-03 2005-11-01 Advanced Semiconductor Eng The fabrication method of the wafer and the structure thereof
US7323406B2 (en) 2005-01-27 2008-01-29 Chartered Semiconductor Manufacturing Ltd. Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
US7348210B2 (en) 2005-04-27 2008-03-25 International Business Machines Corporation Post bump passivation for soft error protection
US7468545B2 (en) 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
US7391112B2 (en) 2005-06-01 2008-06-24 Intel Corporation Capping copper bumps
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US20070023904A1 (en) 2005-08-01 2007-02-01 Salmon Peter C Electro-optic interconnection apparatus and method
US7224067B2 (en) 2005-09-15 2007-05-29 Intel Corporation Intermetallic solder with low melting point
US7566650B2 (en) 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
JP4755486B2 (ja) 2005-11-17 2011-08-24 Ｏｋｉセミコンダクタ株式会社 半導体装置およびその製造方法
KR101486587B1 (ko) 2005-11-18 2015-01-26 레플리서러스 그룹 에스에이에스 마스터 전극 및 마스터 전극 형성 방법
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7524755B2 (en) 2006-02-22 2009-04-28 Chartered Semiconductor Manufacturing, Ltd. Entire encapsulation of Cu interconnects using self-aligned CuSiN film
US20070287279A1 (en) 2006-06-08 2007-12-13 Daubenspeck Timothy H Methods of forming solder connections and structure thereof
KR100762354B1 (ko) 2006-09-11 2007-10-12 주식회사 네패스 플립칩 반도체 패키지 및 그 제조방법
TWI360211B (en) 2006-10-05 2012-03-11 Flipchip Int Llc Wafer-level interconnect for high mechanical relia
US20090197114A1 (en) 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US7485564B2 (en) 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US7838424B2 (en) 2007-07-03 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching
US8669658B2 (en) 2007-07-24 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Crosstalk-free WLCSP structure for high frequency application
TWI339868B (en) 2007-08-15 2011-04-01 Siliconware Precision Industries Co Ltd Semiconductor device and method for fabricating the same
US7759792B2 (en) 2007-08-15 2010-07-20 Infineon Technologies Ag Integrated circuit including parylene material layer
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
JP2009094378A (ja) 2007-10-11 2009-04-30 Panasonic Corp 半導体装置及びその製造方法
US7713861B2 (en) 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8039964B2 (en) * 2008-02-27 2011-10-18 International Business Machines Corporation Fluorine depleted adhesion layer for metal interconnect structure
US7648899B1 (en) 2008-02-28 2010-01-19 Novellus Systems, Inc. Interfacial layers for electromigration resistance improvement in damascene interconnects
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US7956442B2 (en) 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
TW201019440A (en) 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US9082762B2 (en) * 2009-12-28 2015-07-14 International Business Machines Corporation Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices

Also Published As

Publication number Publication date
US8610270B2 (en) 2013-12-17
US8952534B2 (en) 2015-02-10
CN102148211A (zh) 2011-08-10
CN102148211B (zh) 2013-04-24
TW201128750A (en) 2011-08-16
US20140070409A1 (en) 2014-03-13
US20110193219A1 (en) 2011-08-11

Similar Documents

Publication Publication Date Title
TWI437677B (zh) 半導體組件、半導體元件及其製法
US10734347B2 (en) Dummy flip chip bumps for reducing stress
US9627339B2 (en) Method of forming an integrated circuit device including a pillar capped by barrier layer
US11257714B2 (en) Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
US9653423B2 (en) Integrated circuit structure having dies with connectors
US10163710B2 (en) Method of manufacturing semiconductor device by applying molding layer in substrate groove
US9018758B2 (en) Cu pillar bump with non-metal sidewall spacer and metal top cap
US9041225B2 (en) Integrated circuit structure having dies with connectors
US20130099371A1 (en) Semiconductor package having solder jointed region with controlled ag content
US9786622B2 (en) Semiconductor package
US8716858B2 (en) Bump structure with barrier layer on post-passivation interconnect
US10050000B2 (en) Bump-on-trace structures with high assembly yield
US8647925B2 (en) Surface modification for handling wafer thinning process