TWI760726B - 電子封裝件及其製法與導電結構 - Google Patents

電子封裝件及其製法與導電結構 Download PDF

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TWI760726B
TWI760726B TW109112491A TW109112491A TWI760726B TW I760726 B TWI760726 B TW I760726B TW 109112491 A TW109112491 A TW 109112491A TW 109112491 A TW109112491 A TW 109112491A TW I760726 B TWI760726 B TW I760726B
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layer
conductive
electronic package
metal
conductive structure
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TW109112491A
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TW202139305A (zh
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黃玉龍
鄭子企
林長甫
許元鴻
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矽品精密工業股份有限公司
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Priority to TW109112491A priority Critical patent/TWI760726B/zh
Priority to CN202010391873.5A priority patent/CN113540009A/zh
Priority to US16/922,169 priority patent/US11410954B2/en
Publication of TW202139305A publication Critical patent/TW202139305A/zh
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Abstract

一種電子封裝件，係包括一配置有第一導電結構之第一基材以及一配置有第二導電結構之第二基材，該第一導電結構於該第一基材上依序形成有第一導電層、凸塊體與金屬輔助層，且該第二導電結構於該第二基材上依序形成有金屬柱、第二導電層、金屬層與銲錫層，以令該銲錫層結合該凸塊體及該金屬輔助層，使該第一基材與該第二基材相堆疊，故藉由該凸塊體與該金屬輔助層之設計，以於回銲該銲錫層後，可完全反應出IMC，因而該些導電結構之體積不會持續縮小，因而能有效避免該些導電結構碎裂之問題。

Description

電子封裝件及其製法與導電結構
本發明係有關一種半導體封裝製程，尤指一種電子封裝件及其製法與導電結構。
現行覆晶技術因具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等型態的封裝模組、或將晶片立體化堆疊整合為三維積體電路(3D IC)晶片堆疊技術等。
於覆晶封裝製程中，因晶片與封裝基板之熱膨脹係數的差異甚大，故晶片外圍的凸塊無法與封裝基板上對應的接點形成良好的接合，使得凸塊容易自封裝基板上剝離。另一方面，隨著積體電路之積集度的增加，因晶片與封裝基板之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，其結果將導致晶片與封裝基板之間的電性連接之可靠度(reliability)下降，並造成信賴性測試的失敗。
為了解決上述問題，業界遂發展出以半導體基材作為中介結構的製程，其係於一封裝基板與一半導體晶片之間增設一矽中介板(silicon interposer)，俾透過該矽中介板與該半導體晶片的材質接近，以避免熱膨脹係數不匹配所產生的問題。具體地，如第1圖所示之半導體封裝件1，係提供一矽中介板(Through Silicon interposer，簡稱TSI)10，該矽中介板10具有相對之置晶側10b與轉接側10a、及連通該置晶側10b與轉接側10a之複數導電矽穿孔(Through-silicon via，簡稱TSV)100，且該置晶側10b上具有一線路重佈結構(Redistribution layer，簡稱RDL)11，以供半導體晶片6之複數具有小間距之電極墊60藉由複數銲錫凸塊61電性結合至該線路重佈結構11上，再以底膠62包覆該些銲錫凸塊61，且於該導電矽穿孔100上藉由複數如銲料凸塊之導電元件17電性結合至封裝基板7之複數具有大間距之銲墊70，之後形成封裝膠體8於該封裝基板7上，以包覆該半導體晶片6及矽中介板10。
惟，習知半導體封裝件1之矽中介板10與封裝基板7之間，當回銲該導電元件17後，銲錫材尚未完全反應成介面金屬共化物(Intermetallic Compound，簡稱IMC)而立即形成封裝膠體8，此時因回銲過程所產生之殘留熱應力會集中在該些導電元件17中，致使該IMC之持續反應會導致該導電元件17之體積縮小，而產生氣泡(Void)於該導電元件17中(IMC反應不完全)及該導電元件17碎裂(Crack)(如第1圖所示之應力集中處k)等問題，甚至斷裂延伸至其所結合之線路(如該封裝基板7之線路或導電矽穿孔100等)，因而降低該半導體封裝件1之信賴性及產品之良率。
再者，相同問題亦可能發生於該半導體晶片6與該線路重佈結構11之間的銲錫凸塊61上，致使該銲錫凸塊61與該線路重佈結構11之間出現破裂 之情形，如第1圖所示之應力集中處k，甚至斷裂延伸至其所結合之線路(如線路重佈結構11或半導體晶片6之電極墊60等)，因而降低該半導體封裝件1之信賴性及產品之良率。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種導電結構，係包括：第一導電層；凸塊體，係形成於該第一導電層之局部表面上；以及金屬輔助層，係形成於該第一導電層及/或該凸塊體上。
前述之導電結構中，該第一導電層係為鎳層。
前述之導電結構中，該凸塊體係為銅凸塊。
前述之導電結構中，該金屬輔助層係為金層。
本發明亦提供一種電子封裝件，係包括：第一基材，係配置有複數第一墊部，且令複數前述之導電結構藉該第一導電層結合至該第一墊部上；第二基材，係具有複數第二墊部；以及複數第二導電結構，係形成於該第二墊部上，且該第二導電結構於該第二墊部上依序形成有金屬柱、第二導電層、金屬層與銲錫層，以供該第二基材之銲錫層與該第一基材上之該導電結構之凸塊體及該金屬輔助層結合，而使該第一基材與該第二基材相堆疊。
前述之導電結構中，該第一墊部係為銅墊。
前述之電子封裝件中，該金屬柱係為銅柱。
前述之電子封裝件中，該第二導電層係為鎳層。
前述之電子封裝件中，該金屬層係為銅層。
前述之電子封裝件中，該凸塊體之體積及該金屬層之體積之總和與該銲錫層之體積的比例係為1：1.6~2.1。
前述之電子封裝件中，該凸塊體與該金屬層係未相互接觸。例如，該凸塊體與該金屬層之間的間隔距離係至多12微米。
本發明復提供一種電子封裝件之製法，係包括：提供一前述之電子封裝件；以及回銲該銲錫層，使該銲錫層、凸塊體及金屬層形成一強化體，以令該強化體、第一導電層、第二導電層及該金屬柱形成第三導電結構。
前述之製法中，該強化體係包含接觸該第一導電層之第一化合物及接觸該第二導電層之第二化合物。例如，該第一化合物係為四錫化三鎳，且該第二化合物係為五錫化六銅或五錫化六鎳。
前述之製法中，復包括形成絕緣層於該第一基材與第二基材之間，以包覆該第三導電結構。
由上可知，本發明之電子封裝件及其製法與導電結構中，主要藉由該凸塊體之設計以提供足夠的銅材進行IMC之反應，且藉由該金屬輔助層之設計，以增加銲錫層之附著性，使銲錫材產生側向收縮，故相較於習知技術，於回銲後，已完全反應出IMC，因而該第三導電結構之體積不會持續縮小，以有效避免於該強化體中產生氣泡及該第三導電結構碎裂等問題，進而有效提升該電子封裝件之信賴性及產品之良率。
1:半導體封裝件
10:矽中介板
10a:轉接側
10b:置晶側
100:導電矽穿孔
11:線路重佈結構
17:導電元件
2,2’,2”:電子封裝件
2a:第一導電結構
2b:第二導電結構
2c:第三導電結構
20:強化體
20a:第一化合物
20b:第二化合物
21:第一基材
210:第一墊部
22:第二基材
220:第二墊部
22a:第一導電層
22b:第二導電層
23:凸塊體
24:金屬輔助層
25:金屬柱
26:金屬層
27:銲錫層
28:絕緣層
6:半導體晶片
60:電極墊
61:銲錫凸塊
62:底膠
7:封裝基板
70:銲墊
8:封裝膠體
k:應力集中處
F,F’:作用方向
V,V1,V2:體積
t:間隔距離
D:寬度
第1圖係為習知半導體封裝件的剖視示意圖。
第2A至2D圖係為本發明之電子封裝件之製法之剖視示意圖。
第2D’圖係為第2D圖之另一實施例之剖視圖。
第3A至3E圖係為第2A圖之不同實施例之局部上視圖。
第4A至4C圖係為第2A圖之不同實施例之局部剖視圖。
第4D至4E圖係為第2A圖之不同實施例之局部側視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、“上”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，提供一第一基材21與一第二基材22，該第一基材21係具有至少一第一墊部210，且該第二基材22係具有至少一第二墊部220。
於本實施例中，該第一基材21及第二基材22係為基板結構及/或電子元件。例如，該基板結構係為具有核心層與線路結構之封裝基板(substrate) 或無核心層(coreless)之線路結構，該線路結構係於介電材上形成線路層(圖略)，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，且該電子元件係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。具體地，該介電材係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等，且該電子元件係為半導體晶片，其具有作用面與相對該作用面之非作用面，且該作用面上具有複數電極墊(如第一墊部210或第二墊部220)，使其藉由複數第一導電結構2a與複數第二導電結構2b以覆晶方式電性連接該基板結構之線路層(如第一墊部210或第二墊部220)，且可將凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)(未圖示)形成於該墊部與該導電結構之間。應可理解地，該基板結構亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(lead frame)或矽中介板(silicon interposer)等載件，並不限於上述。
再者，本實施例係將基板結構作為該第一基材21，而將電子元件作為該第二基材22，但於其它實施例中，只要是相覆晶堆疊之基材均可採用，並無特別限制。
又，所述之第一導電結構2a係於如銅墊之第一墊部210上依序形成有第一導電層22a、凸塊體23與金屬輔助層24，該第一導電層22a係大致佈滿該第一墊部210，且該凸塊體23係僅形成於該第一導電層22a之局部頂面上。例如，該第一導電層22a係為鎳層，且該凸塊體23係為銅凸塊，而該金屬輔助層24係為金層。具體地，該凸塊體23之形狀可依需求調整(如第3A至3E圖所示)，但不能全部覆蓋該第一導電層22a之頂面上，且該金屬輔助層24可依需求形成於該第 一導電層22a及/或該凸塊體23上，如第2A圖所示之完全覆蓋該第一導電層22a及該凸塊體23之上方或如第4A至4E圖所示之佈設方式，並無特別限制。
另外，所述之第二導電結構2b於如銅電極墊之第二墊部220上依序形成一金屬柱25、第二導電層22b、一金屬層26與銲錫層27。例如，該第二導電層22b係為鎳層，且該金屬柱25係為銅柱，而該金屬層26係為銅層。具體地，該第二導電結構2b係為晶片覆晶製程用之凸塊規格，且該銲錫層27包覆該金屬層26。
如第2B圖所示，進行覆晶接合作業，將該第二導電結構2b以其銲錫層27包覆該凸塊體23及該金屬輔助層24，以形成電子封裝件2”。
於本實施例中，該銲錫層27係接觸該第一導電層22a。例如，該銲錫層27覆蓋全部該第一導電層22a。
再者，該凸塊體23之體積V2及該金屬層26之體積V1之總和與該銲錫層27之體積V的比例係為1：1.6~2.1(若V2+V1之總和係為1單位體積，則V係為1.6至2.1單位體積)，如第2A圖所示，以利於後續完全反應成介面金屬共化物(Intermetallic Compound，簡稱IMC)。
又，該凸塊體23與該金屬層26並未相互接觸。例如，該凸塊體23與該金屬層26之間的間隔距離t係至多12微米(μm)，且經實驗後可得到較佳為5~12微米。
如第2C圖所示，進行覆晶回銲作業，以回銲該銲錫層27，使該銲錫層27及其內之凸塊體23與金屬層26形成一強化體20，以令該強化體20、第一導電層22a、第二導電層22b及該金屬柱25形成一第三導電結構2c。
於本實施例中，該強化體20係包含兩種介面金屬共化物(IMC)，其中一者係接觸該第一導電層22a之第一化合物20a，而另一者係接觸該第二導電層22b之第二化合物20b。例如，該第一化合物20a係為四錫化三鎳(Ni3Sn4)，且該第二化合物20b係為五錫化六銅(Cu6Sn5)或五錫化六鎳(Ni6Sn5)。具體地，於回銲該銲錫層27之過程中，藉由金材(金屬輔助層24)之外擴作用(如第2B圖所示之作用方向F)，致使銅凸塊(凸塊體23)朝側向(如第2B圖所示之作用方向F)反應形成IMC，而使銲錫材(銲錫層27)產生側向的收縮(如第2C圖所示之作用方向F’)，以令回銲後之導電結構2c之整體寬度D呈現一致，其中，該第一基材21之第一墊部210與第二基材22之第二墊部220藉由該第三導電結構2c相互電性連接。
再者，該金屬輔助層24於回銲後會殘存於該強化體20外，並以清潔液清除。
如第2D圖所示，於後續覆晶封裝作業中，可形成一絕緣層28於該第一基材21與第二基材22之間，以包覆該導電結構2c，至此即完成另一電子封裝件2之製作。
於本實施例中，該絕緣層28係為底膠材、聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體、封裝材(molding compound)或其它等適當材質。例如，該絕緣層28之製程可選擇填膠、液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成之。
再者，於其它實施例中，可依封裝規格之需求，如晶圓級封裝或晶片尺寸構裝(CSP)，移除該第一基材21，如第2D’圖所示之電子封裝件。
因此，本發明之製法中，主要藉由該凸塊體23之設計以提供足夠的銅材進行IMC之反應，且藉由該金屬輔助層24之設計，以增加銲錫層27之附著性，使銲錫材產生側向收縮(如第2C圖所示之作用方向F’)，故相較於習知技術，於後續形成該絕緣層28時，該IMC已完全反應，因而該第三導電結構2c之體積不會持續縮小，以有效避免於該強化體20中產生氣泡(Void)及該第三導電結構2c碎裂(Crack)等問題，甚至斷裂延伸至其所結合之線路(如該第一墊部210或第二墊部220)之問題，進而有效提升該電子封裝件2之信賴性及產品之良率。
本發明係提供一種第一導電結構2a，係包括：形成於第一墊部210上之第一導電層22a、僅形成於該第一導電層22a之局部表面上的凸塊體23、以及形成於該第一導電層22a及/或該凸塊體23上之金屬輔助層24。
於一實施例中，該第一墊部210係為銅墊。
於一實施例中，該第一導電層22a係為鎳層。
於一實施例中，該凸塊體23係為銅凸塊。
於一實施例中，該金屬輔助層24係為金層。
本發明亦提供一種電子封裝件2”，係包括：設有第一導電結構2a之第一基材21、具有第二墊部220之第二基材22、以及形成於該第二墊部220上之第二導電結構2b。
所述之第一基材21係配置有該第一墊部210，以結合該第一導電結構2a。
所述之第二導電結構2b於該第二墊部220上依序形成有金屬柱25、第二導電層22b、金屬層26與銲錫層27，以令該銲錫層27結合該第一導電結構2a之凸塊體23及該金屬輔助層24，使該第一基材21與該第二基材22相堆疊。
於一實施例中，該金屬柱25係為銅柱。
於一實施例中，該第二導電層22b係為鎳層。
於一實施例中，該金屬層26係為銅層。
於一實施例中，該凸塊體23之體積V2及該金屬層26之體積V1之總和與該銲錫層27之體積V的比例係為1：1.6~2.1。
於一實施例中，該凸塊體23與該金屬層26係未相互接觸。例如，該凸塊體23與該金屬層26之間的間隔距離t係至多12微米(即t≦12)。
綜上所述，本發明之電子封裝件及其製法與第一導電結構，係藉由該凸塊體與該金屬輔助層之設計，以於回銲該銲錫層後，已完全反應完成該IMC，因而該第三導電結構之體積不會持續縮小，因而有效避免於該強化體中產生氣泡及該第三導電結構碎裂等問題，故本發明之第一導電結構能有效提升該電子封裝件之信賴性及產品之良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2”:電子封裝件
2a:第一導電結構
2b:第二導電結構
21:第一基材
210:第一墊部
22:第二基材
220:第二墊部
22a:第一導電層
22b:第二導電層
23:凸塊體
24:金屬輔助層
25:金屬柱
26:金屬層
27:銲錫層
F:作用方向
t:間隔距離

Claims (17)

  1. 一種導電結構，係包括：
    第一導電層；
    凸塊體，係形成於該第一導電層之局部表面上；以及
    金屬輔助層，係形成於該凸塊體及/或該外露於該凸塊體之第一導電層上。
  2. 如申請專利範圍第1項所述之導電結構，其中，該第一導電層係為鎳層。
  3. 如申請專利範圍第1項所述之導電結構，其中，該凸塊體係為銅凸塊。
  4. 如申請專利範圍第1項所述之導電結構，其中，該金屬輔助層係為金層。
  5. 一種電子封裝件，係包括：
    第一基材，係配置有複數第一墊部，且令複數如申請專利範圍第1項所述之導電結構藉該第一導電層結合至該第一墊部上；
    第二基材，係具有複數第二墊部；以及
    複數第二導電結構，係形成於該第二墊部上，且該第二導電結構於該第二墊部上依序形成有金屬柱、第二導電層、金屬層與銲錫層，以供該第二基材之銲錫層與該第一基材上之該導電結構之凸塊體及該金屬輔助層結合，而使該第一基材與該第二基材相堆疊。
  6. 如申請專利範圍第5項所述之導電結構，其中，該第一墊部係為銅墊。
  7. 如申請專利範圍第5項所述之電子封裝件，其中，該金屬柱係為銅 柱。
  8. 如申請專利範圍第5項所述之電子封裝件，其中，該第二導電層係為鎳層。
  9. 如申請專利範圍第5項所述之電子封裝件，其中，該金屬層係為銅層。
  10. 如申請專利範圍第5項所述之電子封裝件，其中，該凸塊體之體積及該金屬層之體積之總和與該銲錫層之體積的比例係為1：1.6~2.1。
  11. 如申請專利範圍第5項所述之電子封裝件，其中，該凸塊體與該金屬層係未相互接觸。
  12. 如申請專利範圍第11項所述之電子封裝件，其中，該凸塊體與該金屬層之間的間隔距離係至多12微米。
  13. 一種電子封裝件之製法，係包括：
    提供一如申請專利範圍第5項所述之電子封裝件；以及
    回銲該銲錫層，使該銲錫層、凸塊體及金屬層形成一強化體，以令該強化體、第一導電層、第二導電層及該金屬柱形成第三導電結構。
  14. 如申請專利範圍第13項所述之電子封裝件之製法，其中，該強化體係包含接觸該第一導電層之第一化合物及接觸該第二導電層之第二化合物。
  15. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該第一化合物係為四錫化三鎳。
  16. 如申請專利範圍第14項所述之電子封裝件之製法，其中，該第二化合物係為五錫化六銅或五錫化六鎳。
  17. 如申請專利範圍第13項所述之電子封裝件之製法，復包括形成絕 緣層於該第一基材與第二基材之間，以包覆該第三導電結構。
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