CN101924088A - 一种集成电路结构 - Google Patents

一种集成电路结构 Download PDF

Info

Publication number
CN101924088A
CN101924088A CN2010101417076A CN201010141707A CN101924088A CN 101924088 A CN101924088 A CN 101924088A CN 2010101417076 A CN2010101417076 A CN 2010101417076A CN 201010141707 A CN201010141707 A CN 201010141707A CN 101924088 A CN101924088 A CN 101924088A
Authority
CN
China
Prior art keywords
projection
integrated circuit
circuit structure
soldering projection
soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010101417076A
Other languages
English (en)
Other versions
CN101924088B (zh
Inventor
李明机
李建勋
余振华
郑心圃
古进誉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101924088A publication Critical patent/CN101924088A/zh
Application granted granted Critical
Publication of CN101924088B publication Critical patent/CN101924088B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明为一种集成电路结构，包含半导体基板、聚亚酰胺层、凸块下金属层、第一焊接凸块以及第二焊接凸块，其中聚亚酰胺层位于半导体基板之上；凸块下金属层包含第一区块与第二区块，其中第一区块位于聚亚酰胺层之上，第二区块与聚亚酰胺层位于同一平面；第一焊接凸块与第二焊接凸块形成于聚亚酰胺层之上，且第一焊接凸块与第二焊接凸块两者的间距不超过150微米，其中凸块下金属层的第一宽度为前述间距的一半再加上一大于5微米的长度。

Description

一种集成电路结构
技术领域
本发明是关于一种集成电路，且特别是关于集成电路结构与集成电路接合结构的制作方式。
背景技术
集成电路(IC)芯片通常会电性连接于封装结构中的封装基板，用以提供外部信号的交换。覆晶接合结构(flip-chip)是最常使用的接合结构，因为它提供了最坚固的内连线结构。当覆晶结构使用如环氧化物(epoxy)等胶粘剂来进行底胶填充(underfill)时，此覆晶结构即可承受严格的耐久测试。此外，覆晶接合结构是一种低成本的内连线结构，适合运用于大量自动化生产。
覆晶结构一般是将焊接凸块(solder bump)置放在硅芯片上，在已知的内连线结构中，首先形成介电层于硅基板之上，并在介电层中形成金属线与介层窗(via)。随后，金属垫片(metal pad)形成于介电层之上，然后再将保护层形成于金属垫片上，此保护层具有一位于介电层内的孔洞用以露出金属垫片，接着再形成聚亚酰胺缓冲层(polyimide layer)。另外，凸块下金属层(under-bump-metallurgy，UBM)、金属钛层、铜镀层(plated copper layer)与镍镀层(plated nickel layer)将于焊接凸块形成后，形成于上述孔洞内。
以往，包含铅与锡的共熔(eutectic)焊接材料应用于焊接凸块，通常所使用的含铅共熔焊接材料是由约63％的锡与约37％的铅所形成，此组合可使焊接材料具有适合的熔化温度(melting temperature)与低电阻系数。然而，铅是一种有毒材料，无论法律或工业上的需求，均要求使用无铅(lead-free)焊接凸块，因此，电子连接产业供应链的厂商们，均积极寻找可替代的共熔焊接材料，遗憾的是现有的无铅焊接材料，如锡银(Sn-Ag)与锡银铜(Sn-Ag-Cu)，本质均较脆且有易碎裂的问题，更甚者，无铅凸块本质坚硬，将会导致无铅凸块于介电层内脱层与碎裂。
凸块于介电层内的碎裂与脱层主要是由应力所造成，而在封装结构中的凸块材料间热膨胀系数(coefficient of thermal expansion，CTE)的不匹配是导致此应力形成的主要原因之一。举例而言，硅基板的典型热膨胀系数约为3ppm/℃，低介电常数(low-k)介电层的典型热膨胀系数约为20ppm/℃，而封装基板的典型热膨胀系数约为17ppm/℃，当温度发生变化时，上述结构间热膨胀系数显著的差异，将导致应力的产生。
在使用先进技术所制成的集成电路中，在低介电常数材料中的凸块碎裂与脱层现象皆变得更加剧烈。举例而言，在40纳米与40纳米以下的技术中，凸块于低介电常数介电层中的碎裂与脱层现象均过于剧烈，以致于各个集成电路甚至无法通过可靠度测试，而上述现象限制了极低介电常数(extra low-k，ELK)与超低介电常数(ultra low-k，ULK)介电材料于介电层中的使用。因此，目前为止尚未出现采用极低介电常数/超低介电常数介电材料的介电层与无铅焊接材料的组合的集成电路，能够成功应用40纳米与40纳米以下的技术来制造的例子。
发明内容
根据本发明的一实施例，本发明提供一种集成电路结构，包含一半导体基板、一聚亚酰胺层、一凸块下金属层、一第一焊接凸块以及一第二焊接凸块。其中聚亚酰胺层位于半导体基板之上；凸块下金属层包含第一区块与第二区块，其中第一区块位于聚亚酰胺层之上，而第二区块与聚亚酰胺层位于同一平面；第一焊接凸块与第二焊接凸块形成于聚亚酰胺层之上，且第一焊接凸块与第二焊接凸块两者的间距不超过150微米，其中凸块下金属层的第一宽度为前述间距的一半再加上一大于5微米的长度。
根据本发明的另一实施例，本发明提供一种集成电路结构，包含：一半导体基板；一金属垫片，位于该半导体基板之上；一保护层，至少部分该保护层位于该金属垫片之上，其中该金属垫片露出于第一孔洞；一聚亚酰胺层，位于该保护层之上并延伸进该第一孔洞，其中该聚亚酰胺层包含第二孔洞，该第二孔洞的宽度小于40微米，且该金属垫片露出于该第二孔洞；一凸块下金属层，包含第一区块与第二区块，其中该第一区块位于该第二孔洞内，该第二区块位于该聚亚酰胺层之上，其中该凸块下金属层包含：一种晶层，位于该金属垫片之上并接触该金属垫片；一铜镀层，位于一金属钛层之上，且该铜镀层的厚度小于5微米；一镍镀层，位于该铜镀层之上，且该镍镀层的厚度小于3微米；一第一焊接凸块，位于该镍镀层之上并接触该镍镀层；以及一第二焊接凸块，与该第一焊接凸块相邻，且该第一焊接凸块与该第二焊接凸块两者的间距不超过150微米，其中该凸块下金属层的第一宽度为该间距的一半再加上一大于5微米的长度，且该第一焊接凸块与该第二焊接凸块两者的凸块高度为该间距的一半再加上一介于5微米和10微米间的长度。
本发明的其它实施例亦将揭露于发明说明中，这些实施例所揭露本发明的优点包含改善集成电路结构的可靠性以及提升制造良率。
附图说明
为让本发明的上述和其它目的、特征、优点与实施例能更明显易懂，所附附图的说明如下：
图1是绘示依照本发明一实施方式的一种覆晶封装结构的剖面图。
【主要组件符号说明】
20：芯片/晶圆
22：基板
24：主动电路
26：内连线结构
28：介电层
30：金属线
32：介电窗
34：保护层
38：金属垫片
39：凸块下金属层
40：金属钛层
42：缓冲层
44：金属铜层
46：铜镀层
48：镍镀层
50：第一焊接凸块
50’：第二焊接凸块
54：底部填胶
60：金属线
120：封装基板
122：介电层
124：阻焊剂开口
126：金属垫片
具体实施方式
图1为本发明实施例的部分芯片(或晶圆)20的剖面图，其包含一基板22，且有一主动电路24形成于基板22上，芯片/晶圆20透过第一焊接凸块50与第二焊接凸块50’以与封装基板120结合，基板22可为普遍为业界所采用的半导体材料如硅、锗化硅或其它类似材料所形成的半导体基板。以长方形符号表示的主动电路24形成于基板22的表面上，此主动电路24可包含互补型金属氧化物半导体(CMOS)晶体管、电阻、电容以及类似电子组件。内连线结构26形成于主动电路24之上，用以连接主动电路24内的组件，并连接主动电路24和覆盖在主动电路24之上的第一焊接凸块50以及第二焊接凸块50’。内连线结构26包含多个金属化层，其中这些金属化层包含介电层28，这些介电层28内包含金属线30与介电窗32。此外，内连线结构26包含一具有金属线的顶端金属化层，此顶端金属化层即为紧接于金属垫片38之下的金属化层。在本发明一实施例中，位于顶端金属化层内的金属线60的厚度为T7，此厚度T7大于约0.9微米，且金属线60与金属垫片38可透过介层窗来连接。
在本发明一实施例中，介电层28是以具有介电常数(k值)介于约2.9和约3.8之间的低介电常数介电材料所形成，因此，介电层28亦为低介电常数介电层；在本发明另一实施例中，介电层28可以具有介电常数值小于约2.5的超低介电常数介电材料所形成，因此，介电层28亦为超低介电常数介电层；在本发明又一实施例中，介电层28可以具有介电常数值介于约2.5和约2.9之间的极低介电常数介电材料所形成，因此，介电层28亦为极低介电常数介电层。随着介电常数值的递减，介电层28亦变得愈加易碎，也更有可能导致脱层与碎裂。
保护层34形成于内连线结构26之上，保护层34可由介电材料所形成，如氧化硅、氮化硅、未掺杂硅玻璃(un-doped silicate glass，USG)、氮氧化硅或其组合，保护层34亦可为上述介电材料所形成的多层结构。金属垫片38形成于保护层34内。在本发明一实施例中，保护层34包含两层结构(图中未显示)，此两层结构为保护层1与保护层2，其中保护层2位于保护层1之上，前述金属垫片38位于保护层1内并较保护层2低，且金属垫片38露出于保护层34上方部分(如保护层2)的孔洞。金属垫片38可由铝所形成，因此金属垫片38可被视为铝垫片38，然而金属垫片38尚可由其它金属材料所形成或包含其它金属材料，如铜、银、金、镍、钨或其合金，金属垫片38亦可为上述材料所形成的多层结构。此外，金属垫片38可透过金属垫片38之下的内连线结构26电性连接于主动电路24。在金属垫片38形成时，与金属垫片38位于相同水平面上的再分配线(redistribution lines，RDLs)亦可使用相同制程来形成。再者，金属垫片38的厚度为T1，在本发明一实施例中，此厚度T1介于约1.4微米和约15微米之间。
第一孔洞形成于保护层34内，且金属垫片38露出于第一孔洞，此外，位于保护层34内的第一孔洞的宽度标示为W1。在本发明一实施例中，缓冲层42形成于保护层34之上，其中部分的缓冲层42延伸进第一孔洞内，而其它部分的缓冲层42位于保护层34之上。此外，缓冲层42可由聚亚酰胺(polyimide)所形成，然而亦可由其它较不坚硬的介电材料所形成。第二孔洞形成于缓冲层42内，位于缓冲层42内的第二孔洞的宽度标示为W2，在本发明一实施例中，宽度W2小于40微米。在本发明一实施例中，缓冲层42的厚度是以T2表示，此厚度T2大于5微米。
接着，凸块下金属层(under-bump metallurgy，UBM)39形成于缓冲层42之上，其中部分的凸块下金属层39位于第二孔洞内且电性连接于金属垫片38。在本发明一实施例中，凸块下金属层39包含多层状结构，如种晶层、铜镀层46以及镍镀层48，其中前述种晶层包含金属钛层40与金属铜层44(因此种晶层亦可被视为种晶层40/44)，在本发明其它实施例中，凸块下金属层39可包含其它金属，如金。此外，凸块下金属层39的宽度为W3，此宽度W3与第一焊接凸块50以及第二焊接凸块50’的间距P相关，在本发明一实施例中，宽度W3可表示为0.5P+M，其中M值大于0.5微米。再者，位于缓冲层42内第二孔洞的宽度W2可少于凸块下金属层39的宽度W3的50％，或介于凸块下金属层39的宽度W3的约35％和约50％之间。
金属钛层40的厚度可为T3，且可例如以物理气相沉积法(physical vapordeposition，PVD)形成。而金属铜层44的厚度可为T4，且可例如以物理气相沉积法形成。此外，凸块下金属层39可进一步包含位于种晶层44之上的铜镀层46(厚度为T5)以及位于铜镀层46之上的镍镀层48(厚度为T6)。种晶层40/44、铜镀层46与镍镀层48可以毯覆式沉积法(blanket)形成，之后可使用同一光罩与光阻剂以光微影术形成所需图形。在本发明一实施例中，厚度T3为约0.1微米，厚度T4为约0.5微米，厚度T5小于5微米，厚度T6小于3微米。
接着，第一焊接凸块50形成于凸块下金属层39之上并接触凸块下金属层39，第一焊接凸块50可以无铅焊接材料所形成，此无铅焊接材料包含如锡银(SnAg)、锡银铜(SnAgCu)或类似材料。此外，在第一焊接凸块50中银的重量百分比可介于约1％和约2.2％之间。在第一焊接凸块50经由回焊(reflow)后，第一焊接凸块50的外型是形成球状，其中第一焊接凸块50下方部分的大小与形状与多个金属层40/44/46/48的大小与形状相符。再者，第一焊接凸块50与相邻的第二焊接凸块50’两者的间距标示为间距P，间距P以不超过150微米为佳，其中第二焊接凸块50’大体上与第一焊接凸块50为相同的结构。在本发明一实施例中，凸块高度H可表示为0.5P+N，其中N值大于5微米，且N值可介于5微米和约10微米之间。
芯片/晶圆20透过第一焊接凸块50与第二焊接凸块50’以与封装基板120结合，封装基板120可包含具有阻焊剂开口(solder resist opening，SRO)124的介电层122，此外，金属垫片126露出于阻焊剂开口124。当芯片/晶圆20与封装基板120结合时，焊接凸块50经回焊而与金属垫片126结合。回焊之后，底部填胶54可用以填入芯片/晶圆20与封装基板120之间的间隙。在本发明一实施例中，底部填胶54的玻璃转换温度(glass transition temperature，Tg)高于摄氏70度，或高于摄氏约85度，抑或介于摄氏约85度和约120度之间。
由实验结果可知，如图1中显示的结构的可靠度易受到结构参数的影响，此结构参数包含结构尺寸，如厚度T1至厚度T7、间距P、宽度W1至宽度W3、凸块高度H以及底部填胶的玻璃转换温度Tg。若使用已知的参数值(其中已知参数值被使用在以氧化硅所形成的介电层28的结构中)，如图1所示的结果构造将无法通过可靠度测试，且此结果结构将于约200至约500次热循环后产生损坏。此外，上述采用已知参数值的结果结构具有低制造良率。
实验结果亦揭露只要每一个前述的参数，如厚度T1至厚度T7、间距P、宽度W1至宽度W3、凸块高度H以及底部填胶的玻璃转换温度Tg，皆能够限定在一小范围内(如前所述)，图1所示的结构即可通过可靠度测试，否则无铅焊接凸块50将会碎裂，且有极低介电常数/超低介电常数介电材料的介电层28将会脱层。此外，本发明所提供各参数的理想范围必须联合使用，若仅有部分参数在所需范围内，而其它参数未在所需范围内，则此结果构造将无法通过可靠度测试。当所有参数均在所需范围内时，图1所示的结果结构可承受超过1000次的热循环，若部分参数不在所需范围内时，则仅能承受约200至约500次热循环。
虽然本发明已以实施方式揭露如上，然其并非用以限定本发明，任何熟悉此技艺者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求书所界定的范围为准。

Claims (18)

1.一种集成电路结构，其特征在于，包含：
一半导体基板；
一聚亚酰胺层，位于该半导体基板之上；
一凸块下金属层，该凸块下金属层包含一第一区块与一第二区块，其中该第一区块位于该聚亚酰胺层之上，该第二区块与该聚亚酰胺层位于同一平面；以及
一第一焊接凸块与一第二焊接凸块，位于该凸块下金属层之上，该第一焊接凸块与该第二焊接凸块两者的间距不超过150微米，其中该凸块下金属层的第一宽度为该间距的一半再加上一大于5微米的长度。
2.根据权利要求1所述的集成电路结构，其特征在于，该第一焊接凸块与该第二焊接凸块的凸块高度为该间距的一半再加上一介于5微米至10微米间的长度。
3.根据权利要求1所述的集成电路结构，其特征在于，该聚亚酰胺层包含一孔洞，该孔洞具有第二宽度且该凸块下金属层延伸进该孔洞，其中该第二宽度介于35％的该第一宽度和50％的该第一宽度之间。
4.根据权利要求1所述的集成电路结构，其特征在于，该第一焊接凸块与该第二焊接凸块包含银，且该第一焊接凸块以及该第二焊接凸块中银的重量百分比均介于1％和2.2％之间。
5.根据权利要求1所述的集成电路结构，其特征在于，还包含：
多个介电层，位于该半导体基板和该凸块下金属层之间，其中该些介电层是由具有介电常数值介于2.5和2.9之间的极低介电常数介电材料所形成。
6.根据权利要求1所述的集成电路结构，其特征在于，还包含：
多个介电层，位于该半导体基板与该凸块下金属层之间，其中该些介电层是由具有介电常数值小于2.5的超低介电常数介电材料所形成。
7.根据权利要求1所述的集成电路结构，其特征在于，还包含：
一保护层，位于该聚亚酰胺层之下；以及
一金属垫片，位于该保护层之下并透过一孔洞电性连接于该凸块下金属层。
8.根据权利要求1所述的集成电路结构，其特征在于，该凸块下金属层包含：
一种晶层；
一铜镀层，位于该种晶层之上并接触该种晶层，且该铜镀层的厚度小于5微米；
一镍镀层，位于该铜镀层之上并接触该铜镀层，且该镍镀层的厚度小于3微米。
9.根据权利要求1所述的集成电路结构，其特征在于，还包含：
一底部填胶，位于该第一焊接凸块与该第二焊接凸块之间，其中该底部填胶的玻璃转换温度介于摄氏85度和120度之间。
10.根据权利要求1所述的集成电路结构，其特征在于，还包含：
一封装基板，与该第一焊接凸块和该第二焊接凸块连接。
11.一种集成电路结构，其特征在于，包含：
一半导体基板；
一金属垫片，位于该半导体基板之上；
一保护层，至少部分该保护层位于该金属垫片之上，其中该金属垫片露出于第一孔洞；
一聚亚酰胺层，位于该保护层之上并延伸进该第一孔洞，其中该聚亚酰胺层包含第二孔洞，该第二孔洞的宽度小于40微米，且该金属垫片露出于该第二孔洞；
一凸块下金属层，包含第一区块与第二区块，其中该第一区块位于该第二孔洞内，该第二区块位于该聚亚酰胺层之上，其中该凸块下金属层包含：
一种晶层，位于该金属垫片之上并接触该金属垫片；
一铜镀层，位于一金属钛层之上，且该铜镀层的厚度小于5微米；
一镍镀层，位于该铜镀层之上，且该镍镀层的厚度小于3微米；
一第一焊接凸块，位于该镍镀层之上并接触该镍镀层；以及
一第二焊接凸块，与该第一焊接凸块相邻，且该第一焊接凸块与该第二焊接凸块两者的间距不超过150微米，其中该凸块下金属层的第一宽度为该间距的一半再加上一大于5微米的长度，且该第一焊接凸块与该第二焊接凸块两者的凸块高度为该间距的一半再加上一介于5微米和10微米间的长度。
12.根据权利要求11所述的集成电路结构，其特征在于，该第二孔洞具有第二宽度，且该第二宽度介于35％的该第一宽度和50％的该第一宽度之间。
13.根据权利要求11所述的集成电路结构，其特征在于，该第一焊接凸块与该第二焊接凸块包含银，且该第一焊接凸块以及该第二焊接凸块中银的重量百分比均介于1％和2.2％之间。
14.根据权利要求11所述的集成电路结构，其特征在于，还包含：
多个介电层，位于该半导体基板与该凸块下金属层之间，其中该些介电层是由具有介电常数值介于2.5和2.9之间的极低介电常数介电材料所形成。
15.根据权利要求11所述的集成电路结构，其特征在于，还包含：
多个介电层，位于该半导体基板与该凸块下金属层之间，其中该些介电层是由具有介电常数值小于2.5的超低介电常数介电材料所形成。
16.根据权利要求11所述的集成电路结构，其特征在于，还包含：
一底部填胶，介于该第一焊接凸块与该第二焊接凸块之间，其中该底部填胶的玻璃转换温度介于摄氏85度和120度之间。
17.根据权利要求11所述的集成电路结构，其特征在于，还包含：
一封装基板，与该第一焊接凸块和该第二焊接凸块连接。
18.根据权利要求11所述的集成电路结构，其特征在于，该保护层包含选自于主要由氮化硅、氧化硅、氮氧化硅及其组合所组成的群组的材料。
CN2010101417076A 2009-06-16 2010-03-29 一种集成电路结构 Active CN101924088B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US18754209P 2009-06-16 2009-06-16
US61/187,542 2009-06-16
US12/537,001 US8169076B2 (en) 2009-06-16 2009-08-06 Interconnect structures having lead-free solder bumps
US12/537,001 2009-08-06

Publications (2)

Publication Number Publication Date
CN101924088A true CN101924088A (zh) 2010-12-22
CN101924088B CN101924088B (zh) 2012-07-04

Family

ID=43305728

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010101417076A Active CN101924088B (zh) 2009-06-16 2010-03-29 一种集成电路结构

Country Status (2)

Country Link
US (1) US8169076B2 (zh)
CN (1) CN101924088B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623429A (zh) * 2012-04-11 2012-08-01 日月光半导体制造股份有限公司 封装载体结构
CN103367301A (zh) * 2012-03-29 2013-10-23 台湾积体电路制造股份有限公司 集成电路器件中的细长凸块
CN104253054A (zh) * 2013-06-26 2014-12-31 索尼公司 半导体装置
CN108122933A (zh) * 2016-11-28 2018-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及制备方法、电子装置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법
US8698308B2 (en) * 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
US9806042B2 (en) 2012-04-16 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strain reduced structure for IC packaging
US8653662B2 (en) * 2012-05-02 2014-02-18 International Business Machines Corporation Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits
US8759210B2 (en) * 2012-07-19 2014-06-24 International Business Machines Corporation Control of silver in C4 metallurgy with plating process
US8742578B2 (en) 2012-07-19 2014-06-03 International Business Machines Corporation Solder volume compensation with C4 process
KR101488580B1 (ko) * 2013-01-11 2015-02-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 이에 따른 반도체 패키지
US9466547B1 (en) * 2015-06-09 2016-10-11 Globalfoundries Inc. Passivation layer topography
WO2020033632A2 (en) * 2018-08-08 2020-02-13 Kuprion Inc. Electronic assemblies employing copper in multiple locations

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220199A (en) * 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
CN101174601A (zh) * 2006-11-03 2008-05-07 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531417B2 (en) * 1998-12-21 2009-05-12 Megica Corporation High performance system-on-chip passive device using post passivation process
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TWI231555B (en) * 2003-06-30 2005-04-21 Advanced Semiconductor Eng Wafer level package and fabrication process thereof
TWI228306B (en) * 2003-07-21 2005-02-21 Advanced Semiconductor Eng Method for forming a bump protective collar
CN100501955C (zh) * 2004-03-22 2009-06-17 株式会社田村制作所 焊料组成物和使用该焊料组成物的隆起形成方法
TWI259572B (en) * 2004-09-07 2006-08-01 Siliconware Precision Industries Co Ltd Bump structure of semiconductor package and fabrication method thereof
US7355282B2 (en) * 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US7807506B2 (en) * 2006-02-03 2010-10-05 Infineon Technologies Ag Microelectromechanical semiconductor component with cavity structure and method for producing the same
US7656042B2 (en) * 2006-03-29 2010-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Stratified underfill in an IC package
TWI370515B (en) * 2006-09-29 2012-08-11 Megica Corp Circuit component
US7838954B2 (en) * 2008-01-16 2010-11-23 International Business Machines Corporation Semiconductor structure with solder bumps
DE102008044984A1 (de) * 2008-08-29 2010-07-15 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Verspannungsrelaxationsspalte zur Verbesserung der Chipgehäusewechselwirkungsstabilität
US7892963B2 (en) * 2009-04-24 2011-02-22 Globalfoundries Singapore Pte. Ltd. Integrated circuit packaging system and method of manufacture thereof
TWI412107B (zh) * 2009-10-02 2013-10-11 Ind Tech Res Inst 凸塊結構、晶片封裝結構及該凸塊結構之製備方法
US8035218B2 (en) * 2009-11-03 2011-10-11 Intel Corporation Microelectronic package and method of manufacturing same
US20110186989A1 (en) * 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220199A (en) * 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
CN101174601A (zh) * 2006-11-03 2008-05-07 台湾积体电路制造股份有限公司 半导体装置及其制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367301A (zh) * 2012-03-29 2013-10-23 台湾积体电路制造股份有限公司 集成电路器件中的细长凸块
CN103367301B (zh) * 2012-03-29 2017-04-26 台湾积体电路制造股份有限公司 集成电路器件中的细长凸块
CN102623429A (zh) * 2012-04-11 2012-08-01 日月光半导体制造股份有限公司 封装载体结构
CN104253054A (zh) * 2013-06-26 2014-12-31 索尼公司 半导体装置
CN104253054B (zh) * 2013-06-26 2019-04-05 索尼公司 半导体装置
CN108122933A (zh) * 2016-11-28 2018-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及制备方法、电子装置

Also Published As

Publication number Publication date
CN101924088B (zh) 2012-07-04
US8169076B2 (en) 2012-05-01
US20100314756A1 (en) 2010-12-16

Similar Documents

Publication Publication Date Title
CN101924088B (zh) 一种集成电路结构
US10734347B2 (en) Dummy flip chip bumps for reducing stress
US9093314B2 (en) Copper bump structures having sidewall protection layers
US7361990B2 (en) Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads
CN102054811B (zh) 集成电路结构
US8193639B2 (en) Dummy metal design for packaging structures
CN101894814B (zh) 焊料凸块ubm结构
KR101120769B1 (ko) 반도체 장치들에서 솔더 범프 연결들을 개선하기 위한 구조들 및 방법들
US10037962B2 (en) Ball height control in bonding process
CN103681615A (zh) 互连结构及其形成方法
US20110101519A1 (en) Robust Joint Structure for Flip-Chip Bonding
US10050000B2 (en) Bump-on-trace structures with high assembly yield
CN102064136B (zh) 集成电路结构
US20240113060A1 (en) Heterogeneous solder bump structure
TWI483366B (zh) 凸塊結構與封裝結構

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant