CN104253054A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN104253054A
CN104253054A CN201410181198.8A CN201410181198A CN104253054A CN 104253054 A CN104253054 A CN 104253054A CN 201410181198 A CN201410181198 A CN 201410181198A CN 104253054 A CN104253054 A CN 104253054A
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China
Prior art keywords
semiconductor element
substrate
semiconductor device
layer
reflection layer
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CN201410181198.8A
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CN104253054B (zh
Inventor
畑田出穂
大鸟居英
冈修一
柳川周作
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Sony Corp
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Sony Corp
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Publication of CN104253054A publication Critical patent/CN104253054A/zh
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Abstract

本发明涉及半导体装置,该半导体装置包括:基底基板,在所述基底基板上布置有基板电极;以及半导体元件,所述半导体元件包括通过焊料与所述基板电极电连接的芯片电极,且在所述半导体元件的下表面侧上形成有光吸收层。根据本发明,可利用激光束来移除半导体元件,且无需覆盖光吸收材料。这样,在不增加制造成本的情况下,可从半导体装置中仅移除失效半导体元件。

Description

半导体装置
技术领域
本发明涉及具有安装在基板上的半导体元件的半导体装置。
背景技术
在基板上以高密度集成有半导体元件的半导体装置中,当发现半导体元件失效时,应考虑将该半导体元件从半导体装置中移除。
针对从半导体装置中移除半导体元件的方法,已经提出了一些方案。例如,在日本未审查专利申请2003-204150中,提出了利用在半导体元件上吹送加热气体的方法来移除半导体元件(日本未审查专利申请2003-204150中的电子部件41)的方案。另外,在日本未审查专利申请2004-273795中,提出了通过在失效的半导体元件上覆盖光吸收材料并在其上照射激光来移除该半导体元件(日本未审查专利申请2004-273795中的电子部件8)的方法。
然而,在日本未审查专利申请.2003-204150中,存在着加热气体影响安装在失效半导体元件周围的正常半导体元件的可能,因此将引起正常半导体元件失效,或造成正常半导体元件被移除。
此外,在日本未审查专利申请2004-273795中,必须包括在失效半导体元件上覆盖光吸收材料的步骤,因此增加了成本。
发明内容
这里,在本发明中,期望在不增加制造成本的条件下从半导体装置中仅移除失效半导体元件。
根据本发明的实施例的半导体装置包括:基底基板,在所述基底基板上布置有基板电极;以及半导体元件,所述半导体元件包括通过焊料与所述基板电极电连接的芯片电极,且在所述半导体元件的下表面侧上形成有光吸收层。
由于在半导体元件中形成了光吸收层,因此可利用激光束来移除半导体元件,且无需覆盖光吸收材料。
在根据上述本发明的实施例的半导体装置中,可在所述半导体元件的下表面侧上形成有与所述光吸收层接触的热扩散层。
由于形成了与光吸收层接触的热扩散层,可与常规相比将在光吸收层处吸收的热量更多地传递到焊料。
在根据上述本发明的实施例的半导体装置中,可在所述基底基板的上表面侧上形成有光反射层。
因此,通过来自光反射层的反射光来加热焊料。
在根据上述本发明的实施例的半导体装置中,所述光反射层可与所述基板电极电连接。
因此,易于将因激光束的照射而在光反射层处产生的热量传导至焊料。
在根据上述本发明的实施例的半导体装置中,可在所述光反射层的下表面侧上形成有与所述光反射层接触的保护层。
因此,因激光束的照射而在光反射层处产生的热量很难传导至保护层下面的层。
在根据上述本发明的实施例的半导体装置中,可所述半导体元件在下表面侧上具有未形成有所述光吸收层的空隙部,并且可在所述基板的上表面侧中的与所述空隙部相对的一部分上形成有所述光反射层。
因此,穿过半导体元件的激光束被基底基板上的光反射层反射,从而该激光束不直接照射位于光反射层下方的层。
在根据上述本发明的实施例的半导体装置中,所述光吸收层可形成为包括Ti、Ni、Sn、Pt以及W中的任一种。
因此,该光吸收层易于吸收激光束。
在根据上述本发明的实施例的半导体装置中,所述热扩散层形成为包括Al、Cu、Au以及Ag中的任一种。
因此,通过热扩散层可容易地传导在光吸收层处吸收的热量。
在根据上述本发明的实施例的半导体装置中,所述光反射层形成为包括Al、Cu、Au以及Ag中的任一种。
因此,光反射层可容易地反射激光束。
在根据上述本发明的实施例的半导体装置中,所述保护层形成为包括Ti、Ni、Pt、Sn以及W中的任一种。
因此,因照射激光束而在光反射层13处产生的热量难以传递至位于保护层下方的层。
根据本发明,可利用激光束来移除半导体元件,且无需覆盖光吸收材料。这样,在不增加制造成本的情况下,可从半导体装置中仅移除失效半导体元件。
附图说明
图1与图2A至15一起图示了本发明的实施例,且图1是图示了整个半导体装置的立体图;
图2A和2B是图示了将失效半导体元件处于从半导体装置中移除的状态的放大立体图;
图3是图示根据第一实施例的半导体装置的一部分的放大示意剖面图;
图4是图示第一实施例中的从移除器件照射激光束的状态的放大示意剖面图;
图5是图示第一实施例中的移除器件吸附半导体元件的状态的放大示意剖面图;
图6是图示根据第二实施例的半导体装置的一部分的放大示意剖面图;
图7是图示第二实施例中的从移除器件照射激光束的状态的放大示意剖面图;
图8是图示根据第三实施例的半导体装置的一部分的放大示意剖面图;
图9A和9B与图10至12一起图示了芯片UBM层的布置图案和基板UBM层布置图案的示例,且图9A和9B是图示第一布置图案的放大立体图;
图10是图示第二布置图案的放大立体图;
图11是图示第三布置图案的放大立体图;
图12是图示第四布置图案的放大立体图;
图13是图示根据半导体元件形状的变化示例的放大示意平面图;
图14是图示在半导体元件的下表面侧上没有形成空隙部的示例的放大示意剖视图;以及
图15是图示在基板的上表面侧上处没有形成空隙部的示例的放大示意剖视图。
具体实施方式
下面,将参考附图来描述用于实现根据本发明的半导体装置的实施例。
下面,将描述本发明被应用于以高密度集成有半导体元件的半导体装置的示例。同时,本发明可广泛应用于具有安装在基板上的半导体元件的半导体装置。
将以如下顺序来描述实施例。
1.半导体装置的整体结构
2.移除半导体元件的方法
3.根据第一实施例的半导体装置的构造
4.在移除半导体元件时的操作及其效果
5.第二实施例
6.第三实施例
7.芯片UBM层和基板UBM层的布置图案
7-1.第一布置图案
7-2.第二布置图案
7-3.第三布置图案
7-4.第四布置图案
7-5.其他布置图案
8.关于半导体元件形状的变化示例
9.没有空隙部的示例
10.概述
1.半导体装置的整体结构
如图1所示,半导体装置1包括基底基板2和多个利用焊料等安装在基底基板2上的半导体元件3,3,…。
半导体元件3,3,…以数十um至数百um的间距安装在基底基板2上,并且以相对高的密度安装。
2.移除半导体元件的方法
这里,在制造半导体装置(例如,上述半导体装置)1的情况下,在将半导体元件3,3,…安装在基底基板2上之后的检测过程中,可发现失效的半导体元件3。此时,由于半导体元件3,3,…按照上述方式以相对高的密度安装,因此存在着难以仅移除失效半导体元件3的情况。
因此,在下文所描述的实施例中,采用了例如图2A和2B所示的使用移除器件200的方法,以作为从基底基板2移除失效半导体元件3的方法。移除器件200配置成使得能够照射激光束以吸附部件。
如图2A所示,在被设定为移除目标的半导体元件3中通过移除器件200从上部照射激光束,因此使用于将半导体元件3结合至基底基板2的焊料溶解。此时,选取从移除器件200中发射出的激光束的波长,该波长穿过半导体元件3的基板部6。例如,在由硅(Si)形成基板部6的情况下,选取波长长于1nm的激光束,而在由砷化镓(GaAs)形成基板部6的情况下,则选取波长长于900nm的激光束。
之后,如图2B所示,半导体元件3和焊料由于被移除器件200吸附而与基底基板2分离。
因此,尽管半导体元件3,3,…以相对高的密度安装,但仍可将失效的半导体元件3从基底基板2中移除。
3.根据第一实施例的半导体装置的构造
在上述移除方法的前提下,将结合图3描述根据第一实施例的半导体装置1的详细构造。
基底基板2包括基板部4和多个形成在基板部4的上表面侧上并用于与焊料100的电连接的基板电极5,5,…。基板电极5由如下金属形成,该金属的主要成分是诸如铜(Cu)之类的导体。
半导体元件3包括基板部6、形成在基板部6的下表面侧上的多个芯片电极7,7,…,以及芯片凸点下金属(UBM)层8,8,…。
芯片电极7,7,…通过芯片UBM层8,8,…分别与焊料100电连接。此外,芯片电极7由如下金属形成,该金属的主要成分是诸如铜(Cu)之类的导体。
芯片UBM层8为由三层形成的多层结构,其从上到下的顺序依次包括光吸收层9、热扩散层10以及光吸收层9。
另外,虽然芯片UBM层8,8,…分别与芯片电极7,7,…结合,但是为了避免所有芯片电极7,7,…直接彼此导通,在至少一组芯片UBM层8和8之间设置有空隙部11(未形成部分),且芯片UBM层8和8分离地形成。
4.在移除半导体元件时的操作及其影响
通过上述方法,在将失效半导体元件3从半导体装置1中移除时,如图4中的箭头所示,来自移除器件200的激光束照射在半导体元件3中。
此时,由于半导体元件3的光吸收层9有效地吸收照射的激光束,因此,通过芯片UBM层8可有效地加热焊料100。
此外,在半导体元件3中形成有与光吸收层9接触的热扩散层10,且由此与常规相比可将在光吸收层9处吸收的热量更多地传递到焊料100。由此,可更有效地溶解焊料100。
这里,优选的是,光吸收层9形成为包括易于吸收激光束的Ti、Ni、Pt、Sn以及W中的任意一种。因此,光吸收层9容易吸收激光束,且由此可通过芯片UBM层8有效地加热与其底部结合的焊料100。
此外,优选的是,热扩散层10形成为包括具有高热导率的Al、Cu、Au以及Ag中的任意一种。于是,通过热扩散层10可容易地扩散在光吸收层9处吸收的热量,并由此与常规相比能够通过芯片UBM层8可向焊料100传递更多的热量,并且能够更有效地溶解焊料100。
以此方式,根据第一实施例的半导体装置1,可更有效地溶解焊料100。为此,如图5所示,在通过移除器件200进行吸附时,减少了残留在(布置在基底基板2的上表面侧上的)基板电极5上的焊料100的量。因而,能够易于在半导体元件3被移除的位置上重新安装半导体元件3。
5.第二实施例
将参考图6和图7描述根据第二实施例的半导体装置1A。
同时,在第二实施例中,与第一实施例具有相同结构的部分将使用与第一实施例中相同的符号和参考标记来表示,并且省略其说明。因此,下面将描述那些与第一实施例具有不同构造的的部分。
如图6所示,在根据第二实施例的半导体装置1A中,在基底基板2A的上表面侧上形成用作凸点下金属层的基板UBM层12,12,…。在本实施例中,基板UBM层12,12,…分别由单层结构形成,且由由光反射层13,13,…形成。光反射层13,13,…按照如下方式形成:部分光反光层13,13,…与位于基底基板2A上部的空隙部11相对。具体地,光反射层13,13,…在基底基板2A的上表面侧上布置成覆盖基板部4的上表面侧中的与空隙部11相对的所有部分。
光反射层13与基板电极5结合,并且光反射层13与基板电极5电连接。
同时,在至少一组光反射层13和13之间形成空隙部14,使得所有基板电极5,5…不会直接导通,从而使光反射层13和13分离地形成。
根据第二实施例的半导体装置1A,来自移除器件200的激光束被在基底基板2A的上表面侧上形成的光反射层13,13,…反射。
如图7所示,来自移除器件200的部分激光束穿过半导体元件3,从空隙部11发射出去,并且由光反射层13反射。此外,激光束的其余部分在半导体元件3之间穿过,并且由光反射层13反射。
这样反射的光束入射至光吸收层9并由光吸收层9吸收,并且直接照射至焊料100中。
反射的光被吸收至光吸收层9中,并因此通过热扩散层10来加热焊料100。另外,焊料100由照射至焊料100中的反射光直接加热。
这样,半导体装置1A包括基底基板2A上表面侧上的光反射层13,13,…,并由此通过从光反射层13,13,…反射的光来加热焊料100。因此,可有效地加热焊料100。
此外,由于光反射层13与基板电极5电连接,并因而在光反射层13处产生的热量被传递至焊料100,所以能够有效地加热焊料100。
另外,由于光反射层13形成于与基底基板2A的上表面侧中的与半导体元件3中的空隙部件11相对的部分上,并因而穿过半导体元件3的激光束并不直接照射至位于光反射层13下侧的基板部4中,所以能够抑制对基板部4造成损害。
此时,优选地,基底基板2A的光反射层13形成为包括易于反射激光束的Al、Cu、Au以及Ag中的任一种。因此,由于光反射层13易于反射激光束,所以可通过利用穿过半导体元件3的激光束来更有效地加热焊料100。
6.第三实施例
将参考图8描述根据第三实施例的半导体装置1B。
同时,在第三实施例中,与第一实施例和第二实施例具有相同结构的部分将以与第一实施例和第二实施例中相同的符号和参考标记来表示,并且省略其说明。因此,下面将描述那些与第一实施例和第二实施例中结构不同的部分。
如图8所示,在根据第二实施例的半导体装置1B中,与基底基板2B的上表面侧结合的基板UBM层12B,12B…分别由双层结构形成。在每个基板UBM层12B上从上到下的顺序依次布置有光反射层13和保护层15。
由于保护层15形成于基底基板2B的基板部4与光反射层13之间,且由此根据激光束的照射而在光反射层13处产生的热量并不直接传递至基板部4,所以可抑制对基板部4造成损害。
此时,优选地,基底基板2B的保护层15形成为包括易于吸收热量的Ti、Ni、Pt、Sn以及W中的任意一种。因此,由于通过照射激光束而在光反射层13处产生的热量难以传递至基板部4,所以可进一步抑制对基底基板2B的基板部4造成损害。
7.芯片UBM层和基板UBM层的布置图案
这里将描述根据上述第二实施例和第三实施例的半导体装置1A(1B)中的芯片UBM层8和基板UBM层12(12B)的布置图案。
7-1.第一布置图案
图9A和9B中所示的第一布置图案为如下情况下的布置图案,即假定芯片电极7,7,…和基板电极5,5,…分别形成为用于传输不同信号的独立端子。在这些图的示例中,在半导体元件3的下表面侧上形成四个芯片电极7,7,7和7。与芯片电极7,7,7和7结合的芯片UBM层8,8,8和8布置成各自独立,使得这些芯片电极7,7,7和7不直接彼此连接。芯片UBM层8,8,8和8形成为近似正方形形状,且在这种情况下,空隙部11在半导体元件3的下表面侧上形成为近似十字形形状。
在基底基板2A(2B)的上表面侧上形成有金属层12'(12B)以及与基板电极5,5,5和5结合的基板UBM层12,12,12和12(12B,12B,12B和12B)。金属层12'是由类似于基板UBM层12的光反射层13构成的金属层,且金属层12B'是从上到下布置有类似于基板UBM层12B的光反射层13以及保护层15的金属层。
在金属层12'(12B')和基板UBM层12,12,12和12(12B,12B,12B和12B)之间形成有空隙部14,14,14和14,且由此基板电极5,5,5和5不直接彼此导通。
金属层12'(12B')形成为覆盖与在半导体元件3的下表面上形成的空隙部11相对的这个部分。因此,光反射层形成为覆盖与基底基板2A(2B)的上表面侧上的空隙部11相对的整个部分。为此,穿过空隙部11的激光束不直接照射基板部4。
此外,在第一布置图案中,芯片UBM层8,8,8和8形成为覆盖基底基板2A(2B)侧上的空隙部14,14,14和14(参考图9B)。为此,防止了穿过半导体元件3侧上的空隙部11的激光束照射至基底基板2A(2B)侧上的空隙部14,14,14和14中,并能够抑制对基板部4的损害。
7-2.第二布置图案
图10所示的第二布置图案中的每个芯片UBM层8和每个空隙部14的形状与第一布置图案的形状不同。具体地,在第二布置图案中,芯片UBM层8,8,8和8的形状为矩形。为此,基底基板2A(2B)中的空隙部14,14,14和14的外缘形状均为彼此相同的矩形形状。
7-3.第三布置图案
在如图11所示的第三布置图案中,半导体元件3的每个芯片UBM层8都具有三角形外形。为此,基底基板2A(2B)中的每个空隙部14,14,14和14也具有三角形形状的外缘形状。
7-4.第四布置图案
第四布置图案为在半导体元件3的芯片电极7,7,…中以及在基底基板2A(2B)的基板电极5,5,…中形成有具有相同电势的端子的示例。
在图12所示的示例中,半导体元件3中的四个芯片电极7,7,7和7之中的三个芯片电极7,7和7由具有彼此相同的电势的端子形成,并且通过公共的芯片UBM层8与彼此电连接。剩余的一个芯片电极7是不同于具有相同电势的三个端子的端子,在相关的芯片电极7的下部中布置的芯片UBM层8形成为通过空隙部11与公共芯片UBM层8分离,并由此彼此具有不同电势的端子不彼此直接导通。
在基底基板2A(2B)的上表面侧中,形成有与三个基板电极5,5和5(它们是具有彼此相同电势的端子)结合的公共基板UBM层12(12B)和与基板电极5(它是与具有彼此相同电势的端子不同的端子)结合的基板UBM层12(12B)。在这两个基板UBM层12(12B)之间形成有空隙部14,并且不具有彼此相同电势的端子不直接彼此导通。
公共基板UBM层12(12B)在基底基板2A的上表面侧上形成为覆盖基板部4的上表面侧中的与空隙部11相对的整个部分。为此,穿过空隙部11的激光束不直接照射基板部4。
此外,在半导体元件3侧,形成为与公共芯片UBM层8分离的芯片UBM层8形成为覆盖基底基板2A(2B)上的空隙部14。因此,可防止穿过空隙部11的激光束照射空隙部14。
7-5.其他布置图案
芯片UBM层8和基板UBM层12(12B)的布置图案并不局限于上述第一至第四布置图案中所示的图案,并且光反射层13可形成为使得穿过形成在芯片UBM层8,8,…之间的空隙部11的激光束被基底基板2A(2B)的光反射层13反射。
8.关于半导体元件的形状的变化示例
在半导体元件3在基底基板2A(2B)上无间隙地布置成一行的情况下,当激光束照射至作为移除目标的半导体元件3中时,认为部分激光束照射至相邻的半导体元件3。此时,存在可损坏正常半导体元件3的情况。
因此,有必要研究半导体元件3的形状以及与半导体元件3的下部结合的焊料100,100,…的布置。
在图13所示的示例中,半导体元件3形成为六边形形状,并且焊料100,100,…的布置位置与半导体元件3的六边形形状的中心点的距离相等。
由于激光束的照射点300大致为圆形形状,所以激光束可照射所有焊料100,100,…,并且可通过调节照射点300的直径使照射范围适配于半导体元件3的外围边缘内。
因此,可移除作为移除目标的半导体元件3,而不损坏与作为移除目标的半导体元件3相邻的半导体元件3。
同时,除上述六边形形状外,半导体元件3可配置成三角形形状、多种形状或其类似物的组合。
9.没有空隙部的示例
在上述示例中,由于芯片UBM层8,8,…与基板UBM层12,12,…(12B,12B,…)分离地形成,因此,形成了半导体元件3的空隙部11和基底基板2(2A、2B)的空隙部14。然而,可按照如下方式配置,即不会形成空隙部11或空隙部14。这里,空隙部11表示半导体元件3下表面侧上的基板部6在下部处暴露的部分,且空隙部14表示基底基板2(2A、2B)的上表面侧上的基板部4在上部处暴露的部分。
图14表示在半导体元件3C的下表面侧上没有形成空隙部11的示例。
半导体元件3C的下表面侧全部由芯片UBM层8C,8C,…覆盖,且在至少一组芯片UBM层8C和8C之间,一个芯片UBM层8C的一部分形成在不同于另一芯片UBM层8C的层的位置(层在半导体元件3C的厚度方向上的形成位置)处。因此,芯片UBM层8C和8C形成在彼此不同的层位置处,由此能够形成不彼此直接导通的芯片UBM层8C和8C。
由于没有形成空隙部11,因此可减少形成为用于抑制对基底基板2B上表面侧上的基板部4的损害的光反射层13的面积。
同时,图14图示了使用基底基板2B的示例,而且在基底基板2A的光反射层13中也能够获得与基底基板2B中相同的效果。
此外,图15图示了在基底基板2D的上表面侧上未形成空隙部14的示例(第二示例)。
基底基板2D的上表面侧全部由基板UBM层12D,12D,…覆盖,且在至少一组基板UBM层12D和12D之间,一个基板UBM层12D的一部分形成在不同于另一基板UBM层12D的层的位置(层在基底基板2D的厚度方向上的形成位置)处。因此,基板UBM层12D和12D形成在彼此不同的层位置处,由此能够形成不彼此直接导通的基板UBM层12D和12D。
由于穿过半导体元件3的激光束因没有形成空隙部14而不直接照射至基板部4,因此可减少在半导体元件3中形成的芯片UBM层8的面积。
10.概述
如上所述,在根据本发明的实施例的半导体装置1(1A、1B、1C、1D)中,在半导体元件3(3C)中形成光吸收层,且因而可利用激光束移除半导体元件3(3C),且无需覆盖光吸收材料。因此,可从半导体装置1(1A、1B、1C、1D)仅移除失效的半导体元件3(3C),而不增加制造成本。
同时,本发明可采用如下构造。
(1)一种半导体装置,包括:
基底基板,在所述基底基板上布置有基板电极;以及
半导体元件,所述半导体元件包括通过焊料与所述基板电极电连接的芯片电极,且在所述半导体元件的下表面侧上形成有光吸收层。
(2)如(1)中所述的半导体装置,其中,在所述半导体元件的下表面侧上形成有与所述光吸收层接触的热扩散层。
(3)如(1)或(2)所述的半导体装置,其中,在所述基底基板的上表面侧上形成有光反射层。
(4)如(3)所述的半导体装置,其中,所述光反射层与所述基板电极电连接。
(5)如(3)或(4)所述的半导体装置,其中,在所述光反射层的下表面侧上形成有与所述光反射层接触的保护层。
(6)如(3)至(5)中任一项所述的半导体装置,其中,
所述半导体元件在下表面侧上具有未形成有所述光吸收层的空隙部,并且
在所述基板的上表面侧中的与所述空隙部相对的一部分上形成有所述光反射层。
(7)在如(1)至(6)任一项所述的半导体装置,其中,所述光吸收层形成为包括Ti、Ni、Sn、Pt以及W中的任一种。
(8)如(2)至(7)中任一项所述的半导体装置,其中,所述热扩散层形成为包括Al、Cu、Au以及Ag中的任一种。
(9)如(3)至(8)中任一项所述的半导体装置,其中,所述光反射层形成为包括Al、Cu、Au以及Ag中的任一种。
(10)如(5)至(9)中任一项所述的半导体装置,其中,所述保护层形成为包括Ti、Ni、Pt、Sn以及W中的任一种。
本领域技术人员可以理解,在附属权利要求或其等效权利要求的范围内,根据设计需求或其他因素可发生多种变形、组和、分组和以及替换。
本申请包含与2013年6月26日向日本专利局提交的日本在先专利申请JP2013-133772的公开内容相关的主题,在这里将该在先申请的全部内容以引用的方式并入本文。

Claims (10)

1.一种半导体装置,其包括:
基底基板,在所述基底基板上布置有基板电极;以及
半导体元件,所述半导体元件包括通过焊料与所述基板电极电连接的芯片电极,且在所述半导体元件的下表面侧上形成有光吸收层。
2.如权利要求1所述的半导体装置,其中,在所述半导体元件的下表面侧上形成有与所述光吸收层接触的热扩散层。
3.如权利要求1所述的半导体装置,其中,在所述基底基板的上表面侧上形成有光反射层。
4.如权利要求3所述的半导体装置,其中,所述光反射层与所述基板电极电连接。
5.如权利要求3所述的半导体装置,其中,在所述光反射层的下表面侧上形成有与所述光反射层接触的保护层。
6.如权利要求3所述的半导体装置,其中,
所述半导体元件在下表面侧上具有未形成所述光吸收层的空隙部,并且
在所述基板的上表面侧中的与所述空隙部相对的一部分上形成有所述光反射层。
7.如权利要求1-6中任一项所述的半导体装置,其中,所述光吸收层形成为包括Ti、Ni、Sn、Pt以及W中的任一种。
8.如权利要求2-6中任一项所述的半导体装置,其中,所述热扩散层形成为包括Al、Cu、Au以及Ag中的任一种。
9.如权利要求3-6中任一项所述的半导体装置,其中,所述光反射层形成为包括Al、Cu、Au以及Ag中的任一种。
10.如权利要求5或6所述的半导体装置,其中,所述保护层形成为包括Ti、Ni、Pt、Sn以及W中的任一种。
CN201410181198.8A 2013-06-26 2014-04-30 半导体装置 Expired - Fee Related CN104253054B (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108028259A (zh) * 2015-10-14 2018-05-11 索尼半导体解决方案公司 成像元件、成像元件的制造方法、成像装置以及成像装置的制造方法
CN116110805A (zh) * 2023-04-13 2023-05-12 深圳宏芯宇电子股份有限公司 芯片键合方法、结构及存储器

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6156402B2 (ja) 2015-02-13 2017-07-05 日亜化学工業株式会社 発光装置
US10141288B2 (en) * 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US10797038B2 (en) * 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1396641A (zh) * 2002-08-13 2003-02-12 威盛电子股份有限公司 覆晶接合结构与形成方法
US6573537B1 (en) * 1999-12-22 2003-06-03 Lumileds Lighting, U.S., Llc Highly reflective ohmic contacts to III-nitride flip-chip LEDs
CN101924088A (zh) * 2009-06-16 2010-12-22 台湾积体电路制造股份有限公司 一种集成电路结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6936859B1 (en) * 1998-05-13 2005-08-30 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
JP3735069B2 (ja) 2002-01-07 2006-01-11 株式会社大成化研 はんだ付けされた電子部品の取り外し方法及びその装置
JP2004273795A (ja) 2003-03-10 2004-09-30 Sharp Corp 部品リペア装置および部品リペア方法
US7129576B2 (en) * 2003-09-26 2006-10-31 Tessera, Inc. Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573537B1 (en) * 1999-12-22 2003-06-03 Lumileds Lighting, U.S., Llc Highly reflective ohmic contacts to III-nitride flip-chip LEDs
CN1396641A (zh) * 2002-08-13 2003-02-12 威盛电子股份有限公司 覆晶接合结构与形成方法
CN101924088A (zh) * 2009-06-16 2010-12-22 台湾积体电路制造股份有限公司 一种集成电路结构

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108028259A (zh) * 2015-10-14 2018-05-11 索尼半导体解决方案公司 成像元件、成像元件的制造方法、成像装置以及成像装置的制造方法
CN108028259B (zh) * 2015-10-14 2022-05-17 索尼半导体解决方案公司 成像元件、成像元件的制造方法、成像装置以及成像装置的制造方法
US11652122B2 (en) 2015-10-14 2023-05-16 Sony Semiconductor Solutions Corporation Imaging element, method of manufacturing imaging element, imaging device, and method of manufacturing imaging device
CN116110805A (zh) * 2023-04-13 2023-05-12 深圳宏芯宇电子股份有限公司 芯片键合方法、结构及存储器

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