CN201829475U - 半导体芯片互连结构及应用其的半导体封装件 - Google Patents

半导体芯片互连结构及应用其的半导体封装件 Download PDF

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CN201829475U
CN201829475U CN201020507572.6U CN201020507572U CN201829475U CN 201829475 U CN201829475 U CN 201829475U CN 201020507572 U CN201020507572 U CN 201020507572U CN 201829475 U CN201829475 U CN 201829475U
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projection
interconnection structure
semiconductor chip
group
bumps
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林少雄
林建福
周辉星
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Advanpack Solutions Pte Ltd
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Advanpack Solutions Pte Ltd
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Abstract

本实用新型公开一种半导体芯片互连结构及应用其的半导体封装件。半导体芯片互连结构包括芯片、凸块组及焊球。芯片包括接垫并具有接垫开孔，接垫从接垫开孔露出。凸块组包括第一凸块及第二凸块。第一凸块设于接垫。第二凸块设于第一凸块，第二凸块的外径实质上等于或大于第一凸块的外径。焊球连接于凸块组。

Description

半导体芯片互连结构及应用其的半导体封装件
技术领域
本实用新型涉及一种半导体芯片互连结构及应用其的半导体封装件，且特别是涉及一种具有堆叠凸块的半导体芯片互连结构及应用其的半导体封装件。 
背景技术
请参照图1(现有技术)，其绘示现有的半导体芯片互连结构示意图。半导体芯片互连结构10包括一基板12、一接垫14、一凸块16及一焊球18。 
然而，设于凸块16上的焊球18在回焊(reflow)常常流至接垫14-而污染到接垫14，影响接垫14的电性品质与可靠性。 
实用新型内容
本实用新型的目的在于提供一种半导体芯片互连结构及应用其的半导体封装件，焊球于回焊后不会接触到接垫，避免影响接垫的电性品质与可靠性。 
本实用新型的目的是这样实现的，即提出一种半导体芯片互连结构。半导体芯片互连结构包括一芯片、一凸块组及一焊球。芯片包括一接垫并具有一接垫开孔，接垫从接垫开孔露出。凸块组包括一第一凸块及一第二凸块。第一凸块设于接垫上。第二凸块设于第一凸块上，第二凸块的外径实质上等于或大于第一凸块的外径。焊球连接于凸块组。 
根据本实用新型还提出一种半导体封装件。半导体封装件包括一基板及一半导体芯片互连结构。半导体芯片互连结构包括一芯片、一凸块组及一焊球。芯片包括一接垫并具有一接垫开孔，接垫从接垫开孔露出。凸块组包括一第一凸块及一第二凸块。第一凸块设于接垫。第二凸块设于第一凸块，第二凸块的外径至少等于第一凸块的外径。焊球连接于凸块组。 
本实用新型的优点在于，本实用新型所述半导体芯片互连结构及半导体 封装件，与焊球接触的凸块的外径适当，使凸块中与焊球接触的表面的面积足够。如此，回焊后的焊球便可完全地形成于凸块上，不会往旁边流至接垫，避免污染到接垫。此外，由于回焊后的焊球可完全地形成于凸块上，故在制造性上，对焊球是可控制的。如此，可控制焊球的高度、大小及形状等，以配合制作工艺的运作，使制作工艺运作更具弹性。再者，与焊球接触的凸块尺寸不受接垫的尺寸影响，故可设计较大的凸块，以承接较大的焊球，增加焊球与对手件的结合度及电性品质。 
为让本实用新型的上述内容能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下： 
附图说明
图1为现有的半导体芯片互连结构示意图； 
图2为本实用新型第一实施例的半导体芯片互连结构的示意图； 
图3为图2的半导体芯片互连结构的示意图； 
图4为本实用新型第二实施例的半导体芯片互连结构的示意图； 
图5为本实用新型第三实施例的半导体芯片互连结构的示意图； 
图6为本实用新型第四实施例的半导体芯片互连结构的示意图； 
图7为本实用新型第五实施例的半导体芯片互连结构的示意图； 
图8为本实用新型第六实施例的半导体芯片互连结构的示意图； 
图9为本实用新型第七实施例的半导体芯片互连结构的示意图。 
主要元件符号说明 
10、112、212、412、512、612、712、812：半导体芯片互连结构 
12：基板 
14、114、814：接垫 
16：凸块 
18、108、208、408、708：焊球 
100：半导体封装件 
110：基板 
116：接垫开孔 
118、218、418、518、618、718、818：凸块组 
120、220、420、520、620、720、820：第一凸块 
122、222、422、522、622、722、822：第二凸块 
126：芯片 
132：底胶 
134、734：上表面 
224、424：第三凸块 
638：涂布层 
726：绝缘层 
D11、D12、D21、D22、D23、D41、D42、D43、D51、D52：外径 
DP：内径 
具体实施方式
第一实施例 
请参照图2，其绘示依照本实用新型第一实施例的半导体芯片互连结构的示意图。半导体封装件100包括基板110、半导体芯片互连结构112及底胶(underfill)132。底胶132填充于基板110与半导体芯片互连结构112之间。 
半导体芯片互连结构112，例如是覆晶式芯片(flip chip)、引线框或基板，其通过焊球108与基板110电连接。 
请参照图3，其绘示图2的半导体芯片互连结构的示意图。图3的半导体芯片互连结构的型态为未与基板110接合的型态。半导体芯片互连结构112包括芯片126、凸块(bump)组118、焊球108及接垫114。 
芯片126包括接垫114并具有接垫开孔116，接垫114从接垫开孔116露出。焊球108连接于凸块组118。 
凸块组118包括第一凸块120及第二凸块122。第一凸块120设于接垫114上，第二凸块122设于第一凸块120上。第二凸块122的外径D12大于第一凸块120的外径D11。此处所称的“外径”指外围的径向尺寸，而以下所称的“内径”指内围的径向尺寸。 
较佳但非限定地，凸块组118通过热超音波结合(thermosonic wirebond)的方式，以银或铜形成。较佳但非限定地，第一凸块120的材质是银而第二凸块122的材质是铜。较佳但非限定地，接垫114是铝垫。较佳但非限定地， 焊球108的材质选自于由锡、银、铜及铅所构成的群组。 
第二凸块122的外径D12大于第一凸块120的外径D11及接垫开孔116的内径DP。即，第二凸块122可完全地遮蔽第一凸块120的上表面及接垫开孔116。由于第二凸块122的外径D12大于接垫开孔116的内径DP，故，焊球108于回焊后可完全地形成于第二凸块122上(如图3所示)而不会溢流至接垫114而污染到接垫114。 
进一步地说，本实施例通过适当地设计第二凸块122的外径D12，使第二凸块122的上表面134的面积足够大，回焊后的焊球108便可完全地形成于第二凸块122上，避免溢流问题发生。 
此外，因为回焊后的焊球108可完全地形成于第二凸块122上，故在制作工艺上对焊球108是可控制的。如此，可通过控制焊球108的高度、大小及形状等去配合制作工艺的运作，使制作工艺在操作上更具弹性。 
此外，第二凸块122的尺寸不受接垫114的尺寸影响。如此，可设计较大的第二凸块122，以承接较大的焊球108，增加焊球108与对手件的结合度及电性品质。 
此外，堆叠的第一凸块120及第二凸块122可产生垫高基板110的效果，增加基板110与接垫114之间的距离，此有助于底胶132的形成及提升半导体封装件100的可靠度。 
第一凸块120及第二凸块122可分别由不同材质所制成。例如，第一凸块120的材质较软且价格较高的金(Au)，其形成于接垫114上；而第二凸块122的材质较硬且价格较低的铜(Cu)，此有助于降低封装成本及避免在形成第一凸块120时破坏芯片126。 
第二实施例 
请参照图4，其绘示依照本实用新型第二实施例的半导体芯片互连结构的示意图。在第二实施例中，与第一实施例相同之处沿用相同标号，在此不再赘述。第二实施例的半导体芯片互连结构212与第一实施例的半导体芯片互连结构112不同之处在于，半导体芯片互连结构212的凸块组218还包括第三凸块224。较佳但非限定地，第三凸块224的材质是铜。 
凸块组218包括第一凸块220、第二凸块222及第三凸块224。第三凸块224的外径D23大于第二凸块222的外径D22、第一凸块220的外径D21 及接垫开孔116的内径DP，且第二凸块222的外径D22大于第一凸块220的外径D21。即，第三凸块224可完全地遮蔽第二凸块222的上表面、第一凸块220的上表面及接垫开孔116。 
由于第三凸块224的外径D23大于接垫开孔116的内径DP，故焊球208于回焊后完全地形成于第三凸块224上，如图4所示，而不致污染到接垫114。 
第三实施例 
请参照图5，其绘示依照本实用新型第三实施例的半导体芯片互连结构的示意图。在第三实施例中，与第二实施例相同之处沿用相同标号，在此不再赘述。第三实施例的半导体芯片互连结构412与第二实施例的半导体芯片互连结构212不同之处在于，半导体芯片互连结构412的凸块组418的第三凸块424的外径D43小于第二凸块422的外径D42。 
凸块组418包括第一凸块420、第二凸块422及第三凸块424。第三凸块424的外径D43小于第二凸块422的外径D42，而第二凸块422的外径D42大于第一凸块420的外径D41及接垫开孔116的内径DP。即，第二凸块422可完全地遮蔽第一凸块420的上表面及接垫开孔116。 
第三凸块424可提升焊球408与第二凸块422之间的结合性。在回焊制作工艺中，第三凸块424对流动的焊球408起阻碍作用且由于第三凸块424改变第二凸块422的表面轮廓，故第三凸块424可避免流动的焊球408溢流至接垫114。 
第四实施例 
请参照图6，其绘示依照本实用新型第四实施例的半导体芯片互连结构的示意图。在第四实施例中，与第一实施例相同之处沿用相同标号，在此不再赘述。第四实施例的半导体芯片互连结构512与第一实施例的半导体芯片互连结构112不同之处在于，半导体芯片互连结构512的凸块组518的第二凸块522的外径D52实质上等于第一凸块520的外径D51。 
此外，堆叠的第一凸块520及第二凸块522可产生垫高基板110的效果，此有助于底胶132的形成及提升半导体封装件100的可靠度。并且，第一凸块520及第二凸块522分别可由不同材质所制成，例如，第一凸块520的材质较软且价格较高的金(Au)，其形成于接垫114上；而第二凸块522的材 质较硬且价格较低的铜(Cu)，此有助于降低封装成本及避免在形成第一凸块120时破坏芯片126。 
第五实施例 
请参照图7，其绘示依照本实用新型第五实施例的半导体芯片互连结构的示意图。在第五实施例中，与第一实施例相同之处沿用相同标号，在此不再赘述。第五实施例的半导体芯片互连结构612与第一实施例的半导体芯片互连结构112不同之处在于，半导体芯片互连结构612的凸块组618更包括涂布层638，其形成于第一凸块620的外表面及第二凸块622的外表面。较佳但非限定地，涂布层638覆盖整个第一凸块620及第二凸块622。涂布层638可保护第一凸块620及第二凸块622免于受到环境的侵蚀，例如是氧化。 
本实施例中，在第一凸块620及第二凸块622形成后，可应用溅镀(sputter)技术或无电镀法(electroless plating)形成涂布层638；或者，在另一实施态样中，形成第一凸块620及第二凸块622的焊线(未绘示)本身即具有涂布层638。在打线工具头将第一凸块620及第二凸块622形成于基板上后，涂布层638仍保留在第一凸块620及第二凸块622上。 
较佳但非限定地，涂布层638的材质由镍(Ni)与金(Au)至少一者所组成，例如是镍金合金、化学镍金(ENIG)或金。 
虽然第五实施例的涂布层638以形成于图7的第一凸块620及第二凸块622为例作说明。然本技术领域的通常知识当知，涂布层638也可形成于上述第二实施例至第三实施例的第一凸块、第二凸块及第三凸块上，以及上述第四实施例的第一凸块及第二凸块上。 
第六实施例 
请参照图8，其绘示依照本实用新型第六实施例的半导体芯片互连结构的示意图。在第六实施例中，与第一实施例相同之处沿用相同标号，在此不再赘述。第六实施例的半导体芯片互连结构712与第一实施例的半导体芯片互连结构112不同之处在于，半导体芯片互连结构712更包括绝缘层726，其包覆凸块组718。第二凸块722的上表面734未被绝缘层726覆盖而外露，用于与焊球708电连接。 
第二凸块722设于第一凸块720上，焊球708设于第二凸块722上。 
绝缘层726可保护凸块组718，使凸块组718免受环境的侵蚀，例如是氧化。绝缘层726完全避免焊球708溢流至接垫114上，可提升凸块组718与接垫114之间的电性品质及可靠性 
虽然第六实施例的绝缘层726以形成于图8的半导体芯片互连结构712为例作说明。然本技术领域的通常知识当知，绝缘层726也可形成于上述第二实施例至第五实施例的凸块组。 
当绝缘层726形成于第二实施例(图4)至第三实施例(图5)的凸块组时，绝缘层726包覆凸块组的侧面而不覆盖凸块组中与焊球连接的凸块表面，可使凸块表面外露而与焊球电连接。举例来说，以图3(第一实施例)为例作说明，绝缘层包覆凸块组118并暴露出第二凸块122的上表面134。又例如，以图4(第二实施例)为例作说明，绝缘层包覆凸块组218并暴露出第三凸块224的上表面。再例如，以图5(第三实施例)为例作说明，绝缘层包覆凸块组418并暴露出第二凸块422及第三凸块424的上表面。 
此外，在另一实施态样中(未绘示)，半导体芯片互连结构712的凸块组也可形成有如第五实施例所述的涂布层638。 
第七实施例 
请参照图9，其绘示依照本实用新型第七实施例的半导体芯片互连结构的示意图。在第七实施例中，与第一实施例相同之处沿用相同标号，在此不再赘述。第七实施例的半导体芯片互连结构812与第一实施例的半导体芯片互连结构112不同之处在于，半导体芯片互连结构812包括两组凸块组818，其同时形成于单一接垫814上。 
每组凸块组818包括一第一凸块820及一第二凸块822。两组凸块组818共同形成于接垫814上。 
通过较小的第一凸块820，可同时设置两组第一凸块820至接垫814上，以增加输出/入接点的数目。 
此外，在另一实施态样中(未绘示)，可形成如第六实施例所述的绝缘层726于半导体芯片互连结构812，以保护凸块组818。其中，较佳但非限定地，两组凸块组818之间填满绝缘层726的一部分(未绘示)。 
在另一实施态样中(未绘示)，也可形成如第五实施例所述的涂布层638于半导体芯片互连结构812的凸块组。 
此外，上述半导体芯片互连结构212、312、412、512、612、712及812也可跟图1的基板110电性接合，接合后的半导体封装件相似于第一实施例的半导体封装件100，在此便不再赘述。 
本实用新型上述实施例所揭露的半导体芯片互连结构及半导体封装件，与焊球接触的凸块的外径适当，使凸块中与焊球接触的表面的面积足够。如此，回焊后的焊球便可完全地形成于凸块上，不会往旁边流至接垫，避免污染到接垫。此外，由于回焊后的焊球可完全地形成于凸块上，故在制造性上，对焊球是可控制的。如此，可控制焊球的高度、大小及形状等，以配合制作工艺的运作，使制作工艺运作更具弹性。再者，与焊球接触的凸块尺寸不受接垫的尺寸影响，故可设计较大的凸块，以承接较大的焊球，增加焊球与对手件的结合度及电性品质。 

Claims (16)

1.一种半导体芯片互连结构，其特征在于，该半导体芯片互连结构包括：芯片、凸块组以及连接于该凸块组的焊球，其中该芯片包括接垫并具有接垫开孔，该接垫从该接垫开孔露出，该凸块组包括：第一凸块，设于该接垫；及第二凸块，设于该第一凸块上，该第二凸块的外径至少等于该第一凸块的外径。
2.如权利要求1所述的半导体芯片互连结构，其特征在于，该半导体芯片互连结构还包括绝缘层，其包覆该凸块组，其中该第二凸块的上表面外露。
3.如权利要求1所述的半导体芯片互连结构，其特征在于，该第二凸块的外径至少等于该接垫开孔的内径。
4.如权利要求3所述的半导体芯片互连结构，其特征在于，该凸块组还包括第三凸块，其设于该第二凸块；其中，该第三凸块的外径小于该第二凸块的外径。
5.如权利要求1所述的半导体芯片互连结构，其特征在于，该凸块组还包括第三凸块，其设于该第二凸块；其中，该第三凸块的外径至少等于该第二凸块的外径。
6.如权利要求1所述的半导体芯片互连结构，其特征在于，该凸块组还包括涂布层，其形成于该第一凸块及该第二凸块。
7.如权利要求6所述的半导体芯片互连结构，其特征在于，该涂布层的材质选自由镍(Ni)与金(Au)所构成的群组。
8.如权利要求1所述的半导体芯片互连结构，其特征在于，该凸块组还包括第三凸块，其设于该第二凸块，该半导体芯片互连结构还包括绝缘层，其包覆该凸块组，其中该第三凸块的上表面露出。
9.一种半导体封装件，包括基板以及半导体芯片互连结构，其特征在于，该半导体芯片互连结构包括：芯片、凸块组以及连接于该凸块组的焊球，其中该芯片包括接垫并具有接垫开孔，该接垫从该接垫开孔露出；该凸块组包括：第一凸块，设于该接垫；及第二凸块，设于该第一凸块，该第二凸块的外径至少等于该第一凸块的外径。
10.如权利要求9所述的半导体封装件，其特征在于，该半导体芯片互连结构还包括绝缘层，其包覆该凸块组，其中该第二凸块的上表面外露。
11.如权利要求9所述的半导体封装件，其特征在于，该第二凸块的外径至少等于该接垫开孔的内径。
12.如权利要求11所述的半导体封装件，其特征在于，该凸块组还包括第三凸块，设于该第二凸块；其中，该第三凸块的外径小于该第二凸块的外径。
13.如权利要求9所述的半导体封装件，其特征在于，该凸块组还包括第三凸块，其设于该第二凸块；其中，该第三凸块的外径至少等于该第二凸块的外径。
14.如权利要求9所述的半导体封装件，其特征在于，该凸块组还包括涂布层，其形成于该第一凸块及该第二凸块。
15.如权利要求14所述的半导体封装件，其特征在于，该涂布层的材质选自于由镍与金所构成的群组。
16.如权利要求9所述的半导体封装件，其特征在于，该凸块组还包括第三凸块，其设于该第二凸块，该半导体芯片互连结构还包括绝缘层，其包覆该凸块组，其中该第三凸块的上表面外露。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958309A (zh) * 2009-08-27 2011-01-26 先进封装技术私人有限公司 半导体芯片互连结构及应用其的半导体封装件

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
CN102931108B (zh) * 2012-10-10 2014-04-30 矽力杰半导体技术(杭州)有限公司 一种倒装芯片封装方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
DE4446471C2 (de) * 1994-12-23 1997-05-22 Fraunhofer Ges Forschung Verfahren zur Montage eines Chips auf einem flexiblen Schaltungsträger
JP2735022B2 (ja) * 1995-03-22 1998-04-02 日本電気株式会社 バンプ製造方法
CN1107979C (zh) * 1995-07-14 2003-05-07 松下电器产业株式会社 半导体器件的电极结构、形成方法及安装体和半导体器件
US5956606A (en) * 1997-10-31 1999-09-21 Motorola, Inc. Method for bumping and packaging semiconductor die
JP3407275B2 (ja) * 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6437448B1 (en) * 2000-01-14 2002-08-20 I-Ming Chen Semiconductor device adapted for mounting on a substrate
US20020093108A1 (en) * 2001-01-15 2002-07-18 Grigorov Ilya L. Flip chip packaged semiconductor device having double stud bumps and method of forming same
US20020151164A1 (en) * 2001-04-12 2002-10-17 Jiang Hunt Hang Structure and method for depositing solder bumps on a wafer
TW544901B (en) * 2001-06-13 2003-08-01 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
JP4427298B2 (ja) * 2003-10-28 2010-03-03 富士通株式会社 多段バンプの形成方法
US7064434B2 (en) * 2003-11-26 2006-06-20 Atmel Corporation Customized microelectronic device and method for making customized electrical interconnections
KR100597993B1 (ko) * 2004-04-08 2006-07-10 주식회사 네패스 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법
JP2006156544A (ja) * 2004-11-26 2006-06-15 Denso Corp 基板の実装構造およびその実装方法
US7279409B2 (en) * 2005-10-31 2007-10-09 Freescale Semiconductor, Inc Method for forming multi-layer bumps on a substrate
US7422973B2 (en) * 2006-01-27 2008-09-09 Freescale Semiconductor, Inc. Method for forming multi-layer bumps on a substrate
US20070200234A1 (en) * 2006-02-28 2007-08-30 Texas Instruments Incorporated Flip-Chip Device Having Underfill in Controlled Gap
US7573137B2 (en) * 2006-03-31 2009-08-11 Texas Instruments Incorporated Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices
US7547577B2 (en) * 2006-11-14 2009-06-16 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with solder paste connections
US20090014852A1 (en) * 2007-07-11 2009-01-15 Hsin-Hui Lee Flip-Chip Packaging with Stud Bumps
US20090091027A1 (en) * 2007-10-05 2009-04-09 Powertech Technology Inc. Semiconductor package having restraining ring surfaces against soldering crack
TW201133745A (en) * 2009-08-27 2011-10-01 Advanpack Solutions Private Ltd Stacked bump interconnection structure and semiconductor package formed using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958309A (zh) * 2009-08-27 2011-01-26 先进封装技术私人有限公司 半导体芯片互连结构及应用其的半导体封装件

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