CN105575827B - 用于把半导体管芯附接到载体的方法 - Google Patents

用于把半导体管芯附接到载体的方法 Download PDF

Info

Publication number
CN105575827B
CN105575827B CN201510720146.8A CN201510720146A CN105575827B CN 105575827 B CN105575827 B CN 105575827B CN 201510720146 A CN201510720146 A CN 201510720146A CN 105575827 B CN105575827 B CN 105575827B
Authority
CN
China
Prior art keywords
interarea
semiconductor element
semiconductor
insulating layer
solder interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510720146.8A
Other languages
English (en)
Other versions
CN105575827A (zh
Inventor
M.鲍尔
L.海策尔
C.施蒂姆普弗尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN105575827A publication Critical patent/CN105575827A/zh
Application granted granted Critical
Publication of CN105575827B publication Critical patent/CN105575827B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Die Bonding (AREA)

Abstract

本公开涉及用于把半导体管芯附接到载体的方法。方法包括：提供半导体管芯，所述半导体管芯包括第一主面和与第一主面相对的第二主面以及在第一主面上的至少一个电接触元件；把绝缘层施加到所述半导体管芯的所述第二主面上；把焊料互连层施加到所述绝缘层上；以及利用焊料互连层把所述半导体管芯附接到载体。

Description

用于把半导体管芯附接到载体的方法
技术领域
本公开涉及一种用于制作电子器件的方法，用于把半导体管芯附接到载体的方法，以及一种电子器件。
背景技术
当制作电子器件或电子模块时，非常常见的是，具有背面电接触焊盘的半导体芯片以及不具有背面电接触焊盘的半导体芯片必须被附接到载体。具有背面电接触焊盘的半导体芯片例如是包括垂直晶体管结构的芯片，比如例如，绝缘栅双极（IGB）晶体管。不具有背面电接触焊盘的半导体芯片是例如逻辑芯片或控制器芯片。为了把这些不同的半导体芯片附接到载体，不同的非兼容过程步骤是必要的，这些过程步骤以不同的热负荷条件为特征，这意味着它们必须被分离并且材料也必须相应地被选择。
附图说明
附图被包括以提供对实施例的进一步理解，并且被并入本说明书中且构成本说明书的一部分。附图图示实施例，并且与描述一起用于解释实施例的原理。其他实施例和实施例的许多预期优点将被容易理解，因为它们通过参考下面的详细描述而变得更好理解。附图中的元件不一定相对于彼此按比例。相似的附图标记指示相应的类似部分。
图1A-C示出示意性横截面侧视图表示以图示用于根据示例制作电子器件的方法。
图2A-E示出示意性横截面侧视图表示以图示用于制作半导体芯片以使得半导体芯片能够以电绝缘方式附接到载体的方法的示例。
图3A-E示出示意性横截面侧视图表示以图示用于制作半导体芯片以使得半导体芯片能够以电绝缘方式附接到载体的方法的示例，其中，在半导体管芯下方的周缘部（circumferential edge portion）不被焊料互连层覆盖。
图4示出根据示例的电子器件的示意性横截面侧视图表示。
具体实施方式
现在参照附图描述各方面和实施例，其中贯穿全文，相似的附图标记通常用于指代相似的元件。在下面的描述中，出于解释的目的，许多具体的细节被阐述以便提供对实施例的一个或多个方面的彻底理解。然而，对于本领域的一个技术人员可能明显的是，这些实施例的一个或多个方面可以用较少程度的具体细节被实践。在其他实例中，已知的结构和元件以示意性的形式示出，以便于促进描述实施例的一个或多个方面。应该理解的是，在不脱离本发明的范围的情况下其他实施例可以被利用并且结构或逻辑的改变可以被做出。应当进一步注意的是，附图不是按比例的或不一定按比例。
此外，虽然实施例的特定特征或方面可以相对于几个实施方式中的只有一个被公开，但是这样的特征或方面可以与其他实施方式的一个或多个其他特征或方面组合，如对于任何给定或特定应用而言可以期望和有利的那样。此外，关于术语“包括”、“有”、“具有”或其其他变体在详细描述或权利要求中使用，这样的术语旨在以类似于术语“包含”的方式是包括性的。可以使用术语“耦合”和“连接”连同派生词。应当理解，这些术语可以被用于指示两个元件彼此协作或交互，无论它们是直接物理或电接触，还是它们不彼此直接接触。此外，术语“示例性”仅意指作为示例，而不是最佳的或最优的。因此，下面的详细描述不应被以限制意义理解，并且本发明的范围由所附权利要求限定。
电子器件和用于制作电子器件的方法的实施例可以使用各种类型的半导体芯片或并入在半导体芯片中的电路，其中包括逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS（微机电系统）、功率集成电路、具有集成无源器件的芯片等。实施例也可以使用半导体芯片，该半导体芯片包括MOS晶体管结构或垂直晶体管结构，像例如，IGBT（绝缘栅双极晶体管）结构或者，通常来说，其中至少一个电接触焊盘被布置在半导体芯片的第一主面上并且至少一个其他电接触焊盘被布置在与半导体芯片的第一主面相对的半导体芯片的第二主面上的晶体管或其他结构或器件。
在几个实施例中，层或层堆叠被施加到彼此或者材料被施加或沉积到层上。应当理解，任何如“施加”或“沉积”这样的术语意指字面上涵盖施加层到彼此上的所有种类和技术。尤其是，它们意指涵盖在其中层作为整体被同时施加的技术（像例如，层压技术），以及在其中以顺序的方式沉积层的技术（像例如，溅射、电镀、模制、CVD等）。
半导体芯片可以包括在一个或多个它们的外表面上的接触元件或接触焊盘，其中所述接触元件用于电接触半导体芯片。接触元件可以具有任何期望的形式或形状。它们能够例如具有地面（land）的形式，即半导体芯片的外表面上的平坦接触层。接触元件或接触焊盘可以由任何导电材料制成，例如，由例如金属（比如铝、金、或铜）或金属合金或导电有机材料或者导电半导体材料制成。
在权利要求中和在下面的描述中，用于制作电子器件的方法的不同的实施例尤其在流程图中被描述为过程或措施的特定顺序。要注意的是，实施例不应当限于所描述的特定顺序。不同的过程或措施中特定的一些或所有也能够同时地或以任何其他有用的和适当的顺序被施行。
图1A-C示出用于图示制作电子器件的方法的示例的示意性横截面侧视图表示。
根据图1A，提供第一半导体芯片10，其中第一半导体芯片10包括第一半导体管芯11和施加到第一半导体管芯11的主面的第一焊料互连层12。
参照图1B，提供第二半导体芯片20，其中所述第二半导体芯片20包括第二半导体管芯21、施加到第二半导体管芯的主面的绝缘层22、和施加到绝缘层22的第二焊料互连层23。
参照图1C，第一半导体芯片10利用第一焊料互连层12附接到第一载体31，并且第二半导体芯片20利用第二焊料互连层23附接到第二载体32。
根据图1的方法的示例，第一及第二载体31和32能够是要制作的电子器件40的一部分。根据其示例和把第一和第二半导体芯片10和20附接到第一和第二载体31和32的时间，第一和第二载体31和32能够已经被保持在相对于彼此的固定位置。第一及第二载体31和32可以例如是同一引线框架的一部分。
根据图1的方法的示例，第一半导体管芯11包括在两个相对主面的每一个上的至少一个电接触元件。根据其示例，第一半导体管芯21包括如下各项中的一个或多个：功率晶体管、垂直晶体管、绝缘栅双极（IGB）晶体管和垂直二极管。在IGB晶体管的情况下，第一半导体管芯11的第一上主面可包括源极接触元件和栅极接触元件，并且第一半导体管芯21的第二下主面包括漏极接触元件。
根据图1的方法的示例，第二半导体管芯21包括如下各项中的一个或多个：逻辑集成电路、控制电路、以及配置成控制晶体管的电路。半导体管芯11和21中的一个或两个可以基于Si、GaN或SiC。
根据图1的方法的示例，半导体管芯11和21中的一个或两个包括范围为5 μm至1000 μm的厚度，特别是从30 μm至300 μm，特别是从50 μm至100 μm。
根据图1的方法的示例，第二半导体芯片20的绝缘层22包括范围从0.5 μm到2.5 μm厚度，特别是从1.0 μm到2.0 μm。
根据图1A的方法的示例，第一和第二焊料互连层12和23中的一个或多个包括范围为0.5 μm到1.0 μm的厚度。
根据图1的方法的示例，第一和第二焊料互连层12和23中的一个或两个被形成为同一材料的均匀层。
根据图1的方法的示例，第一和第二焊料互连层12和23中的一个或两个由不同材料的层的堆叠形成。
根据图1的方法的示例，第一和第二焊料互连层12和23被形成类似的或相同的。根据其示例，第一和第二焊料互连层12和23不相同，但包括类似的焊接温度，例如之间的差不高于较高焊接温度的10％的焊接温度。
根据图1的方法的示例，绝缘层包括二氧化硅层。根据其示例，二氧化硅层通过退火或溅射被制作。
根据图1的方法的示例，绝缘层包括绝缘层压板、绝缘箔和绝缘片中的一个或多个。
根据图1的方法的示例，第二焊料互连层23覆盖绝缘层22的整个表面。
根据图1的方法的示例，第二焊料互连层23覆盖绝缘层22的表面以使得在第二半导体管芯21下方的绝缘层22的周缘部不被第二焊料互连层23覆盖。
参照图2A-E，示意性顶视图（A）和横截面侧视图表示（B-E）被示出以图示用于制作半导体芯片以便它能够被附接到载体的方法的示例。
图2A示出了包括多个经处理的半导体管芯210的半导体晶片200的顶视图表示。为简单起见，仅半导体管芯210的上部第一排被描绘。该半导体管芯210意指对应于图1A-C的第二半导体管芯21。
图2B示出在由线BB所指示的平面内半导体晶片200的示意性横截面侧视图表示。该半导体管芯包括具有并入其中的集成电路的上有源表面。半导体管芯210的上表面还可以包括为简单起见未被示出的接触元件或接触焊盘。
图2C示出在把绝缘层220施加到半导体晶片200的背表面上之后的半导体晶片200的横截面侧视图表示，半导体晶片200的背表面与半导体管芯210的有源表面相距遥远。绝缘层220能够由通过退火过程或通过溅射得到的二氧化硅层制成。可替代地，绝缘层220能够由绝缘层压板或箔制成。绝缘层220可以具有范围从1.0 μm至2.0 μm的厚度。
图2D示出在把焊料互连层230施加到绝缘层220的整个表面上之后的半导体晶片200的横截面侧视图表示。焊料互连层230能够由同一材料的均匀层制成，或者可替代地，可以由不同材料的层的堆叠制成。焊料互连层230可以具有范围从0.5 μm至1.0 μm的厚度。
图2E示出单颗化所述半导体晶片200之后得到的分离的半导体芯片240的横截面侧视图表示。可以通过沿锯切道锯切半导体晶片200得到半导体芯片240。
如图2A-E所描绘的，该方法的一个可能的缺点可能是如下事实：在锯切半导体晶片200的过程中，焊料互连层230或者其颗粒可能被拖到绝缘层220的侧面并且甚至半导体管芯210的侧面上或者另外可能到达绝缘层220的侧面并且甚至半导体管芯210的侧面，并且因此可能能够引起漏电流或短路。在下面，方法的另一示例将被示出，利用该示例可能避免该缺点。
图3A-C对应于图2A-C，使得描述在此将不被重复。
图3D示出了在沉积结构化焊料互连层330之后晶片200的横截面侧视图表示。焊料互连层330被结构化以使得它仅覆盖每一个半导体管芯210下方的中央部，使得作为结果，在每一个半导体管芯下方的绝缘层220的周缘部不被焊料互连层330覆盖。
图3E再次示出在单颗化所述半导体晶片200之后的分离的半导体芯片340。能够清楚地看出，焊料互连层330不被施加到绝缘层220的周缘部上。利用这一措施，能够避免焊料互连层330的部分或颗粒被输送或拖到绝缘层220或者甚至半导体管芯210的侧面上。
图4示出根据示例的电子器件的示意性横截面侧视图表示。图4的电子器件400包括：第一载体410、第二载体420、包括在两个相对的主面中的每一个上的至少一个电接触元件（未示出）的第一半导体管芯430、以及包括第一主面和与第一主面相对的第二主面以及第一主面上的至少一个电接触元件（未示出）的第二半导体管芯440。第一半导体管芯430被布置在第一载体410上以使得第一焊料互连层431被设置在第一半导体管芯430的主面之一与第一载体410之间。第二半导体管芯440被布置在第二载体420上使得绝缘层441被施加到第二半导体管芯440的第二主面上，并且第二焊料互连层442被设置在绝缘层441和第二载体420之间。
第一和第二载体410和420以及第一和第二半导体管芯430和440能够嵌入在模制材料450中。此外，第一和第二载体410和420能够是同一引线框架的部分或起源于同一引线框架。第一和第二载体410和420以及第一和第二半导体管芯430和440的接触元件能够连接到外部接触元件460、470和480，它们能够用于将电子器件400连接到印刷电路板（PCB）或任何其他的基板。
图4的电子器件400的另外的示例和实施例能够按照如上面结合图1-3之一详细描述的示例和实施例来形成。
虽然相对于一个或多个实施方式说明了并且描述了本发明，但是在不脱离所附权利要求的精神和范围的情况下，可以对说明的示例做出改变和/或修改。特别是关于由上述部件或结构（组件、器件、电路、系统等）执行的各种功能，用于描述这些部件的术语（包括对“装置”的参考）旨在对应于执行所描述部件的指定功能的任何部件或结构（例如，功能上等效的），即使结构上不等同于在本文中所说明的本发明的示范性实施方式中执行功能的所公开的结构，除非另有说明。

Claims (18)

1.一种用于制作电子器件的方法，包括：
- 提供第一半导体芯片，所述第一半导体芯片包括具有布置在第一半导体管芯的第一主面上的第一电接触元件和布置在所述第一半导体管芯的与所述第一主面相对的第二主面上的第二电接触元件的第一半导体管芯，和被直接地施加到所述第一半导体管芯的所述第二主面和所述第一半导体管芯的所述第二电接触元件的第一焊料互连层；
- 提供第二半导体芯片，所述第二半导体芯片包括具有布置在第二半导体管芯的第一主面上的电接触元件和与所述第一主面相对的没有电接触元件的第二主面的第二半导体管芯、被直接地施加到所述第二半导体管芯的所述第二主面的绝缘层、以及被直接地施加到绝缘层的第二焊料互连层，以使得所述第二焊料互连层通过所述绝缘层与所述第二半导体管芯的整个第二主面分离；
- 直接经由所述第一焊料互连层把所述第一半导体芯片附接到第一载体；以及
- 直接经由所述第二焊料互连层把所述第二半导体芯片附接到第二载体。
2.根据权利要求1所述的方法，其中
所述第一半导体管芯包括如下各项中的一个或多个：功率晶体管、垂直晶体管、绝缘栅双极（IGB）晶体管和垂直二极管。
3.根据前述权利要求之一所述的方法，其中
所述第二半导体管芯包括如下各项中的一个或多个：逻辑集成电路、控制电路以及配置成控制晶体管的电路。
4.根据权利要求1所述的方法，其中
所述绝缘层包括范围为0.5 μm至2 μm的厚度。
5.根据权利要求1所述的方法，其中
第一和第二焊料互连层中的一个或多个包括范围为0.5 μm到1.0μm的厚度。
6.根据权利要求1所述的方法，还包括：
在同一过程步骤中同时附接第一和第二半导体芯片。
7.一种用于将半导体管芯附接到载体的方法，所述半导体管芯包括第一主面、在所述第一主面上的至少一个电接触元件、和与所述第一主面相对的没有任何电接触元件的第二主面，所述方法包括：
把绝缘层直接地施加到半导体管芯的所述第二主面上；
把焊料互连层直接地施加到所述绝缘层上，所述焊料互连层通过所述绝缘层与所述半导体管芯的整个第二主面分离；以及
直接经由所述焊料互连层把所述半导体管芯附接到所述载体。
8.根据权利要求7所述的方法，其中
施加绝缘层包括沉积二氧化硅层。
9.根据权利要求8的方法，其中
沉积二氧化硅层包括退火或溅射。
10.根据权利要求7的方法，其中
施加绝缘层包括施加绝缘层压板、绝缘箔和绝缘片中的一个或多个。
11.根据权利要求7-10之一所述的方法，还包括：
在半导体晶片上提供多个半导体管芯，所述半导体管芯每个均包括第一主面、在所述第一主面上的至少一个电接触元件和与第一主面相对的没有任何电接触元件的第二主面；
把绝缘层直接地施加到半导体管芯的所述第二主面上；以及
把焊料互连层直接地施加到绝缘层上，所述焊料互连层通过所述绝缘层与每个半导体管芯的整个第二主面分离；以及
单颗化所述半导体晶片以得到多个分离的半导体芯片。
12.根据权利要求7至10之一所述的方法，其中
所述绝缘层被施加到半导体晶片的整个主面。
13.根据权利要求11的方法，其中
所述焊料互连层被施加到所述绝缘层的整个主面。
14.根据权利要求11的方法，其中
所述焊料互连层被施加到所述绝缘层，使得在所述半导体管芯中的每一个下方的绝缘层的周缘部不被焊料互连层覆盖。
15.一种电子器件，包括：
第一载体；
第二载体；
第一半导体管芯，包括在两个相对主表面的每一个上的至少一个电接触元件；
第二半导体管芯，包括第一主面、在所述第一主面上的至少一个电接触元件、和与第一主面相对的没有电接触元件的第二主面；
其中第一半导体管芯被布置在第一载体上，使得第一焊料互连层被设置在第一半导体管芯的主面之一和所述第一载体之间；以及
所述第二半导体管芯被布置在第二载体上，使得绝缘层被施加到所述第二半导体管芯的所述第二主面上并且第二焊料互连层被设置在绝缘层和所述第二载体之间，其中所述第二焊料互连层通过所述绝缘层与所述第二半导体管芯的整个第二主面分离。
16.根据权利要求15所述的电子器件，其中
所述第一半导体管芯包括如下各项中的一个或多个：功率晶体管、垂直晶体管、绝缘栅双极（IGB）晶体管和垂直二极管。
17.根据权利要求15或16所述的电子器件，其中
所述第二半导体管芯包括如下各项中的一个或多个：逻辑集成电路、控制电路以及配置成控制晶体管的电路。
18.根据权利要求15-16之一的电子器件，其中
所述绝缘层包括范围为0.5 μm至2.0 μm的厚度。
CN201510720146.8A 2014-10-31 2015-10-30 用于把半导体管芯附接到载体的方法 Active CN105575827B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102014115882.2A DE102014115882B3 (de) 2014-10-31 2014-10-31 Elektronikbauelement und ein Verfahren zum Herstellen eines Elektronikbauelements und ein Verfahren zum Anbringen eines Halbleiter-Die an einem Träger
DE102014115882.2 2014-10-31

Publications (2)

Publication Number Publication Date
CN105575827A CN105575827A (zh) 2016-05-11
CN105575827B true CN105575827B (zh) 2018-11-02

Family

ID=55274141

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510720146.8A Active CN105575827B (zh) 2014-10-31 2015-10-30 用于把半导体管芯附接到载体的方法

Country Status (3)

Country Link
US (1) US9881909B2 (zh)
CN (1) CN105575827B (zh)
DE (1) DE102014115882B3 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622285B2 (en) * 2016-07-08 2020-04-14 Rohm Co., Ltd. Semiconductor device with solders of different melting points and method of manufacturing
US11482491B2 (en) * 2017-11-08 2022-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure with porous conductive structure and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
CN103839842A (zh) * 2012-11-19 2014-06-04 英飞凌科技股份有限公司 用于制造电子元件的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649978B2 (en) * 2001-06-19 2003-11-18 Koninklijke Philips Electronics N.V. Semiconductor module having multiple semiconductor chips
DE10149774A1 (de) * 2001-10-09 2003-04-24 Bosch Gmbh Robert Verfahren zum Verpacken von elektronischen Baugruppen und Mehrfachchipverpackung
US8110906B2 (en) * 2007-01-23 2012-02-07 Infineon Technologies Ag Semiconductor device including isolation layer
US7799614B2 (en) 2007-12-21 2010-09-21 Infineon Technologies Ag Method of fabricating a power electronic device
WO2011108308A1 (ja) * 2010-03-04 2011-09-09 日本電気株式会社 半導体素子内蔵配線基板
US8816500B2 (en) 2012-12-14 2014-08-26 Infineon Technologies Ag Semiconductor device having peripheral polymer structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
CN103839842A (zh) * 2012-11-19 2014-06-04 英飞凌科技股份有限公司 用于制造电子元件的方法

Also Published As

Publication number Publication date
US9881909B2 (en) 2018-01-30
US20160126227A1 (en) 2016-05-05
DE102014115882B3 (de) 2016-02-25
CN105575827A (zh) 2016-05-11

Similar Documents

Publication Publication Date Title
CN110491856B (zh) 基板结构和制造方法
CN103390601B (zh) 晶片封装体及其形成方法
US11309277B2 (en) Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
SG121104A1 (en) A method of stacking thin substrates by transfer bonding
CN106206509B (zh) 电子封装件及其制法与基板结构
CN109616458A (zh) 贯通电极基板及利用贯通电极基板的半导体装置
US10861775B2 (en) Connecting clip design for pressure sintering
SG162682A1 (en) Manufacturing method for semiconductor devices
CN108074904A (zh) 电子封装件及其制法
CN105575827B (zh) 用于把半导体管芯附接到载体的方法
CN103871914B (zh) 制作层堆叠的方法
CN105870087B (zh) 基板结构
CN105659379B (zh) 具有嵌入式管芯的模制引线框架封装
US9721900B2 (en) Semiconductor package and its manufacturing method
US9365415B2 (en) Compact electronic package with MEMS IC and related methods
CN109964312B (zh) 半导体元件安装用基板端子板的制造方法
US9408301B2 (en) Substrate structures and methods of manufacture
US8525321B2 (en) Conductive chip disposed on lead semiconductor package
CN106158759B (zh) 电子封装件及其制法
JP6149476B2 (ja) 半導体装置の製造方法
CN107546138A (zh) 半导体器件及其制造方法
US7601560B2 (en) Method for producing an electronic circuit
TWI249214B (en) Assembly process
TW502413B (en) Semiconductor chip encapsulation structure with passive device
JP2007180513A5 (zh)

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant