CN105870087B - 基板结构 - Google Patents
基板结构 Download PDFInfo
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- CN105870087B CN105870087B CN201510025409.3A CN201510025409A CN105870087B CN 105870087 B CN105870087 B CN 105870087B CN 201510025409 A CN201510025409 A CN 201510025409A CN 105870087 B CN105870087 B CN 105870087B
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- metal layer
- board structure
- layer
- structure according
- insulating layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims description 19
- 238000007789 sealing Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- -1 abbreviation PDM) Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- PMPVIKIVABFJJI-UHFFFAOYSA-N Cyclobutane Chemical compound C1CCC1 PMPVIKIVABFJJI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structure Of Printed Boards (AREA)
Abstract
一种基板结构,包括:定义有布线区、邻接该布线区的密封体、及邻接该密封体的切割区的基板本体、形成于该布线区的线路层、形成于该布线区与该线路层上的绝缘层、以及形成于该绝缘层与该布线区上的金属层,藉由该金属层的设计,以避免该绝缘层发生分层。
Description
技术领域
本发明涉及一种半导体结构,尤指一种提升可靠度的基板结构。
背景技术
随着电子产业的蓬勃发展,电子产品也逐渐迈向多功能、高性能的趋势。目前应用于晶片封装领域的技术,例如晶片尺寸构装(Chip Scale Package,简称CSP)、晶片直接贴附封装(Direct Chip Attached,简称DCA)或多晶片模组封装(Multi-Chip Module,简称MCM)等覆晶型态的封装模组、或将晶片立体堆迭化整合为三维积体电路(3D IC)晶片堆迭技术等。
图1为现有半导体基板的剖面示意图,且图1’为对应图1的上视示意图。
如图1及图1’所示,现有半导体基板1为晶圆,其包括:一基板本体10、一线路层11以及一绝缘层12。
所述的基板本体10定义有多个布线区100、邻接该布线区100的密封体101、及邻接该密封体101的切割区102。于沿该切割区102进行切单制程时,该基板本体10表面有时会产生裂缝,此裂缝会沿着该基板本体10表面朝该布线区100的方向裂开,所以藉由该密封体101的阻挡效果,以避免该裂缝延伸至该布线区100。
所述的线路层11形成于部分该布线区100上,且该线路层11具有多个电性连接垫110。
所述的绝缘层12形成于部分该布线区100与该线路层11上,且令该些电性连接垫110外露于该绝缘层12。后续可于该些电性连接垫110上形成一凸块底下金属层(UnderBump Metallurgy,简称UBM)14,以于后续制程形成如焊锡材料或金属凸块等的导电元件(图略)于该凸块底下金属层14上。
惟,现有半导体基板1中,该基板本体10与该绝缘层12两者的接触面积极大,且两者的热膨胀系数(Coefficient of thermal expansion,简称CTE)具有差异,所以于进行热处理制程期间(thermal cycle),该半导体基板1难以均匀释放热应力(thermal stress),所以当该绝缘层12受应力时,该绝缘层12容易与该基板本体10发生分层(delamination),导致该半导体基板1容易发生翘曲(warpage)的问题。
此外,于切单制程的过程中时,虽然该密封体101具有阻挡的效果,但有时裂缝仍会破坏该密封体101而延伸至该布线区100,导致该线路层11损坏。
因此,如何克服现有技术的种种缺失,实为一重要课题。
发明内容
为克服现有技术的种种缺失,本发明提供一种基板结构,以避免该绝缘层发生分层。
本发明的基板结构,包括:一基板本体,其定义有至少一布线区、邻接该布线区的密封体、及邻接该密封体的切割区;一线路层,其形成于该基板本体的布线区的部分表面上;一绝缘层,其形成于该基板本体的布线区的部分表面与该线路层上;以及一金属层,其形成于该绝缘层与该基板本体的布线区的部分表面上。
前述的基板结构中,该密封体环绕该布线区。
前述的基板结构中,该密封体为栅栏状或环圈状。
前述的基板结构中,该线路层具有多个电性连接垫,令该些电性连接垫外露于该绝缘层。还包括一形成于该些电性连接垫上的凸块底下金属层。例如,该凸块底下金属层与该金属层的材质为相同或不相同、该凸块底下金属层与该金属层的厚度为相同或不相同。
前述的基板结构中,该金属层未接触该线路层。
前述的基板结构中,该金属层接触该密封体、或未接触该密封体。
另外,前述的基板结构中,还包括一介电层,其形成于该绝缘层与该基板本体之间。例如,该绝缘层的材质与该介电层的材质可相同或不相同。
由上可知,本发明的基板结构,藉由在该基板本体表面与该绝缘层上形成一金属层,以增加该基板本体与该绝缘层之间的结合力,避免该绝缘层发生分层的情况。
此外,于切单制程的过程中时,该金属层能避免该基板本体的切割区的裂缝延伸至该布线区,因而能避免该线路层损坏,进而提高产品良率。
附图说明
图1为现有半导体基板的剖面示意图;
图1’为对应图1的上视示意图;
图2为本发明基板结构的剖面示意图;
图2’为对应图2的上视示意图;以及
图3为本发明基板结构的另一实施例的剖面示意图。
符号说明
1 半导体基板 10,20 基板本体
100,200 布线区 101,201,301 密封体
102,202 切割区 11,21 线路层
110,210 电性连接垫 12,22 绝缘层
14,24 凸块底下金属层 2,3 基板结构
220 开孔 23,33 金属层
35 介电层 350 开口
D 间距 t1,t2 厚度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用于配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用于限定本发明可实施的限定条件,所以不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”及“ㄧ”等用语,也仅为便于叙述的明了,而非用于限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2为本发明基板结构的剖面示意图,且图2’为对应图2的上视示意图。
如图2及图2’所示,所述的基板结构2包括:一基板本体20、一线路层21、一绝缘层22以及一金属层23。
所述的基板本体20定义有多个布线区200、邻接该布线区200的密封体201、及邻接该密封体201的切割区202。
于本实施例中,该基板本体20的种类繁多,例如,具硅穿孔(Through-siliconvia,简称TSV)的中介板、硅中介板(Through Silicon interposer,简称TSI)或半导体晶圆等半导体板材。于其它实施例中,该基板本体的内部可包含介电层(图略)与内部线路(图略),且该内部线路可选择性地电性连接该电性连接垫。因此,该基板本体的构造并无特别限制。
此外,该密封体201为栅栏状并环绕该布线区200。
所述的线路层21形成于该基板本体20的布线区200的部分表面上及基板本体20内,且该线路层21具有多个电性连接垫210。
所述的绝缘层22形成于该基板本体20的布线区200的部分表面与该线路层21上,且该绝缘层22具有多个开孔220,以令该些电性连接垫210外露于该绝缘层22的开孔220。
于本实施例中,形成该绝缘层22的材质为氮化硅(SiNX)、氧化硅(SiO2)、光阻介电材(photosensitive dielectric material,简称PDM)、聚酰亚胺(polyimide,简称PI)、苯并环丁烯(Bis-Benzo-Cyclo-Butene,简称BCB)、聚对二唑苯(Polybenzoxazole,简称PBO)、环氧树脂(epoxy)或硅胶等。
此外,可于该些开孔220的电性连接垫210上形成一凸块底下金属层(UBM)24,以于后续制程形成如焊锡材料或金属凸块等的导电元件(图略)于该凸块底下金属层24上。
又,形成该凸块底下金属层24的材质不限,例如Ti/Cu、Ti/Cu/Ni、Cu/Ni、Cu/Ni/Au或Al/NiV/Cu。
另外,该绝缘层22与该密封体201之间保持间距D,使该布线区200的边缘没有该绝缘层22。
所述的金属层23形成于该绝缘层22与该基板本体20的布线区200的部分表面上,且该金属层23未接触该线路层21。
于本实施例中,该凸块底下金属层24与该金属层23可同时或非同时形成。例如,先形成该凸块底下金属层24,再形成该金属层23;或先形成该金属层23,再形成该凸块底下金属层24。较佳为同时形成该凸块底下金属层24与该金属层23,因而无需增加制程及成本。
此外,该凸块底下金属层24与该金属层23的材质或厚度t1,t2可相同或不同。例如,该凸块底下金属层24的材质为Al/NiV/Cu,该金属层23的材质为Cu。
又,该金属层23的一侧覆盖部分该绝缘层22,而另一侧接触该密封体201,藉此强化该绝缘层22与该基板本体20间的结合力,且使该金属层23具有延续该密封体201阻挡裂缝的效果,以避免于沿该切割区202切单时该基板本体20表面的裂痕延伸至该布线区200。
另外,该金属层23环绕该绝缘层22而成为金属框,且布满该间距D。
图3为本发明基板结构的另一实施例的剖面示意图。本实施例与上述实施例的差异在于新增介电层及密封体的实施例。
如图3所示,该金属层33未接触该密封体301但仍环绕该绝缘层22而成为金属框,且该密封体301为环圈状,又该基板结构3还包括形成于该绝缘层22与该基板本体20之间的一介电层35。
于本实施例中,先形成该介电层35于部分该布线区200与该线路层21上,且该介电层35具有多个开口350,以令该些电性连接垫210外露于该些开口350。之后形成该绝缘层22于部分该布线区200与该介电层35上,且令该些电性连接垫210外露于该绝缘层22的开孔220。
此外,形成该介电层35的材质为氮化硅(SiNX)、氧化硅(SiO2)、光阻介电材(photosensitive dielectric material,简称PDM)、聚酰亚胺(polyimide,简称PI)、苯并环丁烯(Bis-Benzo-Cyclo-Butene,简称BCB)、聚对二唑苯(Polybenzoxazole,简称PBO)、环氧树脂(epoxy)或硅胶等。
又,该绝缘层22的材质与该介电层35的材质可相同或不相同。
综上所述,本发明的基板结构2,3藉由在该基板本体20表面与该绝缘层22上形成一金属层23,以增加该基板本体20与该绝缘层22之间的结合力,避免该绝缘层22发生分层(delamination)的情况。
此外,于切单制程的过程中时,该金属层23能避免该基板本体20的切割区202的裂缝延伸至该布线区200,因而能避免该线路层21损坏,进而提高产品良率。
上述实施例仅用于例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (14)
1.一种基板结构,其特征为,该基板结构包括:
一基板本体,其定义有至少一布线区、邻接该布线区的密封体、及邻接该密封体的切割区;
一线路层,其形成于该基板本体的布线区的部分表面上;
一绝缘层,其形成于该基板本体的布线区的部分表面与该线路层上;以及
一金属层,其形成于该绝缘层与该基板本体的布线区的部分表面上,且该金属层接触或未接触该密封体。
2.根据权利要求1所述的基板结构,其特征为,该密封体环绕该布线区。
3.根据权利要求1所述的基板结构,其特征为,该密封体为栅栏状。
4.根据权利要求1所述的基板结构,其特征为,该密封体为环圈状。
5.根据权利要求1所述的基板结构,其特征为,该线路层具有多个电性连接垫,且该些电性连接垫外露于该绝缘层。
6.根据权利要求5所述的基板结构,其特征为,该基板结构还包括一形成于该些电性连接垫上的凸块底下金属层。
7.根据权利要求6所述的基板结构,其特征为,该凸块底下金属层与该金属层的材质为相同。
8.根据权利要求6所述的基板结构,其特征为,该凸块底下金属层与该金属层的材质为不相同。
9.根据权利要求6所述的基板结构,其特征为,该凸块底下金属层与该金属层的厚度为相同。
10.根据权利要求6所述的基板结构,其特征为,该凸块底下金属层与该金属层的厚度为不相同。
11.根据权利要求1所述的基板结构,其特征为,该金属层未接触该线路层。
12.根据权利要求1所述的基板结构,其特征为,该基板结构还包括一介电层,其形成于该绝缘层与该基板本体之间。
13.根据权利要求12所述的基板结构,其特征为,该绝缘层的材质与该介电层的材质为相同。
14.根据权利要求12所述的基板结构,其特征为,该绝缘层的材质与该介电层的材质为不相同。
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US20160190039A1 (en) | 2016-06-30 |
US9515007B2 (en) | 2016-12-06 |
CN105870087A (zh) | 2016-08-17 |
TWI555145B (zh) | 2016-10-21 |
TW201624646A (zh) | 2016-07-01 |
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