CN103839842A - 用于制造电子元件的方法 - Google Patents
用于制造电子元件的方法 Download PDFInfo
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- CN103839842A CN103839842A CN201310757117.XA CN201310757117A CN103839842A CN 103839842 A CN103839842 A CN 103839842A CN 201310757117 A CN201310757117 A CN 201310757117A CN 103839842 A CN103839842 A CN 103839842A
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Abstract
用于制造电子元件的方法。提供一种载体和一种半导体芯片。连接层被施加到该半导体芯片的第一主面。该连接层包括多个凹陷部。填料被施加到该连接层或该载体。该半导体芯片被附着到该载体,使得该连接层被设置于该半导体芯片和该载体之间。该半导体芯片被附接到该载体。
Description
技术领域
本发明涉及一种用于制造电子元件的方法以及一种电子元件。
背景技术
在很多电子元件中半导体芯片必须安装在载体上,特别是类似例如引线框的导电载体。重要的是,半导体芯片和载体之间的连接具有高可靠性以及展示出高的电导率和热导率。然而,在将半导体芯片安装到载体的过程期间和之后,根据所应用的固定技术,可能会出现问题。所述问题可能例如由于半导体材料和载体材料的不同的热膨胀系数(其可能导致热机械应力)而产生。在较薄的半导体芯片的情况下,这些应力反应可能甚至导致半导体芯片的微观损伤,如形成裂纹。在其他情况中,这种应力可导致半导体基板的强烈变形,使得接下来的工艺步骤不再可能进行,比如例如激光钻孔、层压、线结合等。总的来说,半导体芯片中产生的应力严重地影响了接下来的工艺步骤的可靠性。因此,需要一种能够在半导体芯片和具有高的电导率和热导率的载体之间提供稳定和永久可靠的连接的互连技术。
附图说明
附图被包括用以提供对实施例的进一步的理解并且被并入和构成该说明书的一部分。这些图示出实施例并且与描述一起用来解释实施例的原理。将容易领会其它实施例和实施例的多个预期的优点,因为参考以下详细描述它们将变得更好理解。这些图的元件不一定相对于彼此按比例。相似的参考数字表示相应的相似部分。
图1示出了根据一个实施例制作电子元件的方法的流程图;
图2A和2B,共同为图2,示出了一种带有接触柱的半导体芯片的示意生的截面侧视图表示(图2A)和俯视图(down view)表示(图2B),用以说明根据一个实施例的制作电子元件的方法;
图3示出了在接触柱之间的中间空间中填充填充材料之后的图2的组件的示意性截面侧视图表示;
图4示出了将图3的组件附着到引线框上之后所获得的电子元件的示意性截面侧视图表示;
图5示出了根据一个实施例的电子元件的示意性截面侧视图表示;和
图6示出了根据一个实施例的电子元件的示意性截面侧视图表示。
具体实施方式
现在参照各图描述各方面和实施例,其中从头到尾相似的参考数字通常用来指代相似的元件。在下面的描述中,为了解释的目的,许多特定的细节被阐述以便提供对实施例的一个或多个方面的透彻理解。然而,对于本领域技术人员来说,可以显然的是实施例的一个或多个方面可以以更少程度的特定细节来被实施。在其它实例中,以示意的形式示出已知结构和元件以便便于描述实施例的一个或多个方面。应该理解在不脱离本发明的范围的情况下,可以利用其它实施例并且可以作出结构或逻辑变化。应该进一步注意到各图不是按比例或者不必要按比例。
另外,虽然可以相对于几个实施方式中的仅一个来公开实施例的特定特征或方面,但是在对于任何给定的或特定的应用可以是所需的和有利的时,这样的特征或方面可以与其它实施方式的一个或多个其它特征或者方面相结合。此外,就在详细的描述或者权利要求中使用的术语“包括”,“具有”,“有”或者其其它变体来说,这样的术语以与术语“包含”相似的方式旨在是包括一切的(inclusive)。可以使用术语“耦合”和“连接”以及派生词。应该理解这些术语可以被用来表示两个元件互相协作或互相作用,不管它们是直接物理或电接触,还是它们不是互相直接接触。而且,术语“示例性的”仅意指作为示例,而不是最好的或最佳的。因此,下面详细的描述不是在限制性意义上来进行的,并且本发明的范围被所附权利要求限定。
电子元件和制造电子元件的方法的实施例可使用多种类型的半导体芯片或集成在半导体芯片中的电路,在它们之中有逻辑集成电路,模拟集成电路,混合信号集成电路,传感器电路,MEMS(微机电系统),功率集成电路,具有集成无源器(integrated passives)的芯片等。实施例也可以使用半导体芯片,所述半导体芯片包括MOS晶体管结构或者垂直晶体管结构,比如例如,IGBT(绝缘栅双极晶体管)结构或者通常是其中至少一个电接触焊盘被布置在半导体芯片的第一主面上并且至少一个其它电接触焊盘被布置在与半导体芯片的第一主面相对的半导体芯片的第二主面上的晶体管或其它结构或器件。
在几个实施例中,层或者层堆叠被施加到彼此或者材料被施加或者沉积到层上。应该领会到任何这样的术语如“被施加”或者“被沉积”意味着字面上覆盖将层施加到彼此之上的所有种类和技术。特别地,它们意味着覆盖其中各层作为整体被同时施加的技术,比如,例如层压技术以及其中层以顺序的方式被沉积的技术,比如,例如溅射,电镀,模塑,CVD等。
半导体芯片可以包括在其外表面的一个或多个上的接触元件或接触焊盘,其中接触元件用于电接触半导体芯片。接触元件可以具有任何所需的外形或形状。它们可以例如具有接触面(land)的形式,即在半导体芯片的外表面上的平的接触层。可以由任何导电材料,例如由金属(诸如如铝,金,或铜)或者金属合金,或者导电有机材料,或者导电半导体材料来制成接触元件或者接触焊盘。
在权利要求中并且在下面的描述中,尤其在流程图中,用于制作电子元件的方法的不同实施例被描述为特定顺序的工艺或者测量。应该注意到实施例不应被限制到描述的特定顺序。不同工艺或者测量的特定的一些或者全部也可以同时地或者以任何其它有益的和适当的顺序来进行。
参见图1,示出了一种用于制造电子模块的方法的流程图。图1中的方法100包括提供载体(110),提供半导体芯片(120),将连接层施加到所述半导体芯片的第一主面,所述连接层包括多个凹陷部(130),施加填充材料到连接层或载体(140),利用连接层将所述半导体芯片附着到所述载体(150),并施加热、压力和超声中的一个或多个来将所述半导体芯片固定到所述载体(160)。
所述填充材料可直接填充在连接层的凹陷部中,或其可以被施加到在连接层之间限定凹陷部的柱上面的连接层上,或其可以被施加到载体。由于随后的处理,所述填充材料可以流进凹陷部中,使得凹陷部可以完全被所述填充材料填充。
根据图1的方法100的实施例,所述载体是由导电材料构成的。具体地,所述载体可由引线框或任何其他金属载体构成。所述载体也可由在其主面上具有金属化区域的绝缘材料或印刷电路板(PCB)或任何其他基板构成。
根据图1的方法100的实施例,所述半导体芯片包括第一主面和与第一主面相对的第二主面,其中至少一个电接触焊盘被布置在第一主面上,并且至少一个电接触焊盘被布置在第二主面上。根据其实施例,所述半导体芯片包括垂直晶体管结构,比如,例如,IGBT(绝缘栅双极晶体管)结构。
根据图1的方法100的实施例,所述半导体芯片可包括任何种类的电子器件或并入在半导体芯片中的电路,特别是逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS(微机电系统)、功率集成电路、晶体管(比如例如MOS晶体管、功率晶体管、IGBT晶体管或垂直晶体管)中的一个或多个。
根据图1的方法100的实施例,所述连接层的凹陷部可以具有任何想要的外形和形状。特别地,凹陷部可具有相同的外形和形状,或它们可在外形和形状上不同,其中多个凹陷部的一部分也可以在外形和形状上相同。所述凹陷部或它们的一部分可以具有深度使得它们透过所述层直到半导体芯片的第一主面为止,或者所述凹陷部或它们的一部分可以具有深度使得它们不透过所述层直到所述半导体芯片的第一主面。所述凹陷部或它们的一部分可以具有垂直侧壁。所述凹陷部可以具有矩形截面。所述柱的布局也可以被调整到载体的布局,例如,凸块尖端(bump tip)可以为平面载体限定至少一个平面。
根据图1的方法100的实施例,所述凹陷部可由连接层的柱来限定,其中所述凹陷部由柱之间的中间空问构成。例如,所述柱可以具有在从5μm-50μm范围内的横向尺寸和在从10μm-30μm范围内的高度。柱之间的距离可以在从5μm-50μrn范围内。可以选择柱的尺寸和柱之间的距离,使得由柱之间的中间空间形成的凹陷部可以是邻接的或是不邻接的。根据一个例子,柱和它们之间的中间空间被形成为规则图案,特别是方格图案,在这种情况下所述柱和它们之间的中间空间占据相同的空间体积,或者在非常多的柱或大面积柱的情况下,随着柱之间的间距的增加,所述柱可以占据总面积的仅一小部分。
根据图1的方法100的实施例,通过将连接基层施加到所述半导体芯片的主面上并且然后去除连接基层的预定部分来产生所述连接层。所述连接基层的预定部分可通过激光结构化或通过蚀刻来去除。
根据图1的方法100的实施例,所述连接基层可由导电材料构成,如例如铜或任何其他金属材料。
根据图1的方法100的实施例,所述连接基层可由绝缘材料构成。
根据图1的方法100的实施例,包含多个凹陷部的所述连接层可以由光刻方法或剥离方法制制造。
根据图1的方法100的实施例,所述填充材料由下述中的一个或多个构成:可热收缩的材料、导电材料、绝缘材料、聚合物材料、粘合剂材料,和作为填充有颗粒的主材料的以上所提到的材料中的任一个,特别是导电颗粒、绝缘颗粒、以及微米颗粒或纳米颗粒中的一种或多种。
根据图1中的方法100的实施例,该半导体芯片由半导体晶片的半导体芯片区域构成,其中该半导体晶片包括多个半导体芯片区域。该多个半导体芯片区域可包括共用的第一主面。该连接层可在晶片级基础上被施加,以及特别地,向凹陷部中填充填充材料也可在晶片级基础上进行。然后,该半导体晶片被分离成单独的半导体芯片。其中一个半导体芯片可然后如前述那样附着到载体并固定到该载体。
参考图2-4,示出了用于说明用于制作电子元件的方法的示意图。图2A和2B示出了半导体芯片200和施加到该半导体芯片200的连接层250的截面图(A)和俯视图(B)。图2A是沿图2B中的A-A线的截面图。该半导体芯片200可由例如硅芯片构成,并可进一步地由具有设置在该半导体芯片200的第一主面上的第一接触层210和设置在与该第一主面相对的第二主面上的第二和第三接触层220和230的芯片构成。该半导体芯片200可例如由垂直晶体管芯片(比如例如IGBT(绝缘栅双极晶体管))构成。该第一、第二和第三接触层210、220和230可以是IGBT的漏极、源极和栅极接触层。该半导体芯片200可具有在从50μm-800μm的范围内的厚度,特别是在从50μrn-300μm的范围内,特别是在从50μm-100μm的范围内。该半导体芯片200可以是单独的半导体芯片或者是半导体晶片内的半导体芯片区域。
该连接层250可由规则的接触柱阵列251以及这些接触柱251之间的中间空间(凹陷部)252构成。如图2B中所示,接触柱251和中间空间252的布置可以是棋盘图案的布置,这意味着接触柱251的总数和中间空间252的总数占据同样的空间体积。在图2B中所示的实施例中,中间空间252彼此分开。然而,也可以是这种情况,即接触柱251在彼此之间具有较小的横向尺寸或较大的距离,使得接触柱251之间的中间空间252彼比连接并在管芯接触柱251之间形成邻接的空的空间。接触柱251可具有矩形截面和垂直侧壁,以及中间空间252也可具有矩形截面和垂直侧壁。柱251也可具有任何其他所需的形状,如Y-,U-,I-或X-状形状,以及也可具有非垂直侧壁,优选是相对平面有超过90°的角度的那些侧壁。接触柱251可具有宽度,即在从5μn-50μm的范围内的侧面边缘长度和在从5μm-30μm的范围内的高度。接触柱251可由金属材料制成,比如例如铜。它们可通过沉积铜层以及然后通过例如光刻技术和蚀刻去除预定的部分来制造。预定的部分被预期成为中间空间252。作为替换,也可通过掩模来沉积该铜层,其中该掩模的掩蔽部分限定没有铜将被沉积的区域,即与中间空间252对应的区域。
参考图3,示出了在沉积填充材料300到中间空间252中之后如图2A所示的组件的示意截面图。填充材料300可以是下述中的一种或多种:可热收缩的材料、导电材料、绝缘材料、粘合剂材料、聚合物材料、不导电膏剂(NCP)、不导电箔、和任何种类的填充有颗粒的主材料,特别是导电颗粒或绝缘颗粒,特别是微米或纳米颗粒。填充材料可以,特别地,由固有导电聚合物构成,比如例如掺杂或不掺杂的聚噻吩(polythiophen)(聚3,4d乙撑二氧噻吩(Poly-(3,4-ethylendioxythiopen)),其可填充有导电或绝缘颗粒。填充材料300可根据填充材料300的种类和性质通过不同的方法和技术来沉积。填充材料300可以例如通过旋涂、层压、印刷或利用刮刀或刮板进行涂覆而被填充到中间空间252之中或之上。
参考图4,示出了在将其附着到载体400(比如例如引线框)之后图3的组件的截面图。引线框400可例如由铜或铜合金制成。引线框400可包括第-上表面410和与该上表面410相对的第二下表面420。引线框400可在其整个表面处或仪在连接电子元件所在的第一表面410上具有银或镍镀层,其厚度在从500nm-5μm的范围内。
图3所示的包括半导体芯片200、连接层250和填充材料300的组件被附着到引线框400的第一表面410。然后可以施加压力、热和超声中的一种或多种以便将半导体芯片固定到引线框400,使得最初只在半导体芯片200、连接层250、填充材料300和引线框400之间建立适形连接(form fit connection)。可以从上方和下方施加压力来将半导体芯片200和引线框400压在一起,以及可施加在100℃-250℃,或150℃-200℃范围内的温度达1-10分钟来将连接层250的下表面和填充材料300固定到引线框400的上表面。作为对热处理的替换或者除了热处理之外,超声辐射可指向半导体芯片200和引线框400之间的接合点。
如上所述的这种处理的结果将是,在填充材料300和接触柱251之间、在填充材料300和引线框400之间、以及在接触柱251和引线框400之间产生粘性结合。由于填充材料的性质,填充材料300的热收缩性是不可逆转的,使得在这些元件之间的粘性结合将是稳定的和永久可靠的。在半导体芯片的电子器件的操作中,特别是垂直晶体管,由于施加的电压、以及因电扩散和电迁移以及所得到的从接触接合点中的任一个的一侧到另一侧的原子扩散导致的流过接触的电流,粘性结合可甚至被进一步增强。而且,填充材料300可用作针对可能出现在连接层(即接触柱251)中的机械诱发裂纹或裂缝的屏障。因此,不仅在连接的稳定性方面有优势,而且在由基于焊料的接触化所产生的电迁移方面也有优势。
参考图5,示出了根据一个实施例的电子元件的示意截面侧视图。电子元件500包括载体510、包括主面521和在后表面处的第一接触层522的半导体芯片520、施加到半导体芯片520的主面521的接触层530、包括多个凹陷部531的连接层530、设置于凹陷部531内的填充材料540,其中连接层530设置于半导体芯片520和载体510之间。
该电子元件可具有如上面结合制作方法描述的任何进一步的特征。以下仅描述几个重要特征。
根据图5的电子元件500的一个实施例,载体510由导电材料构成。特别地,载体510可包括引线框或任何其它的金属载体。载体510也可包括在其主面上具有金属化区域的绝缘材料或印刷电路板(PCB)或任何其它基板。
根据图5的电子元件500的一个实施例,半导体芯片520包括第一主面和与该第一主面相对的第二二主面,其中至少一个电接触焊盘被布置在该第一主面上,以及至少一个电接触焊盘被布置在该第二主面上。根据其一个实施例,半导体芯片520包括垂直晶体管结构,比如例如,IGBT(绝缘栅双极晶体管)结构。
根据图5的电子元件500的一个实施例,半导体芯片520可包括任何种类的电子器件或并入在半导体芯片中的电子电路,在它们之中有逻辑集成电路、模拟集成电路、混合信号集成电路、传感器电路、MEMS(微机电系统)、功率集成电路、晶体管,比如例如MOS晶体管、IGBT晶体管或垂直晶体管。
根据图5的电子元件500的一个实施例,连接层530的凹陷部531可以具有任何所需的外形和形状。特别地,凹陷部531可具有相同的外形和形状,或者它们可以在外形和形状方面是不同的,其中该多个凹陷部531中的一部分也可在外形和形状方面是相同的。凹陷部531或其一部分可以具有深度,使得它们穿过层530直到半导体芯片520的第一主面521,或者凹陷部531或其一部分可具有深度,使得它们不穿过层530直到半导体芯片520的第一主面521。凹陷部531或其一部分可具有垂直侧壁。凹陷部531可具有矩形截面。
根据图5的电子元件500的一个实施例,凹陷部531可由层530的柱550来限定,其中凹陷部531由柱550之间的中间空间构成。例如,柱550可具有在5μn-50μn范围内的横向尺寸和在10μm-30μm范围内的高度。柱550之间的距离可以在5μm-50μm范围内或更大。可以选择柱550的尺寸和柱550之间的距离,使得由柱550之间的中间空间形成的凹陷部531可以是邻接的或不邻接的。根据一个例子,柱550以及它们之间的中间空间可以形成为规则的图案,特别是方格图案,在这种情况下,柱550和它们之间的中间空间占据相同的空间体积。根据一个实施例,由柱550所占据的面积与总面积相比小得多。
根据图5的电子元件500的一个实施例,连接层530或柱550可由导电材料构成,比如例如铜或任何其它金属材料。
根据图5的电子元件500的一个实施例,连接层530或柱550可由绝缘材料构成。
根据图5的电子元件500的一个实施例,包括多个凹陷部的连接层530可由光刻方法或剥离方法制造。
根据图5的电子元件500的一个实施例,填充材料540由下述中的一种或多种构成:可热收缩的材料、导电材料、绝缘材料、聚合物材料、粘合剂材料、和作为填充有颗粒的主材料的以上所提到的材料中的任一个,特别是导电颗粒、绝缘颗粒、以及微米颗粒或纳米颗粒中的一种或多种。
参考图6,示出了根据一个实施例的电子元件的示意性截面侧视图。图6的电子元件600是图5的电子元件500的进一步开发。至于使用相同的参考标记,这里不再重复相应元件的描述。电子元件600另外包括在半导体芯片520的前表面上的第二和第三接触层523和524,其中另一连接层560被施加到接触层523和524。连接层560可以以与连接层530相同的方式来形成,即,通过包含由柱580限定的凹陷部570。在稍后阶段中,连接元件可以以与如上所述用于半导体芯片的背面相同的方式通过使用填充材料连接到连接层560。
虽然已经相对于一个或多个实施方式示出和描述了本发明,但是在不脱离所附权利要求的精神和范围的情况下,可以作出对图示示例的改变和域修改。尤其关于由上面描述的部件或结构(组件,器件,电路,系统等)所执行的各种功能,除非另外表明,用来描述这种部件的术语(包括对“装置”的引用)旨在对应于执行所描述部件的指定功能的任何部件或结构(例如,其是功能上等同的),即使结构上不等同于执行本发明于此示出的示例性实施方式中的功能的公开结构。
Claims (27)
1.一种用于制作电子元件的方法,该方法包括:
提供载体;
提供半导体芯片;
施加连接层到该半导体芯片的第一主面,该连接层包括多个凹陷部;
施加填充材料到该连接层或到该载体;
将该半导体芯片附着到该载体,使得该连接层位于该半导体芯片和该载体之间;以及
施加热和压力中的一个或多个以将该半导体芯片固定到该载体。
2.根据权利要求1所述的方法,其中施加该连接层包括施加一层到该半导体芯片的第一主面并去除该层的预定部分。
3.根据权利要求2所述的方法,其中去除预定部分包括通过激光结构化或蚀刻来去除所述预定部分。
4.根据权利要求1所述的方法,其中凹陷部彼此具有相同外形、相同尺寸和相同距离中的一种或多种。
5.根据权利要求1所述的方法,其中该填充材料包括可热收缩的材料。
6.根据权利要求1所述的方法,其中该填充材料包括导电材料。
7.根据权利要求1所述的方法,其中该填充材料包括绝缘材料。
8.根据权利要求1所述的方法,其中该填充材料包括粘合剂材料。
9.根据权利要求1所述的方法,其中该填充材料包括填充有导电颗粒的主材料。
10.根据权利要求1所述的方法,其中:
提供该半导体芯片包括提供半导体晶片;
该半导体晶片包括多个芯片区域;
该连接层被施加到该半导体晶片的第一主面;
该填充材料被填充到凹陷部中;以及
该方法还包括将晶片分离成单独的半导体芯片。
11.一种用于制作电子元件的方法,该方法包括:
提供载体;
提供包括多个芯片区域的半导体晶片;
施加连接层到该半导体晶片的第一主面,该连接层包括多个凹陷部;
用填充材料填充凹陷部;
将该晶片分离成单独的半导体芯片;以及
将具有主面的半导体芯片中的一个附着到该载体。
12.根据权利要求11所述的方法,还包括施加热、压力和超声中的一种或多种以将该半导体芯片固定到该载体。
13.一种电子元件,包括:
载体;
具有第一主面的半导体芯片;
施加到该半导体芯片的第一主面的连接层,该连接层包括多个凹陷部;
该连接层设置在该半导体芯片和该载体之间;以及
设置在该载体和该连接层之间的填充材料。
14.根据权利要求13所述的电子元件,其中凹陷部彼此具有相同外形、相同尺寸和相同距离中的一种或多种。
15.根据权利要求13所述的电子元件,其中该填充材料由可热收缩的材料构成。
16.根据权利要求13所述的电子元件,其中该填充材料包括导电材料。
17.根据权利要求13所述的电子元件,其中该填充材料包括绝缘材料。
18.根据权利要求13所述的电子元件,其中该填充材料包括粘合剂材料。
19.根据权利要求13所述的电子元件,其中该填充材料包括填充有导电颗粒的主材料。
20.根据权利要求13所述的电子元件,其中该半导体芯片包括具有在该第一主面处的第一电接触元件和在与该第一主面相对的第二主面处的第二电接触元件的电器件。
21.根据权利要求20所述的电子元件,其中该电器件包括垂直晶体管、MOS晶体管、IGB晶体管或功率晶体管。
22.根据权利要求20所述的电子元件,还包括设置在该第一电接触元件上的导电层,其中凹陷部形成在该导电层中。
23.根据权利要求13所述的电子元件,其中该半导体芯片还包括与该第一主面相对的第二主面,该电子元件还包括施加到该半导体芯片的第二主面的另一连接层,该另一连接层包括多个凹陷部。
24.一种电子元件,包括:
载体;
包括主面的半导体芯片;
施加到该半导体芯片的主面的连接层,该连接层包括多个隆起,其中该连接层设置于该半导体芯片和该载体之间;以及
设置在所述隆起之间的中间空间中的填充材料。
25.根据权利要求24所述的电子元件,其中所述隆起被形成为柱,所述柱具有垂直侧面。
26.根据权利要求24所述的电子元件,其中所述隆起彼此具有相同外形、相同尺寸和相同距离中的一个或多个。
27.根据权利要求24所述的电子元件,其中所述隆起以规则的方式布置。
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US10923454B2 (en) * | 2015-06-09 | 2021-02-16 | Seyed Amir Paknejad | Method and apparatus for creating a bond between objects based on formation of inter-diffusion layers |
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