CN1329977C - 生产多芯片模块的方法和多芯片模块 - Google Patents

生产多芯片模块的方法和多芯片模块 Download PDF

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CN1329977C
CN1329977C CNB2004100118387A CN200410011838A CN1329977C CN 1329977 C CN1329977 C CN 1329977C CN B2004100118387 A CNB2004100118387 A CN B2004100118387A CN 200410011838 A CN200410011838 A CN 200410011838A CN 1329977 C CN1329977 C CN 1329977C
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pattern
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CN1604309A (zh
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哈里·黑德勒
罗兰·伊尔希格勒
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Infineon Technologies AG
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Abstract

本发明提供一种生产多芯片模块的方法，有以下步骤：(a)在衬底上涂敷至少一个接点高地；(b)在衬底上涂敷和形成图案再接线图样并在至少一个接点高地上有接点图样构造的至少一个接点高地；(c)在有电接触连接的再接线图样的衬底上涂敷半导体芯片；(d)在半导体芯片，衬底，再接线图样和至少一个接点高地上涂敷不导电的密封图样，在至少一个接点高地上的接点图样至少触到密封图样的第一表面；(e)重复步骤(a)和(b)至少一次，密封图样的第一表面作为衬底，并且相应的产生再接线图样，与下面平面的至少一个接点高地的接点图样作电的接触。本发明同样提供多芯片模块。

Description

生产多芯片模块的方法和多芯片模块
技术领域
本发明涉及生产多芯片模块的方法和相应的多芯片模块，特别是在封装中生产多芯片电路系统的方法。
背景技术
为了能提供完全的半导体系统解决方案，必须能在一个组件中集成不同功能的单元。为了此集成，一方面选择SoC方法(系统在芯片上)，另一方面选择SiP方法(系统在封装中)是可能的。SiP解决方案的优点是，在封装中，作为芯片功能单元可以有效的各自最优化、测试和控制成本。相反，在SoC的情况中，所有的功能单元集成在单个芯片上。在SiP解决方案中存在的问题是在封装中，优选的在芯片堆叠中的各个芯片，互相之间必须导电的连接在一起。为了在芯片堆叠中提供各芯片之间的这些导电的连接，已知有许多使用的方法。图16说明两种已知的实例。
在根据图16上半部分的说明中，第一芯片A是通过插入物B与放置在其上面的第二芯片C机械的连接。芯片A、C通过在封装E中的联结线D电的接触连接。例如封装E通过焊料球F能连接到印刷电路板(未示出)。
在根据图16说明的下半部分已知的结构中，半导体芯片A通过焊料球F′电的连接到芯片C。芯片C同样地有再接线的联结线D，并接触连接在封装E中的焊料球F。封装E能通过焊料球F内部的电的接触连接。由于在高频时大的寄生效应，按照图16解释的已知结构有很差的电特性。基于联结线和许多连接点的高电感和电容，缺乏阻抗匹配。
另外通过再接线衬底或插入物，如以折叠封装形式的引线是已知的。然而，此安排引起长的信号路径，这同样在高频产生很差的电特性。更甚者，此已知的安排与衬底成本相关。
通过先前埋入聚合物的芯片边缘到直通电镀位置的薄膜引线同样是已知的。在直通电镀位置，在分离晶片之前在埋入的聚合物中产生导电的电镀直通孔。例如，由填入金属化的孔或开口提供此直通电镀位置。关联高成本的复杂处理在此情况中是不便的。
此外，已知在芯片中提供电镀直通孔，例如，用直通-Si-通路的方法。在通过芯片的接触连接的过程中，在此情况(干蚀刻，湿蚀刻)中通路蚀刻到芯片。因此随后整个通路的金属化钝化这些接触连接。由壁的金属化和随后通路填充导电材料通路金属化。这引起在芯片上必须提供直通电镀自由区的不便，直通电镀使得放大芯片面积成为必要。而且，在此情况中处理是复杂的，并具有高的成本。
发明内容
因此，本发明的目的是提供生产多芯片模块的方法，和依靠从芯片平面到芯片上面产生的导电连接的相应的多芯片模块。
本发明的概念主要根据存在于首先提供接点高地(contactelevation)，和在接点高地上的再接线图样，随后芯片电的连接到再接线图样，因此埋入密封层中是有效的。接点高地或三维连接元件更适宜的由非导电材料，如硅树脂，聚亚安酯，聚酰亚胺或导电材料，如导电粘合剂构成的印刷的高地做成，流体转变为底层衬底，如薄片。衬底更适宜的有金属的，图案的再接线层。
依靠本发明的生产方法和根据本发明的多芯片模块，在芯片堆叠中的芯片多样性可方便地以简单的和成本有效的方式互相连接。因此能避免使用大成本的再接线衬底或不利的联结引线。下面根据本发明的生产方法，作为例子，因为能使用12英寸的基片或方形基片或其它卷轴到卷轴的方法，在生产过程中做高度的平行是可能的。接点孔复杂的金属化和填充不是必须的，在沿芯片边缘分离芯片堆叠后只是形成尽可能少的垂直图案。
在本发明中，提供生产多芯片模块的方法特别解决在背景技术中提到的问题，方法有以下步骤：
在衬底上涂敷至少一个第一接点高地；
在衬底上涂敷和图案形成第一再接线图样和至少一个第一接点高地，其中，第一再接线图样包括第一接点高地上的第一接点图样；
在衬底上涂敷第一半导体芯片，第一半导体芯片与在衬底上涂敷的第一再接线图样电连接；
在第一半导体芯片和衬底上涂敷不导电的第一密封层，第一密封层将第一半导体芯片、衬底、第一再接线图样和至少一个第一接点高地密封起来，至少一个第一接点高地接触到第一密封层的第一表面；
至少重复第一涂敷步骤或涂敷和图案形成步骤之一，密封层的第一表面作为衬底，因此，已产生的再接线图样与下面平面的至少一个接点高地的接点图样作电的接触；
在第一密封层上涂敷至少一个第二接点高地；
在第一密封层上涂敷和图案形成第二再接线图样；
在第一密封层上涂敷第二半导体芯片，第二半导体芯片与涂敷在第一密封层上的第二再接线图样电接触；
在第二半导体芯片和第一密封层上涂敷不导电的第二密封层，第二密封层将第二半导体芯片、第一密封层、第二再接线图样和至少一个第二接点高地密封起来，从而至少一个第二接点高地与第二密封层的第一表面接触。
根据一个优选的实施例，在注入成型步骤或冲压步骤或测定步骤中印刷或涂敷至少一个接点高地。
根据优选的实施例，芯片接点图样涂敷在与半导体芯片电接触连接的再接线图样上。
根据优选的实施例，用焊接或与导电粘合剂的粘合联结或扩散焊接或压紧联结，芯片接点图样与再接线图样导电的电接触。
根据优选的实施例，用印刷或注入成型步骤或填充或喷射或旋转，涂敷非导电的密封层。
根据优选的实施例，在涂敷非导电的密封层后，清洗在至少一个接点高地上的接点图样，优选的在等离子体或湿蚀刻步骤中。
根据优选的实施例，除了半导体芯片，在与再接线图样电接触连接的密封层中，构造用至少一个无源的组件和/或存储器和/或光学的半导体图样做成。
根据优选的实施例，依靠溅射或电镀处理涂敷再接线图样，并随后光刻形成图案，更适宜的的用湿蚀刻步骤。
根据优选的实施例，在多芯片模块上，在最后的密封层上面，涂敷焊料球或接点高地或接点区域作为连接图样，在各情况中更适宜的以通过再接线图样与下面平面导电的连接的方式。
一种多芯片模块，包括：
(a)在衬底上至少有一个接点高地；
(b)在衬底和在至少一个接点高地上的再接线图样，再接线图样包括接点高地上的第一接点图样；
(c)半导体芯片涂敷在衬底上并电连接到再接线图样；
(d)不导电的密封层，将衬底、再接线图样和至少一个接点高地密封起来，至少一个接点高地的接点图样至少触到不导电密封层；
(e)重复特征(a)和(b)至少一次，不导电密封层的第一表面作为衬底，并且相应的再接线图样与下面平面的至少一个接点高地的接点图样作电的接触。
根据优选的实施例，提供薄片作为衬底。
根据优选的实施例，接点高地有非导电材料，更适宜的硅树脂，聚酰亚胺，聚亚安酯，或导电材料，更适宜的导电粘合剂。
根据优选的实施例，至少一个接点高地是球形的，更适宜的在衬底和接点高地之间有小梯度的过渡。
根据优选的实施例，在再接线图样上涂敷芯片接点图样，并与半导体芯片和再接线图样电的接触连接。
根据优选的实施例，密封层有聚合物。
根据优选的实施例，在多芯片模块中至少两个半导体器芯片与它们的芯片接点相互面对。
根据优选的实施例，再接线图样是金属的，并在预先确定的区域更适宜的有阻焊剂层或钝化层。
附图说明
在附图中说明本发明的实例，并在下面的描述中更详细的解释。
图1到11显示本发明的生产多芯片模块的连续步骤的概略的截面图；
图12到14显示本发明的各实例的多芯片模块的概略的截面图；
图15显示本发明的多芯片模块的概略的俯视图和概略的截面图；
图16显示两个已知的多芯片模块。
具体实施方式
在图中，同样的参考数字指同样的或功能同样的组件部分。
图1截面的说明衬底10，更适宜的为薄片。根据图2，至少一个接点高地11涂敷在其上面。接点高地11由聚合物作成，例如，可以是导电的如导电粘合剂，或非导电的，如硅树脂，聚亚安酯，聚酰亚胺。在印刷操作或测量操作或注入成型操作或冲压操作中更适宜的实现至少一个接点高地11的涂敷。至少一个接点高地11更适宜的是球形的，并从衬底10到接点高地11有小梯度的过渡。在此连接中，知道小梯度是小于0.5的梯度。
根据图3，更适宜的在衬底10和至少一个接点高地11上，涂敷和图案成形再接线图样12。在此情况中，再接线图样12在各种情况中在接点高地11上更适宜的有接点图样13。在接点高地11用导电材料构成的情况中，更适宜的避免在接点高地11上的接点图样13，那么再接线图样12与导电接点高地11做电的接触。再接线图样12更适宜的在光刻处理中溅射或电化学镀的图案成形，更适宜的依靠湿蚀刻技术，并在预先确定的部分有钝化层或阻焊剂层(未示出)。
根据图4，涂敷芯片接点图样14，它导电的连接到再接线图样12。根据图3到图11的截面图，在各情况中说明再接线图样12的两个互相电绝缘的导线束，即按照图4及其后的图在芯片接点图样14之间不提供再接线图样12形式的导电的连接。由涂敷焊料沉积或导电粘合剂沉积或凸缘冲击更适宜的提供芯片接点图样14。
在图5中，在按照图4的安排上，涂敷半导体芯片15，更适宜的粘合剂联结，芯片接点图样14导电的连接到半导体器件15的芯片接点(未示出)。这预示在衬底上半导体芯片15的精确定位。依靠焊料流回或压力接触或扩散焊接或使用导电粘合剂的粘合剂联结连接，更适宜的实现芯片接点(未示出)到芯片接点图样14的电接触连接。
根据图6，在芯片15，再接线图样12，至少一个接点高地11和衬底10上面涂敷非导电的聚合物形式的密封层16。由非导电材料的印刷或注入成型或溅射或旋转更适宜的涂敷密封层16。在此情况中，密封层16的垂直长度不超过至少一个接点高地11的垂直长度，因此在接点高地11上的接点图样13或接点高地11本身触到密封层16的至少一个表面16′(遮盖区域)。更适宜的，接点高地11的垂直长度凸出在密封层16的垂直长度上。在按照图6的安排的情况中，这更适宜的跟随在清洗接点高地11的尖端，特别是在接点高地11的尖端上的接点图样13之后，更适宜的在等离子体或湿蚀刻步骤中。
图7显示在密封层16的表面16′上已涂敷接点高地11后按照图6的安排。横向的安排在表面16′上的接点高地11邻近于下面平面的接点高地11的未覆盖的接点图样13。以参考图2解释的方式，在表面16′上涂敷接点高地11。这跟随在涂敷和图案成形在密封层16的表面16′上的再接线图样12和在有按照图8形成接点图样13的表面16′上的接点高地11后。涂敷和图案成形再接线图样12与参考图3解释的一像。与按照图8截面的说明相反，导体轨迹通向在表面16′上的接点高地11并在尖端上形成接点图样13，在表面16′上的再接线图样12的导体轨迹更适宜的不接触连接到在下面平面的接点高地11上的接点图样13，而与横向的邻近导体轨迹再接线(没有在截面图中示出)。
根据图9，在按照图8的安排上涂敷芯片接点图样14，这与下面平面的芯片接点图样14更适宜的是同样的。
图10说明根据图9的安排，在有接触连接的再接线图样12的表面16′上涂敷第二半导体芯片15，更适宜的通过芯片接点图样14。在表面16′上定位和固定的第二半导体芯片15相当于参考图5描述的操作。
按照图11，在各情况中，在表面16′上按照图6的密封层16同样地涂敷在第二半导体芯片15，再接线图样12，接点高地11上面。
图12说明多芯片模块的横截面，与图11比较，多芯片模块在另外的两个上表面上还有两个半导体芯片15。多重性的接点高地17涂敷在最后密封层16的最后表面16′上。例如，以包括如参考图2描述的导电或非导电材料的聚合物形式的高地，同样的更适宜的提供这些接触连接到印刷电路板或插入物(在任一情况中未示出)的连接元件。在最上面的密封层16的表面16′上同样的提供再接线图样18，此再接线图样在接点高地17的尖端上也更适宜的形成接点图样19。再接线图样18导电的连接到在下面平面的接点高地11上的接点图样13。
图13显示本发明的可选择实例，其中提供有互相相对的芯片接点(未示出)的两个半导体芯片15，在各种情况中半导体芯片15导电的连接到芯片接点图样14。与按照图13图例的印象相反，上面的半导体芯片15和下面的半导体芯片15的芯片接点图样不是直接的互相导电的连接。这要求修改的生产过程。
按照图14的实例有按照图13互相相对的芯片，和在上面安排的半导体芯片15。所有的基本特征相当于上面的解释。
参考图15概略的说明阐明本发明实例的截面图和相关的俯视图。在此情况中，截面图说明相当于沿虚线ZZ′的截面。
虽然上面基于优选的例子实例已经描述了本发明，但不限于此，而可以以不同的方式修改。因此，特别是，生产其它形式的接点高地是可能的，例如，凸起，垫片或关于横向和纵向的长度。而且，除了提到的可能性，由涂敷预先形成高地生产接点高地的方式也是可能的，特别是粘合剂联结。
此外，代替在其尖端上有接点图样19的接点高地17，提供电连接到电的或电子的组件的其它接点元件是可能的，例如，通过再接线图样18接触连接的接点区域或其它焊料球。关于芯片的堆叠高度和式样或芯片的安排，任何要求的结构是可能的，因此，由例子的方法，在根据本发明的多芯片模块的平面中，互相依次的提供不同芯片大小或其它芯片。此外，在图例中再现的相对大小只是当作例子的方法。

Claims (18)

1.一种生产多芯片模块的方法，包括步骤：
在衬底上涂敷至少一个第一接点高地；
在衬底上涂敷和图案形成第一再接线图样和至少一个第一接点高地，其中，第一再接线图样包括第一接点高地上的第一接点图样；
在衬底上涂敷第一半导体芯片，第一半导体芯片与在衬底上涂敷的第一再接线图样电连接；
在第一半导体芯片和衬底上涂敷不导电的第一密封层，第一密封层将第一半导体芯片、衬底、第一再接线图样和至少一个第一接点高地密封起来，至少一个第一接点高地接触到第一密封层的第一表面；
至少重复第一涂敷步骤或涂敷和图案形成步骤之一，密封层的第一表面作为衬底，因此，已产生的再接线图样与下面平面的至少一个接点高地的接点图样作电的接触；
在第一密封层上涂敷至少一个第二接点高地；
在第一密封层上涂敷和图案形成第二再接线图样；
在第一密封层上涂敷第二半导体芯片，第二半导体芯片与涂敷在第一密封层上的第二再接线图样电接触；
在第二半导体芯片和第一密封层上涂敷不导电的第二密封层，第二密封层将第二半导体芯片、第一密封层、第二再接线图样和至少一个第二接点高地密封起来，从而至少一个第二接点高地与第二密封层的第一表面接触。
2.根据权利要求1所述的方法，其特征在于在注入成型步骤或冲压步骤或测定步骤中印刷或涂敷至少一个接点高地。
3.根据权利要求1或2所述的方法，其特征在于在再接线图样上涂敷芯片接点图样，再接线图样电接触地连接到半导体芯片。
4.根据权利要求3所述的方法，其特征在于由焊料或与导电粘合剂粘合联结或扩散焊料或压力联结，芯片接点图样导电的连接到再接线图样。
5.根据权利要求1所述的方法，其特征在于由印刷或注入成型步骤或封装密封或溅射或旋转涂敷非导电的密封层。
6.根据权利要求1所述的方法，其特征在于在涂敷非导电的密封层后，以等离子体或湿蚀刻的方法清洗在至少一个接点高地上的接点图样。
7.根据权利要求1所述的方法，其特征在于除了半导体芯片，构造由有电接触连接到再接线图样的密封层中的至少一个无源组件和/或存储器和/或光学半导体器件组成。
8.根据权利要求1所述的方法，其特征在于使用湿蚀刻或溅射或电镀处理涂敷再接线图样，随后光刻成形图案。
9.根据权利要求1所述的方法，其特征在于在多芯片模块上，在最后的密封层上涂敷焊料球或接点高地或接点区域作为连接图样，在各情况中通过再接线图样导电的连接到下面的平面。
10.一种多芯片模块，包括：
(a)在衬底上至少有一个接点高地；
(b)在衬底和在至少一个接点高地上的再接线图样，再接线图样包括接点高地上的第一接点图样；
(c)半导体芯片涂敷在衬底上并电连接到再接线图样；
(d)不导电的密封层，将衬底、再接线图样和至少一个接点高地密封起来，至少一个接点高地的接点图样至少触到不导电密封层；
(e)重复特征(a)和(b)至少一次，不导电密封层的第一表面作为衬底，并且相应的再接线图样与下面平面的至少一个接点高地的接点图样作电的接触。
11.根据权利要求10所述多芯片模块，其特征在于提供薄片作为衬底。
12.根据权利要求10或11所述多芯片模块，其特征在于接点高地有非导电材料，包括硅树脂或聚酰亚胺或聚亚安酯，或导电材料，包括导电粘合剂。
13.根据权利要求12所述多芯片模块，其特征在于至少一个接点高地是球形的，并在衬底和接点高地之间有小梯度的过渡。
14.根据权利要求10所述多芯片模块，其特征在于在再接线图样上涂敷芯片接点图样，并且电的接触连接到半导体芯片和再接线图样。
15.根据权利要求14所述多芯片模块，其特征在于提供芯片接点图样为在再接线图样上的焊料沉积或凸缘冲击或导电粘合剂沉积。
16.根据权利要求10所述多芯片模块，其特征在于密封层有聚合物。
17.根据权利要求10所述多芯片模块，其特征在于在多芯片模块中至少两个半导体芯片有它们的芯片接点互相面对。
18.根据权利要求10所述多芯片模块，其特征在于再接线图样是金属的，在预先确定的区域有阻焊剂层或钝化层。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7919844B2 (en) 2005-05-26 2011-04-05 Aprolase Development Co., Llc Tier structure with tier frame having a feedthrough structure
US7768113B2 (en) * 2005-05-26 2010-08-03 Volkan Ozguz Stackable tier structure comprising prefabricated high density feedthrough
US20070069389A1 (en) * 2005-09-15 2007-03-29 Alexander Wollanke Stackable device, device stack and method for fabricating the same
US20070126085A1 (en) 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US20080054429A1 (en) * 2006-08-25 2008-03-06 Bolken Todd O Spacers for separating components of semiconductor device assemblies, semiconductor device assemblies and systems including spacers and methods of making spacers
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US8421244B2 (en) * 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
US8106496B2 (en) * 2007-06-04 2012-01-31 Stats Chippac, Inc. Semiconductor packaging system with stacking and method of manufacturing thereof
FR2917236B1 (fr) * 2007-06-07 2009-10-23 Commissariat Energie Atomique Procede de realisation de via dans un substrat reconstitue.
US8283756B2 (en) * 2007-08-20 2012-10-09 Infineon Technologies Ag Electronic component with buffer layer
US7868446B2 (en) * 2007-09-06 2011-01-11 Infineon Technologies Ag Semiconductor device and methods of manufacturing semiconductor devices
US10943869B2 (en) * 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6522022B2 (en) * 2000-12-18 2003-02-18 Shinko Electric Industries Co., Ltd. Mounting structure for semiconductor devices

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US5874782A (en) * 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
US5986334A (en) * 1996-10-04 1999-11-16 Anam Industrial Co., Ltd. Semiconductor package having light, thin, simple and compact structure
EP1447849A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board having the same mounted thereon
KR100266637B1 (ko) * 1997-11-15 2000-09-15 김영환 적층형볼그리드어레이반도체패키지및그의제조방법
JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
US6323060B1 (en) * 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
JP2001007472A (ja) * 1999-06-17 2001-01-12 Sony Corp 電子回路装置およびその製造方法
JP3670917B2 (ja) * 1999-12-16 2005-07-13 新光電気工業株式会社 半導体装置及びその製造方法
JP3865989B2 (ja) * 2000-01-13 2007-01-10 新光電気工業株式会社 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置
US6252305B1 (en) * 2000-02-29 2001-06-26 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US6956283B1 (en) * 2000-05-16 2005-10-18 Peterson Kenneth A Encapsulants for protecting MEMS devices during post-packaging release etch
JP3874062B2 (ja) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US20020140073A1 (en) * 2001-03-28 2002-10-03 Advanced Semiconductor Engineering, Inc. Multichip module
JP2002314031A (ja) * 2001-04-13 2002-10-25 Fujitsu Ltd マルチチップモジュール
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6624457B2 (en) * 2001-07-20 2003-09-23 Intel Corporation Stepped structure for a multi-rank, stacked polymer memory device and method of making same
DE10153609C2 (de) * 2001-11-02 2003-10-16 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips
DE10164800B4 (de) * 2001-11-02 2005-03-31 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips
DE10202881B4 (de) * 2002-01-25 2007-09-20 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterchips mit einer Chipkantenschutzschicht, insondere für Wafer Level Packaging Chips
DE10209922A1 (de) * 2002-03-07 2003-10-02 Infineon Technologies Ag Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
US6740546B2 (en) * 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6522022B2 (en) * 2000-12-18 2003-02-18 Shinko Electric Industries Co., Ltd. Mounting structure for semiconductor devices

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