JP2005109486A - マルチチップモジュールの製造方法及びマルチチップモジュール - Google Patents
マルチチップモジュールの製造方法及びマルチチップモジュール Download PDFInfo
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Abstract
【解決手段】 少なくとも1つのコンタクト隆起11を基板10上に設ける工程と、再配線素子12を基板10及びコンタクト隆起11の上に塗布し、パターニングしてコンタクト素子13を設ける工程と、半導体チップ15を再配線素子12から成る電気コンタクト接続を有する基板10上に設ける工程と、電気的導電性を示さない封止素子16を半導体チップ15、基板10、再配線素子12、及び少なくとも1つのコンタクト隆起11の上に、その一表面16’がコンタクト素子13に接触するように設ける工程とを備える。封止素子16の第1表面16’は基板として機能する。本発明による方法は、表面16’に対応して設けられる再配線素子12はその下の平面の少なくとも1つのコンタクト隆起11のコンタクト素子13と電気接続される。
【選択図】 図15
Description
電性材料で充填することによりメタライズされる。このプロセスは、チップにスルーホールメッキのために、チップ面積を大きくしてしまう空き領域を設ける必要があるという不利を生じさせる。また、この場合も処理が複雑となり、高コストを伴う。
、及びこの第1表面に対応して設けられることを要旨とする。
る請求項10記載のことを要旨とする。
請求項12に記載の発明は、前記コンタクト隆起11は非導電性材料、好適にはシリコーン又はポリイミド、又はポリウレタンを含む、又は導電性材料、好適には導電性接着剤を含むことを特徴とする、請求項10又は11記載のことを要旨とする。
請求項17に記載の発明は、請求項10〜16のいずれか一項に記載のマルチチップモジュールにおいて、前記マルチチップモジュールの少なくとも2つの半導体チップ15はそれらのチップコンタクトを通じて相対することを要旨とする。
された2本の再配線素子12が示される、すなわち再配線素子12の形での電気的導電性接続が図4に示すようにチップコンタクト素子14の間には設けられない。チップコンタクト素子14は半田又は導電性接着剤を塗布する、或いはスタッドバンプを配置することにより設けることが好ましい。
図10は図9の構成に続いて形成される構成を示し、図9の構成に対して、第2半導体チップ15を、再配線素子12のコンタクト接続を有する表面16’に、好適にはチップコンタクト素子14を介して取り付ける。表面16’上の第2半導体チップ15の配置及び固定方法は、図5を参照しながら記載した操作に対応する。
する。多くのコンタクト隆起17を最終の封止素子16の最終の表面16’の上に設ける。例えばプリント回路基板又はインターポーザ(どの場合にも示さず)とのコンタクト接続を行なうこれらの接続素子は、図2を参照しながら記載したように、導電性又は非導電性の材料を含むポリマー隆起の形で同じようにして設けることが好ましい。再配線素子18を同じようにして最上層の封止素子16の表面16’に設け、この再配線素子がコンタクト隆起17の先端上のコンタクト素子19も構成することが好ましい。再配線素子18は電気的導電性を示す形で下の平面のコンタクト隆起11上のコンタクト素子13に接続される。
本発明は好適な例示としての実施形態をベースにして上に記載してきたが、本発明はこれらの実施形態に限定されるのではなく、種々の態様で変形させることができる。従って特に、他の形状のコンタクト隆起を、例えばバンプ、ビーズとして設ける、又は横方向及び縦方向の寸法を変更して設けることが考えられる。さらに、記載した種々の考えられる構成に加えて、コンタクト隆起を形成する方法は、予備成形した隆起を設ける、特に接着接合することによっても実施することができる。
Claims (18)
- (a)少なくとも1つのコンタクト隆起を基板の上に設ける工程と、
(b)再配線素子を前記基板及び前記少なくとも1つのコンタクト隆起の上に塗布し、パターニングして、前記少なくとも1つのコンタクト隆起の上にコンタクト素子を設ける工程と、
(c)半導体チップを、前記再配線素子から成る電気コンタクト接続を有した前記基板の上に設ける工程と、
(d)前記半導体チップ、前記基板、前記再配線素子、及び前記少なくとも1つのコンタクト隆起の上に、電気的導電性を示さない封止素子を、前記少なくとも1つのコンタクト隆起上の前記コンタクト素子が少なくとも前記封止素子の第1表面に接触するように設ける工程と、
(e)少なくとも工程(a)及び(b)を少なくとも1回繰り返す工程とを備え、前記封止素子の前記第1表面は1つの基板として機能し、及びこの第1表面に対応して設けられる再配線素子はその下の平面の前記少なくとも1つのコンタクト隆起の前記コンタクト素子との電気コンタクトを行なう、マルチチップモジュールの製造方法。 - 前記少なくとも1つのコンタクト隆起は、印刷により形成する、又は射出成形工程又はスタンピング工程、或いは測光工程によって設けることを特徴とする請求項1記載の方法。
- 工程(b)と工程(c)との間で、チップコンタクト素子を、工程(c)で前記半導体チップに電気コンタクト接続される前記再配線素子の上に設けることを特徴とする請求項1又は2記載の方法。
- 前記チップコンタクト素子は電気的導電性を示す形で前記再配線素子に、半田付け、導電性接着剤使用の接着接合、噴流式半田付け、又は加圧接合により接続されることを特徴とする請求項3記載の方法。
- 前記非導電性の封止素子は、印刷法、又は射出成形工程、ポッティング法、スプレー塗布法、又はスピン塗布法により設けることを特徴とする請求項1〜4のいずれか一項に記載の方法。
- 工程(d)に従って前記非導電性の封止素子を設けた後、前記少なくとも1つのコンタクト隆起上の前記コンタクト素子を、好適にはプラズマ工程又はエッチング工程によりクリーニングすることを特徴とする請求項1〜5のいずれか一項に記載の方法。
- 半導体チップに加えて、受動素子、メモリ、及び光半導体装置のうちの少なくとも1つを少なくとも1つ前記封止素子内に設け、前記再配線素子との電気コンタクト接続を行なうことを特徴とする請求項1〜6のいずれか一項に記載の方法。
- 前記再配線素子をスパッタリングプロセス又はメッキプロセスにより成膜し、そして次にフォトリソグラフィにより、好適にはウェットエッチング工程を使用してパターニングすることを特徴とする請求項1〜7のいずれか一項に記載の方法。
- 前記マルチチップモジュール上に、かつ最終の封止素子の上方に、半田ボール群又はコンタクト隆起群又はコンタクト領域群を接続素子として設け、それぞれが下の平面に再配線素子を通して導電性を示す形で接続されることを特徴とする請求項1〜8のいずれか一項に記載の方法。
- (a)基板の上の少なくとも1つのコンタクト隆起と、
(b)前記基板及び前記少なくとも1つのコンタクト隆起の上にあるとともに、前記少なくとも1つのコンタクト隆起の上にコンタクト素子を有する再配線素子と、
(c)前記再配線素子から成る電気コンタクト接続を有する前記基板の上の半導体チップと、
(d)前記半導体チップ、前記基板、前記再配線素子、及び前記少なくとも1つのコンタクト隆起の上にあるとともに、電気的導電性を示さない封止素子と、前記少なくとも1つのコンタクト隆起の前記コンタクト素子は少なくとも前記封止素子の第1表面に接触することと、
(e)少なくとも構成要素(a)及び(b)を少なくとも1回繰り返して形成される構造とを備え、前記封止素子の前記第1表面は1つの基板として機能し、かつこの第1表面に対応して設けられる再配線素子はその下の平面の前記少なくとも1つのコンタクト隆起の前記コンタクト素子との電気コンタクトを行なう、マルチチップモジュール。 - 1つのシートを前記基板として設けることを特徴とする請求項10記載のマルチチップモジュール。
- 前記コンタクト隆起は非導電性材料、好適にはシリコーン又はポリイミド、又はポリウレタンを含む、又は導電性材料、好適には導電性接着剤を含むことを特徴とする、請求項10又は11記載のマルチチップモジュール。
- 前記少なくとも1つのコンタクト隆起はベル形状であり、そして好適には前記基板と前記コンタクト隆起との間の傾斜が小さい移行部分を有することを特徴とする、請求項12記載のマルチチップモジュール。
- チップコンタクト素子が前記再配線素子の上に設けられ、そして前記半導体チップ15及び前記再配線素子に電気コンタクト接続されることを特徴とする、請求項10〜13のいずれか一項に記載のマルチチップモジュール。
- 前記チップコンタクト素子が塗布半田又はスタッドバンプ、又は塗布導電性接着剤として前記再配線素子の上に設けられることを特徴とする、請求項14記載のマルチチップモジュール。
- 前記封止素子がポリマーを含むことを特徴とする、請求項10〜15のいずれか一項に記載のマルチチップモジュール。
- 前記マルチチップモジュールの少なくとも2つの半導体チップはそれらのチップコンタクトを通じて相対することを特徴とする、請求項10〜16のいずれか一項に記載のマルチチップモジュール。
- 前記再配線素子は金属であり、そして好適には、所定領域に半田レジスト層又は保護層を有することを特徴とする、請求項10〜17のいずれか一項に記載のマルチチップモジュール。
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US8395269B2 (en) | 2005-12-02 | 2013-03-12 | Renesas Electronics Corporation | Method of stacking semiconductor chips including forming an interconnect member and a through electrode |
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