CN106158759B - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN106158759B
CN106158759B CN201510180425.XA CN201510180425A CN106158759B CN 106158759 B CN106158759 B CN 106158759B CN 201510180425 A CN201510180425 A CN 201510180425A CN 106158759 B CN106158759 B CN 106158759B
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electronic component
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CN106158759A (zh
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庄龙山
蒋静雯
巫宗宴
卢俊宏
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法，该电子封装件包括：线路部、设于该线路部上的电子元件、以及设于该线路部上以遮盖该电子元件的盖体，且该盖体与该电子元件之间形成有间隔部。藉由该盖体的设计，能降低整体结构的翘曲程度。

Description

电子封装件及其制法
技术领域
本发明涉及一种电子封装件，尤指一种具晶圆级线路的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于晶片封装领域的技术，例如晶圆尺寸构装(Wafer Scale Package，简称CSP)、晶片直接贴附封装(Direct Chip Attached，简称DCA)或多晶片模组封装(Multi－Chip Module，简称MCM)等覆晶型态的封装模组。
图1A至图1F为现有半导体封装件1的制法的剖面示意图。
如图1A所示，提供一半导体结构，该半导体结构包含一硅板体10、形成于该硅板体10上的一线路部11、覆晶结合于该线路部11上的多个半导体晶片12、及形成于该线路部11与各该半导体晶片12之间的底胶13。
如图1B所示，形成一封装胶体14于该线路部11上以包覆各该半导体晶片12与该底胶13。
如图1C所示，移除该封装胶体14的顶部材质以外露出该半导体晶片12。
如图1D所示，形成一支撑件15于该封装胶体14与该半导体晶片12上，其中，该支撑件15具有粘着层150、硅板151与绝缘层152，且该绝缘层152是以化学气相沉积(ChemicalVapor Deposition，简称CVD)方式形成介电材所构成者。
如图1E所示，移除该硅板体10，以外露该线路部11。接着，形成一绝缘保护层17于该线路部11上，且该绝缘保护层17外露部分该线路部11，以结合多个焊球18于该线路部11上。
如图1F所示，沿如图1E所示的切割路径S进行切单制程，以获得多个半导体封装件1，藉由该硅板151增加该半导体封装件1的刚性，且可提高该半导体晶片12的散热效果。
惟，现有半导体封装件1的制法中，需进行模封(molding)制程以制作该封装胶体14，且需进行研磨(lapping)制程以移除该封装胶体14的顶部材质，造成步骤繁琐、工序复杂，故整体制程不仅耗时耗工，且需购买多种设备，导致产品成本无法下降。
此外，该半导体晶片12与封装胶体14间的热膨胀系数(Coefficient of thermalexpansion，简称CTE)差异甚大，使该尚未进行切单的整体结构容易产生翘曲(warpage)。
又，该封装胶体14容易吸收水气，也会使该尚未进行切单的整体结构容易发生翘曲。
另外，若发生翘曲现象，则可能使该半导体晶片12发生破裂、或于后续如植球制程(即形成该焊球18)时，使焊球接置的可靠度下降而造成掉球等问题，致使产品的品质不佳。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其制法，能降低整体结构的翘曲程度。
本发明的电子封装件，其包括：线路部，其具有相对的第一侧与第二侧；至少一电子元件，其设于该线路部的第一侧上；以及盖体，其设于该线路部的第一侧上以遮盖该电子元件，且该盖体与该电子元件之间具有间隔部。
本发明还提供一种电子封装件的制法，其包括：提供一半导体结构，该半导体结构包含承载件、设于该承载件上的线路部、及结合于该线路部上的至少一电子元件；形成盖体于该线路部的第一侧上以遮盖该电子元件，且该盖体与该电子元件之间具有间隔部；以及移除该承载件。
前述的制法中，还包括于移除该承载件后，进行切单制程。
前述的电子封装件及其制法中，该半导体结构还包含形成于该线路部与该电子元件之间的底胶。
前述的电子封装件及其制法中，该盖体具有至少一开口，使至少一该电子元件容置于单一该开口中。
前述的电子封装件及其制法中，该盖体接触该电子元件。
前述的电子封装件及其制法中，形成该盖体的材质为半导体材质。
前述的电子封装件及制法中，该盖体具有板部与立设于该板部上的支撑部，且该支撑部架设于该线路部的第一侧上，使该板部遮盖该电子元件。
另外，前述的电子封装件及制法中，还包括于移除该承载件后，形成多个导电元件于该线路部上。
由上可知，本发明的电子封装件及其制法，主要藉由藉由该盖体取代现有封装胶体，以简易制程工序与节省设备费用，而降低制作成本，且藉由该盖体的设计，能降低整体结构的翘曲程度，以避免发生翘曲现象。
附图说明
图1A至图1F为现有电子封装件的制法的剖面示意图；
图2A至图2D为本发明的电子封装件的制法的剖面示意图；其中，图2B’及图2B”为图2B的不同实施例，且图2D’及图2D”为图2D的不同实施例；以及
图2E为图2D的后续制程。
符号说明
1 半导体封装件
10 硅板体
11,21 线路部
12 半导体晶片
13,23,290 底胶
14 封装胶体
15 支撑件
150 粘着层
151 硅板
152 绝缘层
17,27 绝缘保护层
18 焊球
2,2’,2” 电子封装件
2a 半导体结构
20 承载件
21a 第一侧
21b 第二侧
210 介电层
211 线路层
212 电性接触垫
22 电子元件
22a 作用面
22b 非作用面
22c 侧面
221 导电凸块
25,25’,25” 盖体
250 板部
251 支撑部
26,26’ 开口
270 开孔
28 导电元件
29 电子装置
A 间隔部
S 切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2D为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一半导体结构2a，该半导体结构2a包含一承载件20、形成于该承载件20上的一线路部21、结合于该线路部21上的多个电子元件22、及形成于该线路部21与各该电子元件22之间的底胶23。
于本实施例中，该承载件20为半导体板材，如硅板。
此外，该电子元件22为主动元件、被动元件或其组合者，该主动元件例如为半导体晶片，而该被动元件为例如电阻、电容及电感。于此该电子元件22为主动元件，且其具有相对的作用面22a与非作用面22b。
又，该线路部21包含相迭的多个介电层210与多个线路层211，并具有相对的第一侧21a与第二侧21b，使该些电子元件22的作用面22a藉由多个导电凸块221覆晶结合于该线路部21的第一侧21a的线路层211上，而该底胶23包覆该些导电凸块221，且该线路部21的第二侧21b具有多个电性接触垫212并结合至该承载件20上。
另外，该线路层211为晶圆级线路，而非封装基板级线路。目前封装基板级线路的最小的线宽与线距为12μm，而半导体制程能制作出3μm以下的线宽与线距的晶圆级线路。
如图2B所示，形成一盖体25于该线路部21的第一侧21a上以遮盖各该电子元件22与该底胶23，且该盖体25具有至少一开口26，使多个该电子元件22容置于单一该开口26中。
于本实施例中，该盖体25与该电子元件22之间形成有间隔部A。例如，该间隔部A形成于该盖体25与该电子元件22的非作用面22b及侧面22c之间。于其它实施例中，该盖体25’的板部250可接触该电子元件22的非作用面22b，如图2B’所示，使该间隔部A形成于该电子元件22的侧面22c外，而未形成于该非作用面22b外。
此外，形成该盖体25的材质可为半导体材质，例如硅晶圆，且该盖体25具有一板部250与立设于该板部250周围的一支撑部251，且该支撑部251架设于该线路部21的第一侧21a上，使该板部250遮盖各该电子元件22与该底胶23，也就是该电子元件22的非作用面22b不会外露出该板部250。具体地，制作该盖体25的方式可蚀刻一硅晶圆，以形成该开口26与该支撑部251，其中，该支撑部251为该开口的侧壁。
另外，该盖体25”的单一该开口26’中亦可仅容置一电子元件22，如图2B”所示。
如图2C所示，移除该承载件20，以外露该线路部21的第二侧21b及该电性接触垫212。接着，形成多个如焊球的导电元件28于该线路部21的第二侧21b上。
于本实施例中，先形成一绝缘保护层27于该线路部21的第二侧21b，且该绝缘保护层27形成有多个开孔270，令该些电性接触垫212外露于各该开孔270，以供结合该些导电元件28。
如图2D所示，沿如图2C所示的切割路径S(即该该盖体25的支撑部251)进行切单制程，以获得多个电子封装件2。
此外，于其它实施例中，也可先进行切单制程，再形成该绝缘保护层27与该些导电元件28。
又，若接续图2B’及图2B”所示的制程，将得到如图2D’及图2D”所示的电子封装件2’,2”。
另外，于后续制程中，该电子封装件2可藉由该些导电元件28结合至一如电路板的电子装置29上，并以底胶290固定与保护该些导电元件28，如图2E所示。
本发明的制法中，藉由该盖体25,25’,25”的设计，使本发明无需形成封装胶体，故能省略现有技术的模封制程与研磨制程，因而使步骤简化、工序简易，因此，本发明的整体制程不仅省时省工，且能节省购买设备的费用，以大幅降低产品的成本。
此外，该盖体25,25’,25”与该电子元件22间的热膨胀系数(Coefficient ofthermal expansion，简称CTE)差异甚小，故能避免该尚未进行切单的整体结构产生翘曲(warpage)现象，因而能提升产品良率。
此外，该盖体25,25’,25”不会吸收水气，故当移除该承载件20后，能避免整体结构(如图2C的结构)发生翘曲。
又，藉由该该盖体25,25’,25”的刚性，以当移除该承载件20后，能降低整体结构的翘曲程度，藉以克服因该线路部21、电子元件22、底胶23间的热膨胀系数(CTE)差异过大所产生的翘曲现象。
因此，利用本发明的制法能避免发生翘曲现象，因而能避免该电子元件22发生破裂、或该导电元件28的可靠度下降而造成掉球等问题，故本发明的制法能提升产品的品质。
本发明提供一种电子封装件2,2’,2”，包括：具有相对的第一侧21a与第二侧21b的一线路部21、设于该线路部21的第一侧21a的至少一电子元件22、以及设于该线路部21的第一侧21a上以遮盖该电子元件22的盖体25,25’,25”。
所述的盖体25,25’,25”具有至少一开口26,26’，使至少一电子元件22容置于单一该开口26,26’中，且该盖体25,25’,25”与该电子元件22之间形成有间隔部A，又形成该盖体25,25’,25”的材质为半导体材质。
于一实施例中，该盖体25’接触该电子元件22。
于一实施例中，该盖体25,25’,25”具有一板部250与立设于该板部250上的一支撑部251，且该支撑部251架设于该线路部21的第一侧21a上，使该板部250遮盖各该电子元件22。
于一实施例中，所述的电子封装件2,2’,2”还包括底胶23，其形成于该线路部21的第一侧21a与该电子元件22之间。
于一实施例中，所述的电子封装件2,2’,2”还包括多个导电元件28，其设于该线路部21的第二侧21b。
综上所述，本发明的电子封装件及其制法，藉由该盖体取代现有封装胶体，以简易制程工序与节省设备费用，而降低制作成本，且藉由该盖体的设计，能降低整体结构的翘曲程度，以避免发生翘曲现象。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (4)

1.一种电子封装件的制法，其特征为，该制法包括：
提供一半导体结构，该半导体结构包含承载件、设于该承载件上的线路部、及结合于该线路部上的至少一电子元件；
形成盖体于该线路部的第一侧上以遮盖该电子元件，其中，形成该盖体的材质为半导体材质，该盖体与该电子元件之间具有间隔部，在该盖体内部未形成封装胶体，该盖体具有板部与立设于该板部上的支撑部，且该支撑部架设于该线路部的第一侧上，使该板部遮盖及接触该电子元件；
移除该承载件；以及
于移除该承载件后，沿该盖体的支撑部进行切单制程，使该支撑部的侧面与该线路部的侧面齐平。
2.根据权利要求1所述的电子封装件的制法，其特征为，该半导体结构还包含形成于该线路部与该电子元件之间的底胶。
3.根据权利要求1所述的电子封装件的制法，其特征为，该盖体具有至少一开口，使至少一该电子元件容置于单一该开口中。
4.根据权利要求1所述的电子封装件的制法，其特征为，该制法还包括于移除该承载件后，形成多个导电元件于该线路部上。
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