TWI484611B - 箔片基底半導體封裝 - Google Patents

箔片基底半導體封裝 Download PDF

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Publication number
TWI484611B
TWI484611B TW098117947A TW98117947A TWI484611B TW I484611 B TWI484611 B TW I484611B TW 098117947 A TW098117947 A TW 098117947A TW 98117947 A TW98117947 A TW 98117947A TW I484611 B TWI484611 B TW I484611B
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TW
Taiwan
Prior art keywords
foil
carrier
metal foil
metal
construction
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TW098117947A
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English (en)
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TW201001658A (en
Inventor
Will Wong
Nghia Thuc Tu
Jaime Bayan
David Chin
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Nat Semiconductor Corp
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Publication of TW201001658A publication Critical patent/TW201001658A/zh
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Publication of TWI484611B publication Critical patent/TWI484611B/zh

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Description

箔片基底半導體封裝
本發明係一般關於積體電路(IC)的封裝。更具體的說，本發明關於涵蓋薄箔片的封裝方法與配置。
有許多用於封裝積體電路(IC)晶粒的傳統處理。舉例來說，很多IC封裝利用由金屬薄片蝕刻或壓印的金屬引線架以提供連結至外部裝置的電氣互連。該晶粒可以藉由連結線、焊接凸塊或其他合適的電氣連接物以電氣連結至引線架。一般而言，該晶粒與引線架的一些部分以模製材料密封以保護在晶粒主動側上脆弱的電氣元件，而讓引線架的一些選定部分曝露以有助於電氣連接至外部裝置。
很多傳統引線架具有大約4到8密耳(mil，千分之一英寸)的厚度。進一步減少引線架厚度提供了幾個好處，包括可能減少總封裝尺寸與節省引線架金屬。但是一般而言，在封裝期間，較薄的引線架具有較容易彎曲的傾向。可以使用像是支持膠帶的支撐構造在引線架上以減少彎曲的風險。但是這一類的構造會負擔比較高的成本。
封裝設計採用金屬箔片作為電性互連來取代引線架的概念已經被提出很多次。雖然一些箔片基底設計已經發展起來，但是沒有一個在工業界達到被廣泛接受的程度，一部分是因為箔片基底封裝處理傾向於比傳統引線架封裝來得更昂貴，而一部分是因為很多現有的封裝設備並不適用 於用在這一類的箔片基底封裝設計。
雖然用於製造引線架與使用引線架科技封裝積體電路的現有技術運作良好，仍然有人持續努力發展用於封裝積體電路更有效的設計與方法。
所主張的發明係關於用於使用薄箔片以在積體電路封裝中形成電氣互連的方法與配置。在一實施例中，藉由將導電箔片的一些部分超音波式連結至金屬載體以形成箔片載體構造。該連結部分定義了在箔片載體構造中的嵌板。在一些實施例中，該箔片載體構造被切割以形成沿著其周圍密封的多個隔離嵌板。每一隔離嵌板可以大約是傳統引線架條或嵌板的尺寸。結果現有的封裝設備可以用來增加晶粒、連結線與模製材料到嵌板上。該超音波焊接幫助防止了不欲物質在這一類處理步驟中穿透箔片載體構造。在移除該模製箔片載體構造的載體部分之後，該構造被單塊化成積體電路封裝。一些實施例與利用一些或全部之上述操作的方法有關。其他實施例與新的封裝配置有關。
在本發明的一些方面，說明了用於形成上述箔片載體構造的方法。該方法涵蓋了將金屬箔片的一些部分超音波式連結至載體。該金屬箔片與該載體個別的厚度可以根據特別應用的需求而變動。舉例來說，範圍從大約0.5密耳到2密耳的箔片厚度與範圍從大約5密耳到10密耳的載體厚度運作良好。該超音波式連結部分可以形成平行的焊接 線，該焊接線定義了箔片載體構造中的嵌板。在一些實施例中，該超音波式連結部分形成環繞每一嵌板的連續周邊。
可以加入額外金屬至箔片以減少電致遷移(electromigration)並且促進之後的焊線。在一些實施例中，該方法包括以金屬(像是銀合金)點鍍金屬薄片的頂端表面以形成多個裝置區域。可以不使用點鍍，而是施加銀的連續層至箔片的表面。在其他實施例中，施加鎳、鈀、及/或金到箔片的一側或兩側。也可以使用其他箔片金屬化層。
在本發明的另一方面，說明了用於封裝積體電路裝置的方法。該方法涵蓋黏附多個晶粒到箔片載體構造。該箔片載體構造可以採用上述說明的箔片載體構造形式，不過這並不是必要的。舉例來說，一些箔片載體構造的實施例使用黏著劑而不是超音波連結以將箔片黏附至載體。該方法進一步涵蓋了以模製材料密封一部分的金屬箔片與晶粒，並且移除載體。在載體從模製箔片載體構造移除之後，該箔片被蝕刻並曝露出一部分的模製材料。該蝕刻定義了箔片中的裝置區域。每一裝置區域組構以電氣連接至積體電路晶粒。在蝕刻步驟之後，該構造被單塊化以形成積體電路封裝。
其他的特點也是可能存在的。該密封可以涵蓋施加條狀連續體的模製材料。在一些方面，該金屬箔片包括基底金屬(例如銅)層與銀塗層。在其他方面，該金屬箔片包括基底金屬層與鈀與鎳的一或多個層。這一類的層可以在 相同的操作中被蝕刻以隔離在每一裝置區域中上的鉛觸點與連結點。在一些實施例中，該蝕刻處理發生在模製箔片被放置在可重覆使用的蝕刻載體腔室之後。
本發明的另一個方面涵蓋適於用在封裝積體電路晶粒的配置。該配置包括金屬箔片，該金屬箔片的一些部分與金屬載體超音波式連結。該箔片載體構造可以具有上面說明的一或多個特點。
本發明一般係關於積體電路的封裝。更特別的是，本發明關於用於使用薄箔片以在積體電路封裝中形成電氣互連的改良式低成本方法與配置。
薄箔片給半導體製造者帶來很多挑戰。如同稍早之前提到的，薄箔片在封裝處理的應力之下，很容易傾向於彎曲。此外，現有的封裝設備(組構以用於操控引線架)典型地不適用於處理薄箔片，因為薄箔片與傳統引線架在尺寸上不同，而且比傳統引線架脆弱。以下會說明用來處理這些挑戰之本發明的各種實施例。
第一個說明的實施例涵蓋了箔片載體構造100，該箔片載體構造100設計以更有效率地將薄箔片整合進入半導體封裝製程。箔片載體構造100由銅箔片114製成，將銅箔片114沿著焊接線112超音波式連結至鋁載體。該箔片與該載體也可以由其他合適材料製成。焊接線112與預定切踞路徑110將該構造分離成多嵌板104。
箔片載體構造100設計以沿著預定切踞路徑110切割。這一類的切割將會產生多個隔離嵌板。因為焊接線112與每一個預定切踞路徑110平行，並且位在每一個預定切踞路徑110的兩側上，在切割操作之後，焊接線112將圍繞著每一隔離嵌板形成連續的密封周邊。在這個實施例中，每一嵌板的尺寸與特點調適以讓現有的封裝設備處理。因此這一類的設備可以用來蝕刻、單塊化、增加晶粒、接線與模製材料到每一嵌板上。(這些處理步驟的例子將在以下連結圖3A到圖3E、圖4A到圖4C與圖5A到圖5E做討論。)因為每一嵌板使用超音波式連結做密封，避免了在上述處理步驟期間來自該嵌板層與層之間的不欲物質。
超音波式連結提供強壯到足以忍受由封裝處理後面的階段施加的應力的優點，並且在加入晶粒、接線與模製材料到該箔片之後，仍然允許載體輕易從該箔片分離。在本發明書使用的用語「超音波式連結」包括具有超音波式元件的任何合適連結技術，也包括熱音波連結。雖然超音波式連結運作良好，但應該了解的是其他合適的連結技術也可以用來將箔片固定至載體上。舉例來說，也可以使用各種合適的黏著劑。
在圖解的實施例中，該焊接線被限制在每一嵌板周邊的連結區域上，而且沒有延伸到該嵌板的中心或內部。但是應該了解的是該焊接線112可以用各種其他方式配置。舉例來說，嵌板104可以由單一且更寬的焊接線來加以分離而不是以一對較薄的焊接線分離。假如切踞路徑是沿著 每一較寬焊接線的中間行進，所得的嵌板也將會沿著嵌板周邊被密封。或者，也可以提供額外的中間焊接線以有效地將嵌板分離成較小的密封區段。舉例來說，每一密封區段可以包括二維陣列的裝置區域或是很像各種傳統引線架條中出現的裝置區域的配置。
應該了解的是在箔片載體構造100中的箔片可以包括各種金屬層。熟悉封裝技術者會了解到有時會施加像是鎳、鈀、或銀在銅引線架上以處理下列各種問題：減少電致遷移及/或改良在連結線與引線架之間的電氣連結等等。在本發明中，該箔片取代引線架，並希望施加類似的塗層到該箔片上。為了減少成本，在箔片接附到載體構造之前，有時候可以施加這一類的金屬化層到該箔片上。舉例來說，假如箔片載體構造100中的箔片由銅製成，可能會希望以鎳層與鈀層對箔片的兩側做塗層。在其他實施例中，該箔片頂端(被曝露的)表面由一層銀或銀合金覆蓋。或者，該箔片也可以是銀點鍍而成的，如同圖1B中圖解所示。
圖1B展示了根據本發明實施例之嵌板104的放大頂端視圖。嵌板104包括多個裝置區域106，該等裝置區域106由銀合金的點鍍形成，也可以使用其他合適的金屬。圖1C圖解裝置區域106其中之一的放大頂端視圖。點鍍部分108形成適用於焊線至積體電路晶粒的連結點圖案。這一類的點鍍可以在沿著預定切踞路徑110切割箔片載體構造100之前或之後發生。當連結線稍後連結到箔片的點鍍部分108時， 銀合金可以強化該連結。
裝置區域106可以採用各種圖案與組構。在圖解的實施例中，點鍍部分108定義了位在裝置區域106周邊附近的環中的複數個連結點。當然也可以使用各種其他的連結點圖案。舉例來說，假如希望下連結(down bonding)至類似晶粒接附墊的放大接地(或其他)觸點，可以接著在裝置區域106的中心提供合適的點鍍。在其他實施例中，可以點鍍多列連結點或各種其他連結點圖案的任何一種在箔片上。
圖2與圖3A到圖3E圖解根據本發明一實施例用於封裝積體電路裝置的製程200。一開始，在步驟202時，提供了在圖3A中包括箔片306與載體308的箔片載體構造300。箔片載體構造300可以採用從圖1A之箔片載體構造100切割下來的嵌板104之形式，不過這不是必要的。在圖解的實施例中，箔片306是銅箔片而該載體308由鋁製成。在替代性實施例中，可以用不同的金屬箔片取代銅箔片，及可以用不同的載體構造來取代鋁載體308。舉例來說，該載體或者可以由銅、鋼或其他金屬、像是聚亞醯胺的非導電材料或各種其他合適材料製成。在一些實施例中，箔片306經由超音波式連結黏著到載體308上，而在其他實施例中，使用黏著劑或其他合適的連結機制來將箔片306固定到載體308。
可以廣泛地變動箔片載體構造300的尺寸以符合特定應用的需要。在一些實施例中，箔片載體構造300大約是典型引線架條的尺寸。也可以廣泛地變動箔片306與載體 308的厚度。在一些實施例中，箔片厚度的範圍大約在0.5密耳到2密耳。載體厚度的範圍可以大約在5密耳到12密耳。當使用鋁載體時，厚度範圍在7密耳到10密耳的鋁載體運作良好。一般而言，箔片載體構造的厚度與標準引線架的厚度匹配是有利的，如此一來可以使用調適以操控引線架的標準封裝設備來處理該構造。
一開始，在步驟204時，使用傳統晶粒接附技術將晶粒318架置在箔片載體構造300上。在接附完晶粒之後，將晶粒用像是焊線的合適手段電氣連接到箔片上。該焊線的構造在圖3B中圖解。應該了解的是所說明方法的顯著優點之一是可以在晶粒接附與焊線的步驟中使用通常可得的晶粒接附與焊線設備。所得的構造具有藉由連結線316電氣連接到箔片的複數個晶粒。在圖解的實施例中，提供額外的鎳層與鈀層在箔片306的兩個表面上。上面的鈀層有助於將連結線316更牢固地固定在箔片上。
在步驟206與圖3C中，將載體308、連結線316與至少一部分箔片載體嵌板301與銅層306用模製材料322密封以形成模製箔片載體構造324。在圖3C的圖解實施例中，加入條狀連續體形式的模製材料322。也就是說，將該模製材料很平均地施加在整個箔片306的模製部分上。應該注意到的是這種型式的模製在引線架基底封裝中不是通用的。相對地來說，引線架條上承載的裝置典型地被個別模製或是以小嵌板模製。條狀連續體模製材料的好處將會連結圖3D、3E與步驟208加以討論。
在步驟208中，移除圖3C中模製箔片載體構造324的載體部分，形成了圖3D中的模製箔片構造325。此時模製材料取代了載體308，提供了箔片的構造支撐。應該了解的是條狀連續體模製方法的優點是它提供了全部嵌板的良好支撐，因此該條狀物仍然可以用嵌板形式操控。反面來說，假如在模製操作期間在小嵌板之間提供模製溝槽，在移除載體之後，接著將需要獨立操控小嵌板。
圖3E展示了模製箔片構造325的外部視圖，應該了解的是，雖然模製箔片構造325的頂端表面328大致上是平面的，但這不是一個必要需求。在模製箔片構造325中的模製材料322可以採用各種圖案與形狀，而且模製材料的深度334可以沿著模製箔片構造325的長度變動。
在步驟209中，如圖4A與圖4B中所示，將模製箔片構造325放置在蝕刻載體404中。圖4A圖解含有模製箔片構造325之蝕刻載體404的頂端視圖。在該圖解的實施例中，蝕刻載體404包括組構以接收模製箔片構造325的對準孔402與腔室406。蝕刻載體404設計以接收圖3F的模製箔片構造325，如此一來該模製箔片構造的頂端表面328被隱藏在腔室406內，而箔片306被曝露。該蝕刻載體可以被重覆使用，而且較佳地以鋁製成，不過也可以使用其他材料。
在步驟210中蝕刻箔片306。該蝕刻移除箔片306的一些部分並且定義了多個裝置區域410，如圖4B所示。也可以使用包括電漿蝕刻的各種合適蝕刻製程。也可以使用其 他合適技術形成裝置區域410，該等技術像是切鋸或雷射切割。
一些實施例涵蓋了以匯流排形成裝置區域410以促進之後金屬(像是錫或焊錫)在由箔片形成之觸點上的電鍍。圖4C概略性地圖解這樣一個裝置區域。在圖解的實施例中，裝置區域410具有晶粒接附墊412、鉛觸點414與匯流排416。匯流排416電氣連接該墊與鉛。匯流排416也可以形成在多個裝置區域之間的導電連結。應該了解的是，裝置區域410只代表很多可能配置的其中之一。
圖5A到圖5B提供模製箔片構造325上之蝕刻製程效果的側視圖。圖5A是在蝕刻之前模製箔片構造325的概略側視圖。圖5B圖解了蝕刻製程是如何移除箔片306的一些部分，露出模製材料322的一些區段並且形成鉛觸點414與晶粒接附墊412。
如同上面討論的，一些實施例考慮到圖2的步驟211，該步驟涵蓋了圖5C的焊錫508在晶粒接附墊412與鉛觸點414上的電鍍。在步驟212，該模製箔片構造325沿著圖5C的預定切踞路徑302單塊化以形成半導體封裝。可以使用包括切鋸與雷射切割的各種技術來單塊化模製箔片構造325。在圖5D中圖解單塊化封裝520的放大側視圖。在圖5E中顯示該封裝的概略底端視圖。該底端視圖圖解由模製材料322圍繞的晶粒接附墊516與鉛觸點518。
雖然只有詳細說明本發明的一些實施例，應該了解的是本發明可以用很多其他形式施行而不偏離本發明的精神 或範疇。在先前的說明當中，很多說明的引線架包括鉛及/或觸點，在這裡通常指稱為鉛觸點。在本發明的內容當中，該用語「鉛觸點」意圖包含可能出現在引線架內的鉛、觸點與其他電氣互連構造。因此本發明的實施例應該被視為解釋性的，並不是限制性的，而且本發明並不限於這裡所給定的細節，並且可以在本發明的範疇內修改，而且可以是隨附申請專利範圍的等效物。
100‧‧‧箔片載體構造
104‧‧‧嵌板
106‧‧‧多個裝置區域
108‧‧‧點鍍部分
110‧‧‧預定切踞路徑
112‧‧‧焊接線
114‧‧‧銅箔片
200‧‧‧用於封裝積體電路裝置的製程
202-212‧‧‧用於封裝積體電路裝置的處理中之每一步驟
300‧‧‧箔片載體構造
301‧‧‧箔片載體嵌板
302‧‧‧預定切鋸路徑
306‧‧‧箔片
308‧‧‧載體
316‧‧‧連結線
318‧‧‧晶粒
322‧‧‧模製材料
324‧‧‧模製箔片載體構造
325‧‧‧模製箔片構造
328‧‧‧模製箔片構造的頂端表面
334‧‧‧模製材料的深度
402‧‧‧對準孔
404‧‧‧蝕刻載體
406‧‧‧腔室
410‧‧‧多個裝置區域
412‧‧‧晶粒接附墊
414‧‧‧鉛觸點
416‧‧‧匯流排
508‧‧‧焊錫
516‧‧‧晶粒接附墊
518‧‧‧鉛觸點
520‧‧‧單塊化封裝
本發明與其中的優點藉由參照與隨附圖式連結的上述說明可以最容易被理解，其中：圖1A為根據本發明一實施例之包括兩個超音波式連結層與多個嵌板之箔片載體構造的概略頂端視圖。
圖1B為根據本發明一實施例在圖1A中說明之嵌板其中之一的放大概略頂端視圖。
圖1C為在圖1B中說明之嵌板上裝置區域其中之一的放大概略頂端視圖。
圖2為根據本發明一實施例說明封裝積體電路裝置之處理的流程圖。
圖3A到圖3E為根據本發明之實施例封裝處理之各種階段的概略側視圖。
圖4A為在圖3E說明之模製箔片構造放置在載體後之例示性蝕刻載體的概略頂端視圖。
圖4B為在蝕刻之後在圖4A中說明之蝕刻載體與模製 箔片構造的概略頂端視圖。
圖4C為根據本發明一實施例由圖4B之蝕刻處理所得之裝置區域的放大概略頂端視圖。
圖5A到圖5C為在蝕刻、電鍍與單塊化之後在圖3D中說明之模製箔片構造的概略側視圖。
圖5D為根據本發明之實施例單塊化封裝的概略側視圖。
圖5E為在圖5D中說明之單塊化封裝的概略底端視圖。
在圖式當中，類似的元件符號有時候會用來代表類似的構造元件。讀者也應該了解圖式中的描繪是概略性的，並且沒有按比例縮放。
200‧‧‧用於封裝積體電路裝置的製程
202-212‧‧‧用於封裝積體電路裝置的處理中之每一步驟

Claims (18)

  1. 一種用於形成箔片載體構造的方法，包含：提供金屬載體；提供金屬箔片；將金屬箔片的一些部分超音波式連結至金屬載體，該連結部分定義在金屬箔片中的多個嵌板，該等嵌板適用於用來作為在積體電路封裝中的箔片載體嵌板；及以銀或銀合金點鍍金屬箔片的表面以形成在每一嵌板內的多個裝置區域，每一裝置區域適用於焊線至積體電路晶粒。
  2. 如申請專利範圍第1項所述之方法，其中該金屬箔片是銅箔片，該銅箔片具有形成在金屬箔片之頂端表面與底端表面的鎳層與鈀層。
  3. 如申請專利範圍第1項所述之方法，其中該金屬箔片的厚度介於大約0.6密耳與2密耳之間，及該載體的厚度介於大約5密耳與10密耳之間。
  4. 如申請專利範圍第1項所述之方法，其中該超音波式連結部分形成圍繞著該多個嵌板中之每一者的連續周邊。
  5. 如申請專利範圍第1項所述之方法，進一步包含切割已連結金屬箔片與金屬載體以形成多個隔離嵌板。
  6. 如申請專利範圍第5項所述之方法，其中該超音波式連結形成平行焊接線，及其中該切割步驟進一步包括沿著平行焊接線切割和在平行焊接線之間切割。
  7. 一種用於封裝積體電路裝置的方法，該方法包含： 提供箔片載體構造，該箔片載體構造包括黏著至載體的金屬箔片；將多個晶粒接附到金屬箔片上；以模製材料密封多個晶粒及至少金屬箔片的一部分以形成模製箔片載體構造；從模製箔片載體構造移除載體以形成模製箔片構造；在移除載體後蝕刻金屬箔片以在金屬箔片中定義多個裝置區域，每一個裝置區域支持至少多個晶粒的其中之一及具有多個電氣觸點，其中該蝕刻曝露了模製材料的一些部分；及在蝕刻步驟之後，單塊化該模製箔片構造以提供多個封裝積體電路裝置。
  8. 如申請專利範圍第7項所述之方法，其中該載體是金屬載體及該金屬箔片的一些部分超音波式連結到金屬載體。
  9. 如申請專利範圍第7項所述之方法，其中以黏著劑將該金屬箔片接附至該載體。
  10. 如申請專利範圍第7項所述之方法，其中該密封步驟包括以在金屬箔片上形成單一連續模製條的方式施加模製材料至多個晶粒及該金屬箔片的一部分上。
  11. 如申請專利範圍第7項所述之方法，其中：該金屬箔片包括銅層及由銀或銀合金形成的第二層；該模製材料接觸該銀層；該蝕刻步驟包括蝕刻銅層與第二層以在每一裝置區域 上形成接觸墊，而在接觸墊之間的模製材料曝露出來；及該第二層在每一接觸墊上提供焊線點。
  12. 如申請專利範圍第7項所述之方法，進一步包含將模製箔片構造放置在可重覆使用之蝕刻載體的腔室中，該蝕刻載體組構以將金屬箔片曝露於蝕刻製程之中。
  13. 如申請專利範圍第7項所述之方法，其中該金屬箔片包括金屬層，該金屬層具有以鎳與鈀覆蓋的複數個表面。
  14. 一種適於用在封裝積體電路晶粒中的配置，包含：金屬載體；及金屬箔片，該金屬箔片的一些部分超音波式連結至金屬載體，該連結部分定義在金屬箔片中的多個嵌板，且該金屬箔片的表面以銀或銀合金點鍍以形成在每一嵌板內的多個裝置區域，每一裝置區域適用於焊線至積體電路晶粒。
  15. 如申請專利範圍第14項所述之配置，其中每一嵌板包括多個裝置區域，用金屬點鍍每一裝置區域以形成適用於焊線至積體電路晶粒的電氣觸點。
  16. 如申請專利範圍第14項所述之配置，其中該載體由鋁製成及該箔片由銅製成。
  17. 如申請專利範圍第14項所述之配置，其中該超音波式連結部分形成圍繞該多個嵌板之每一者的連續周邊。
  18. 如申請專利範圍第14項所述之配置，其中該超音波式連結部分形成定義該多個嵌板之每一者之邊界的平行焊接線。
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US20100084748A1 (en) * 2008-06-04 2010-04-08 National Semiconductor Corporation Thin foil for use in packaging integrated circuits
US7836586B2 (en) * 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
JP2009143234A (ja) * 2008-12-24 2009-07-02 Nippon Mining & Metals Co Ltd キャリア付金属箔
US8101470B2 (en) 2009-09-30 2012-01-24 National Semiconductor Corporation Foil based semiconductor package
US8377267B2 (en) * 2009-09-30 2013-02-19 National Semiconductor Corporation Foil plating for semiconductor packaging
JP5546363B2 (ja) * 2010-06-11 2014-07-09 ローム株式会社 半導体装置および半導体装置の製造方法
US8389334B2 (en) 2010-08-17 2013-03-05 National Semiconductor Corporation Foil-based method for packaging intergrated circuits
TWI442488B (zh) * 2012-01-18 2014-06-21 Dawning Leading Technology Inc 用於一半導體封裝之基板製程、封裝方法、封裝結構及系統級封裝結構
US10186458B2 (en) * 2012-07-05 2019-01-22 Infineon Technologies Ag Component and method of manufacturing a component using an ultrathin carrier
US10192849B2 (en) * 2014-02-10 2019-01-29 Infineon Technologies Ag Semiconductor modules with semiconductor dies bonded to a metal foil
CN104283524B (zh) * 2014-10-22 2017-07-14 应达利电子股份有限公司 一种压电石英晶体谐振器及其制作方法
JP2016139752A (ja) * 2015-01-29 2016-08-04 日立化成株式会社 半導体装置の製造方法
KR102592483B1 (ko) * 2018-10-10 2023-10-25 주식회사 루멘스 퀀텀닷 플레이트 조립체의 제조방법
WO2019195803A1 (en) * 2018-04-06 2019-10-10 Sunpower Corporation Laser assisted metallization process for solar cell fabrication
JP7471229B2 (ja) 2018-04-06 2024-04-19 マキシオン ソーラー プライベート リミテッド レーザービームを使用した半導体基板の局所メタライゼーション
WO2019195793A1 (en) 2018-04-06 2019-10-10 Sunpower Corporation Laser assisted metallization process for solar cell stringing
WO2019195806A2 (en) 2018-04-06 2019-10-10 Sunpower Corporation Local patterning and metallization of semiconductor structures using a laser beam
US11646387B2 (en) 2018-04-06 2023-05-09 Maxeon Solar Pte. Ltd. Laser assisted metallization process for solar cell circuit formation
US10515898B2 (en) * 2018-05-14 2019-12-24 Tdk Corporation Circuit board incorporating semiconductor IC and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW415864B (en) * 1997-04-17 2000-12-21 Mitsui Mining & Smelting Co Ultrasonic welding of copper foil
TW200802636A (en) * 2006-06-20 2008-01-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4048438A (en) 1974-10-23 1977-09-13 Amp Incorporated Conductor patterned substrate providing stress release during direct attachment of integrated circuit chips
JPH0379040A (ja) * 1989-08-22 1991-04-04 Sumitomo Special Metals Co Ltd スポット状部分クラッド材の製造方法
JPH05145003A (ja) * 1991-11-21 1993-06-11 Sony Corp リードフレーム
US5308797A (en) 1992-11-24 1994-05-03 Texas Instruments Incorporated Leads for semiconductor chip assembly and method
WO1995026047A1 (en) 1994-03-18 1995-09-28 Hitachi Chemical Company, Ltd. Semiconductor package manufacturing method and semiconductor package
JP3606275B2 (ja) * 1994-03-18 2005-01-05 日立化成工業株式会社 半導体パッケージ及びその製造方法
JP3352084B2 (ja) * 1994-03-18 2002-12-03 日立化成工業株式会社 半導体素子搭載用基板及び半導体パッケージ
JPH09252014A (ja) 1996-03-15 1997-09-22 Nissan Motor Co Ltd 半導体素子の製造方法
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JP3314939B2 (ja) 1997-04-30 2002-08-19 日立化成工業株式会社 半導体装置及び半導体素子搭載用基板並びにそれらの製造方法
JP3521758B2 (ja) 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
IT1305116B1 (it) * 1998-09-14 2001-04-10 Zincocelere Spa Componente per circuito stampato multistrato, metodo per la suafabbricazione e relativo circuito stampato multiuso.
KR20000071375A (ko) 1999-02-25 2000-11-25 윌리엄 비. 켐플러 땜납 볼을 모방한 융기를 갖는 집적 회로 소자 및 그 제조방법
US6451627B1 (en) * 1999-09-07 2002-09-17 Motorola, Inc. Semiconductor device and process for manufacturing and packaging a semiconductor device
JP2001127212A (ja) 1999-10-26 2001-05-11 Hitachi Ltd 半導体装置および半導体装置の製造方法
JP2001250887A (ja) * 2000-03-08 2001-09-14 Sanyo Electric Co Ltd 回路装置の製造方法
US6586676B2 (en) * 2000-05-15 2003-07-01 Texas Instruments Incorporated Plastic chip-scale package having integrated passive components
DE10031204A1 (de) 2000-06-27 2002-01-17 Infineon Technologies Ag Systemträger für Halbleiterchips und elektronische Bauteile sowie Herstellungsverfahren für einen Systemträger und für elektronische Bauteile
KR100414479B1 (ko) * 2000-08-09 2004-01-07 주식회사 코스타트반도체 반도체 패키징 공정의 이식성 도전패턴을 갖는 테이프 및그 제조방법
US6518161B1 (en) 2001-03-07 2003-02-11 Lsi Logic Corporation Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die
JP4852802B2 (ja) * 2001-06-19 2012-01-11 住友金属鉱山株式会社 リードフレーム
KR100908891B1 (ko) * 2001-07-09 2009-07-23 스미토모 긴조쿠 고잔 가부시키가이샤 리드 프레임 및 그 제조방법
US6769174B2 (en) * 2002-07-26 2004-08-03 Stmicroeletronics, Inc. Leadframeless package structure and method
JP2004058578A (ja) 2002-07-31 2004-02-26 Hitachi Metals Ltd キャリア付き積層金属箔及びそれを用いたパッケージの製造方法
TW200411886A (en) 2002-12-26 2004-07-01 Advanced Semiconductor Eng An assembly method for a passive component
US20070176303A1 (en) 2005-12-27 2007-08-02 Makoto Murai Circuit device
US20100084748A1 (en) 2008-06-04 2010-04-08 National Semiconductor Corporation Thin foil for use in packaging integrated circuits
US7836586B2 (en) 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW415864B (en) * 1997-04-17 2000-12-21 Mitsui Mining & Smelting Co Ultrasonic welding of copper foil
TW200802636A (en) * 2006-06-20 2008-01-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof

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