TWI624018B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TWI624018B
TWI624018B TW103126538A TW103126538A TWI624018B TW I624018 B TWI624018 B TW I624018B TW 103126538 A TW103126538 A TW 103126538A TW 103126538 A TW103126538 A TW 103126538A TW I624018 B TWI624018 B TW I624018B
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Taiwan
Prior art keywords
package structure
circuit layer
insulating layer
layer
conductive
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TW103126538A
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English (en)
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TW201606961A (zh
Inventor
許詩濱
曾昭崇
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恆勁科技股份有限公司
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Application filed by 恆勁科技股份有限公司 filed Critical 恆勁科技股份有限公司
Priority to TW103126538A priority Critical patent/TWI624018B/zh
Priority to CN201410441735.8A priority patent/CN105321888B/zh
Priority to US14/558,955 priority patent/US9972599B2/en
Publication of TW201606961A publication Critical patent/TW201606961A/zh
Priority to US15/975,758 priority patent/US20180261578A1/en
Application granted granted Critical
Publication of TWI624018B publication Critical patent/TWI624018B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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Abstract

一種封裝結構之製法，係先於一承載板上形成第一線路層，且於該第一線路層上形成複數第一導電體，再以第一絕緣層包覆該第一線路層與該些第一導電體，接著於該第一絕緣層上形成第二線路層，且於該第二線路層上形成複數第二導電體，再以第二絕緣層包覆該第二線路層與該些第二導電體，之後於該第二絕緣層形成至少一開口，以於該開口中設置至少一電子元件，故藉由先形成兩絕緣層，再形成該開口，因而不需堆疊或壓合已開口之基材，使該電子元件不會受壓迫而位移，以減少良率損失。本發明復提供該封裝結構。

Description

封裝結構及其製法
本發明係有關一種封裝結構，尤指一種嵌埋電子元件之封裝結構及其製法。
隨著半導體封裝技術的演進，於智慧型手機、平板、網路、筆記型電腦等產品中，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而該半導體裝置主要係在一封裝基板(package substrate)裝置晶片，且將晶片電性連接在該封裝基板上，接著再以膠體進行封裝；而為降低封裝高度，遂有將晶片嵌埋在一封裝基板中，而此種封裝件能縮減整體半導體裝置之體積並提昇電性功能，遂成為一種封裝的趨勢。
第1A至1D圖係為習知封裝結構1之製法的剖視示意圖。
如第1A圖所示，提供一具有貫穿之開口130之核心板13，於該核心板13之上、下兩側具有複數內層線路11與一銅窗110，且於該核心板13中形成複數導電柱12，以電性連接上、下兩側之內層線路11。
如第1B圖所示，於該核心板13底側設置一承載板10，如聚醯亞胺(Polyimide，簡稱PI)膠帶，以將一具有複數電極墊180之半導體晶片18容置於該開口130中，且該半導體晶片18設於該承載板10上。藉由該銅窗110之設計，可避免該半導體晶片18接觸該內層線路11。
如第1C圖所示，於該核心板13上側及半導體晶片18上壓合一介電材料，使該介電材料填入該開口130之孔壁與半導體晶片18之間的間隙中，再移除該承載板10，之後壓合另一介電材料於該核心板13下側，使兩介電材料形成一介電材料層16。
如第1D圖所示，於該介電材料層16之上、下側分別形成一線路層14，且該線路層14具有位於該介電材料層16中並電性連接該電極墊180與內層線路11之導電體15。
然而，習知封裝結構1之製法中，因使用該銅窗110作阻隔層，會減少該內層線路11之佈線區域，且以CO2雷射形成該開口130，會增加雷射製程與成本，並使該核心板13之有機玻纖露出，因而導致影響該半導體晶片18置放良率與品質。
再者，需使用雷射製程製作盲孔(即該導電體15之位置)或通孔(即該導電柱12之位置)，故僅能製作圓形孔型，且孔型不佳。
又，使用PI膠帶(該承載板10)固定該半導體晶片18，不僅需增加貼膠帶與撕膠帶製程，且增加膠帶耗材與設備成本。
另外，需經過兩次介電材料之製作，再進行壓合以形成該介電材料層16，故需進行預壓製程與固化(Cure)壓合製程，不僅增加製程時間與成本，且導致該半導體晶片18產生偏移(甚至旋轉)，因而不易準確定位於該開口130中，以致於該半導體晶片18之電極墊180不易與該導電體15精準對應，而容易產生電性連接之品質不良或失效的情況，導致降低產品的良率。
第1A’至1D’圖係為另一習知封裝結構1’之製法的剖視示意圖。
如第1A’圖所示，於一如銅箔基板之承載板10上形成一第一線路層11’，且將一被動元件18’，如積層陶瓷電容器(Multi-layer Ceramic Capacitor，簡稱MLCC)藉由絕緣膠材180’固定於該第一線路層11’上。
如第1B’圖所示，將一具有貫穿之開口130之第一介電材料層13’設於該承載板10上，且該被動元件18’容置於該開口130中。
如第1C’圖所示，於該第一介電材料層13’上側及該被動元件18’上壓合第二介電材料層，且該第二介電材料層填入於該開口130之孔壁與被動元件18’之間的間隙中，使該第一介電材料層13’與該第二介電層熱壓形成一介電材料包覆層16’，以將該被動元件18’與該第一線路層11’固定於該介電材料包覆層16’中。
如第1D’圖所示，於該介電材料包覆層16’之上側上形成第二線路層14’，且該第二線路層14’具有位於該介電材 料包覆層16’中並電性連接該被動元件18’之導電體15。接著，移除該承載板10以外露該第一線路層11’。
惟，習知封裝結構1’之製法中，因使用銅箔基板作該承載板10，故容易產生分層，而造成結構損壞，且需使用雷射製程製作盲孔(即該導電體15之位置)，故僅能製作圓形孔型，且孔型不佳。
再者，使用非導電材與點膠方式黏著該被動元件18’，由於點膠的膠粒直徑大於200um，故每次點膠的粒徑誤差極大，因而不易控制，導致該絕緣膠材180’容易擴流至其它區域，以致於該第一線路層11’之各線路間易受膠材黏著，而有信賴度之風險。
又，需經過兩次介電材料層之製作，再進行壓合以形成該介電材料包覆層16’，故該第一介電材料層13’與該第二介電材料層兩者之置放容易錯位，不僅增加製程時間與成本，且該被動元件18’置放後而於烘烤該介電材料包覆層16’之前，該被動元件18’並未固定，故該被動元件18’容易偏移，而造成良率損失。
另外，使用該導電體15對該被動元件18’作單側之電性導通，會增加電性路徑及訊號損失之風險，且使用銅電極MLCC做為該被動元件18’，其非一般封裝界使用之元件，故成本極高。
因此，如何避免習知技術中之種種缺失，實已成為目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種封裝結構，係包括：第一絕緣層，係具有相對之第一表面及第二表面；第一線路層，係結合於該第一絕緣層之第一表面；複數第一導電體，係設於該第一絕緣層中並電性連接該第一線路層；第二線路層，係設於該第一絕緣層之第二表面上並藉由該些第一導電體電性連接該第一線路層；複數第二導電體，係設於該第二線路層上；第二絕緣層，係設於該第一絕緣層之第二表面上並包覆該第二線路層與該些二導電體，且該第二絕緣層上具有至少一開口，以令該第二線路層之部分表面外露於該開口；以及至少一電子元件，係設於該開口中並電性連接該第二線路層。
本發明復提供一種封裝結構之製法，係包括：於一承載板上形成第一線路層；於該第一線路層上形成複數第一導電體；於該承載板上形成一具有相對之第一表面及第二表面的第一絕緣層，以令該第一絕緣層包覆該第一線路層與該些第一導電體，且該第一絕緣層係藉其第一表面結合至該承載板上；於該第一絕緣層之第二表面上形成第二線路層，以令該第二線路層藉由該些第一導電體電性連接該第一線路層；於該第二線路層上形成複數第二導電體；於該第一絕緣層之第二表面上形成第二絕緣層，以令該第二絕緣層包覆該第二線路層與該些二導電體；於該第二絕緣層形成至少一開口，以令該第二線路層之部分表面外露於該開口；以及於該開口中設置至少一電子元件，且該電子元件電性連接該第二線路層。
由上可知，本發明封裝結構及其製法，係先形成兩層線路佈設，再於第二絕緣層上形成開口，以有效利用該些第二導電體以外的無效區域製作該開口，而有效使用立體空間，不僅能縮小封裝後整體體積與增加該第二線路層之佈線應用，且可增加電性與訊號穩定。
再者，本發明未使用核心板，因而更能縮小整體基板尺寸，以提升佈線使用率。
另外，本發明不需堆疊或壓合已開口之基材，故該電子元件不會受壓迫而位移，因而能有效定位該電子元件，以減少良率損失。
1,1’,2,3‧‧‧封裝結構
10,20‧‧‧承載板
11‧‧‧內層線路
11’,21‧‧‧第一線路層
110‧‧‧銅窗
12‧‧‧導電柱
13‧‧‧核心板
13’‧‧‧第一介電材料層
130,260,260’‧‧‧開口
14‧‧‧線路層
14’,24,24’,24”,34‧‧‧第二線路層
15‧‧‧導電體
16‧‧‧介電材料層
16’‧‧‧介電材料包覆層
18‧‧‧半導體晶片
18’‧‧‧被動元件
180‧‧‧電極墊
180’‧‧‧絕緣膠材
20‧‧‧承載件
21a,24a,24a’,24a”‧‧‧表面
210‧‧‧電性連接墊
211,241,341‧‧‧導電跡線
22‧‧‧第一導電體
22a‧‧‧端面
23‧‧‧第一絕緣層
23a‧‧‧第一表面
23b‧‧‧第二表面
240,340‧‧‧電性接觸墊
25‧‧‧第二導電體
26‧‧‧第二絕緣層
260a‧‧‧底面
27‧‧‧阻層
270‧‧‧開口區
28,28’,28a,28b‧‧‧電子元件
280‧‧‧導電材料
29‧‧‧導電元件
第1A至1D圖係為習知封裝結構之製法的剖視示意圖；第1A’至1D’圖係為習知封裝結構之另一製法的剖視示意圖；第2A至2G圖係為本發明之封裝結構之製法之剖視示意圖；其中，第2F’及2F”圖係為第2F圖之其它不同態樣，第2G’及2G”圖係為第2G圖之其它不同態樣；以及第3圖係為本發明之封裝結構之另一實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之封裝結構2之製法之剖視示意圖。
如第2A圖所示，藉由圖案化製程於一承載板20上形成一第一線路層21，再於該第一線路層21上形成複數第一導電體22。
於本實施例中，該承載板20係為基材，例如銅箔基板或其它板體，並無特別限制。
再者，該第一線路層21係包含複數電性連接墊210與複數導電跡線211，且該第一導電體22係為導電柱，如銅柱。
如第2B圖所示，於該承載板20上形成一具有相對之第一表面23a及第二表面23b的第一絕緣層23，以令該第一絕緣層23包覆該第一線路層21與該些第一導電體22， 且該第一絕緣層23係藉其第一表面23a結合至該承載板20上。
於本實施例中，該些第一導電體22之一端面22a係外露於該第一絕緣層23之第二表面23b。
再者，該第一線路層21之表面21a係齊平該第一絕緣層23之第一表面23a。
又，該第一絕緣層23係以壓合或鑄模(molding)方式製作。
如第2C圖所示，於該第一絕緣層23之第二表面23b上形成一第二線路層24，以令該第二線路層24藉由該些第一導電體22電性連接該第一線路層21。接著，於該第二線路層24上形成複數第二導電體25，再於該第一絕緣層23之第二表面23b上形成一第二絕緣層26，以令該第二絕緣層26包覆該第二線路層24與該些第二導電體25。
於本實施例中，該第二線路層24係包含複數電性接觸墊240與複數導電跡線241，且該些電性接觸墊240與該導電跡線241係直接連接該些第一導電體22。
再者，該第二導電體25係為導電柱，如銅柱，且該第二導電體25之一端面外露於該第二絕緣層26。
又，該第二絕緣層26係以壓合或鑄模(molding)方式製作。
如第2D圖所示，形成一如光阻之阻層27於該第二絕緣層26上，且該阻層27具有至少一開口區270，以令該第二絕緣層26之部分表面外露於該開口區270。接著，於 該開口區270中之第二絕緣層26上形成至少一開口260，令該第二線路層24之部分表面(即該些電性接觸墊240)外露於該開口260。
於本實施例中，該開口260係以如噴砂法(pumice)之研磨方式製作或以雷射燒灼方式製作，並非採用傳統銑刀成型方式製作，故可縮小該開口260於轉彎處之導角(如底面處、開口處)。
再者，該第二線路層24之表面24a係齊平該開口260之底面260a。
又，該些電性接觸墊240未受雷射或銑刀、鑽針破壞而凹陷，故該些電性接觸墊240能保持表面完整。
如第2E圖所示，移除該阻層27。於本實施例中，該第二導電體25之一端面外露於該第二絕緣層26，因而無需於該第二導電體25上製作接觸墊，以有效利用各該第二導電體25之間的空間而形成該開口260。
如第2F圖所示，移除該承載板20，且於該開口260中設置至少一電子元件28，因而該電子元件28不會包覆於該第一絕緣層23或第二絕緣層26中，並使該電子元件28電性連接該第二線路層24之電性接觸墊240。本發明之製法未使用傳統銑刀成型方式，故可縮小該電子元件28與該開口260之孔壁間的距離。
於本實施例中，該電子元件28係可為主動元件、被動元件或其二者組合，且該主動元件係例如半導體元件(如晶片)，而該被動元件係例如電阻、電容及電感。其中， 第2F圖所示之電子元件28係為被動元件，如積層陶瓷電容器(Multi-layer Ceramic Capacitor，簡稱MLCC)，且該電子元件28係使用現行封裝界之焊錫製程製作，而無需使用較高成本之銅電極，以降低成本。
再者，該電子元件28係藉由印刷或點膠等之導電材料280(如焊料或導電膠)固接並電性連接於該些電性接觸墊240上，且藉由限制各該電性接觸墊240之尺寸或形狀，以防止膠材擴散至相鄰之電性接觸墊240。
又，於另一實施例中，如第2F’圖所示，該電子元件28’係為主動元件，且各該電性接觸墊240間可依需求增設線路，以對應該電子元件28’之接點。
另外，如第2F”圖所示，可於該開口260’內形成高低不等之平面，即該開口260’內係為階梯狀，以於不同高度之階面上設置複數電子元件28a,28b而增加立體空間使用率，例如，其中一電子元件28a係為被動元件，而另一電子元件28b係為主動元件。
如第2G圖所示，形成複數如焊球之導電元件29於該第二絕緣層26上，且該些導電元件29電性連接該些第二導電體25，以藉由該些導電元件29堆疊結合其它電子裝置(圖略)。
於本實施例中，藉由該些導電元件29之設計以增加利用空間，故於後續堆疊製程時，該電子元件28不會碰撞其它電子裝置。
於其它實施例中，依孔深設計，該第二線路層24’之 表面24a’係高於該開口260之底面260a，如第2G’圖所示；或者，該第二線路層24”之表面24a”係低於該開口260之底面260a，如第2G”圖所示之嵌埋式線路。
另外，如第3圖所示，該第二線路層34之電性接觸墊340藉由該導電跡線341間接連接該第一導電體22，亦即該電性接觸墊340並未直接連接該第一導電體22。
本發明封裝結構2之製法中，利用各該第二導電體25之間的無效區域製作開口260，以有效使用立體空間，不僅縮小封裝後整體體積(如厚度)與增加該第二線路層24之佈線應用，且可增加電性與訊號穩定。
再者，相較於習知使用玻璃纖維作為介電材料內埋元件結構，本發明未使用核心板，因而更能縮小整體基板尺寸，以改善於有限空間內之佈線使用率。
又，本發明不需堆疊或壓合已開口之基材，故該電子元件28不會受壓迫而位移，因而能有效定位該電子元件28，以減少良率損失。
另外，傳統電路板與球柵陣列封裝(Ball Grid Array，簡稱BGA)等電路板製程需使用多張介電材料層壓合才能完成內埋式元件製程，因而該內埋式元件之高度與該介電層之厚度會產生配合不易等問題。若使用凹槽(cavity)方式內埋電子元件，常見開口製程係利用機械式成型機與銑刀等工具，故每一凹槽需將每一介電材料層進行開口，因而耗時長，且物料成本增加。若使用本發明進行內埋元件，只需使用一般表面黏著技術(Surface Mount Technology， 簡稱SMT)之封裝流程，再以鑄模(molding)方式一次完成，故無需使用多張介電材料層與進行多次開口製程。若外層開口製程(如該開口260)因使用本發明製程材料特性，因而可用一次性生產或整面性生產，如噴砂法(pumice)，藉以縮短生產時程與成本，此方式為傳統傳統電路板或BGA等電路板所無法製作出的。
本發明復提供一種封裝結構2,3，係包括：一第一絕緣層23、一第一線路層21、複數第一導電體22、一第二線路層24,34、複數第二導電體25、一第二絕緣層26、以及至少一電子元件28。
所述之第一絕緣層23係具有相對之第一表面23a及第二表面23b。
所述之第一線路層21係結合於該第一絕緣層23之第一表面23a。例如，該第一線路層21係嵌埋於該第一絕緣層23之第一表面23a且齊平該第一表面23a。
所述之第一導電體22係為導電柱，其設於該第一絕緣層23中並連通該第二表面23b且電性連接該第一線路層21。
所述之第二線路層24,34係設於該第一絕緣層23之第二表面23b上並藉由該些第一導電體22電性連接該第一線路層21。
所述之第二導電體25係為導電柱，其設於該第二線路層24上。
所述之第二絕緣層26係設於該第一絕緣層23之第二 表面23b上並包覆該第二線路層24與該些二導電體25，且該第二絕緣層26上具有至少一開口260，以令該第二線路層24之部分表面外露於該開口260。
所述之電子元件28係設於該開口260中並電性連接該第二線路層24。例如，該電子元件28,28’,28a,28b係為主動元件、被動元件或其二者組合。
於一實施例中，該第二線路層24,24’之表面24a,24a’係高於或齊平該開口260之底面260a。
於一實施例中，該第二線路層24”之表面24a”係低於該開口260之底面260a。
於一實施例中，該第二線路層24,34係包含複數電性接觸墊340,340與電性連接該電性接觸墊240,340之複數導電跡線341,341，且該些電性接觸墊240,340係結合並電性連接該電子元件28。其中，該電性接觸墊24係連接該第一導電體22；或者，該電性接觸墊34係未連接該第一導電體22，且該導電跡線341係連接該第一導電體22。
於一實施例中，該開口260’內係為階梯狀。
於一實施例中，所述之封裝結構2復包括設於該第二絕緣層26上之複數導電元件29，係電性連接各該第二導電體25。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。

Claims (26)

  1. 一種封裝結構，係包括：第一絕緣層，係具有相對之第一表面及第二表面；第一線路層，係結合於該第一絕緣層之第一表面；複數第一導電體，係設於該第一絕緣層中並電性連接該第一線路層；第二線路層，係形成於該第一絕緣層之第二表面上並藉由該些第一導電體電性連接該第一線路層；複數第二導電體，係設於該第二線路層上；第二絕緣層，係形成於該第一絕緣層之第二表面上並包覆該第二線路層與該些二導電體，且該第二絕緣層上具有至少一開口，並於該第二絕緣層與該第一絕緣層中對應該開口之區域具有部分該第二線路層、部分該第一導電體與部分該第一線路層，以令部分該第二線路層之表面外露於該開口；以及至少一電子元件，係設於該開口中並電性連接該第二線路層。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該第一線路層係嵌埋於該第一絕緣層之第一表面。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該第一導電體係為導電柱。
  4. 如申請專利範圍第1項所述之封裝結構，其中，該第二導電體係為導電柱。
  5. 如申請專利範圍第1項所述之封裝結構，其中，該第 二線路層之表面係高於或齊平該開口之底面。
  6. 如申請專利範圍第1項所述之封裝結構，其中，該第二線路層之表面係低於該開口之底面。
  7. 如申請專利範圍第1項所述之封裝結構，其中，該第二線路層係包含複數電性接觸墊與複數導電跡線，且該些電性接觸墊係結合並電性連接該電子元件。
  8. 如申請專利範圍第7項所述之封裝結構，其中，該電性接觸墊係連接該第一導電體。
  9. 如申請專利範圍第7項所述之封裝結構，其中，該電性接觸墊係未連接該第一導電體，且該導電跡線係連接該第一導電體。
  10. 如申請專利範圍第1項所述之封裝結構，其中，該開口內係為階梯狀。
  11. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件係為主動元件、被動元件或其二者之組合。
  12. 如申請專利範圍第1項所述之封裝結構，復包括設於該第二絕緣層上之複數導電元件，係電性連接各該第二導電體。
  13. 一種封裝結構之製法，係包括：於一承載板上形成第一線路層；於該第一線路層上形成複數第一導電體；於該承載板上形成一具有相對之第一表面及第二表面的第一絕緣層，以令該第一絕緣層包覆該第一線路層與該些第一導電體，且該第一絕緣層係藉其第一 表面結合至該承載板上；於該第一絕緣層之第二表面上形成第二線路層，以令該第二線路層藉由該些第一導電體電性連接該第一線路層；於該第二線路層上形成複數第二導電體；於該第一絕緣層之第二表面上形成第二絕緣層，以令該第二絕緣層包覆該第二線路層與該些第二導電體；於該第二絕緣層形成至少一開口，以令該第二線路層之部分表面外露於該開口；以及於該開口中設置至少一電子元件，且令該電子元件電性連接該第二線路層。
  14. 如申請專利範圍第13項所述之封裝結構之製法，其中，該第一線路層之表面係齊平該第一絕緣層之第一表面。
  15. 如申請專利範圍第13項所述之封裝結構之製法，其中，該第一導電體係為導電柱。
  16. 如申請專利範圍第13項所述之封裝結構之製法，其中，該第二導電體係為導電柱。
  17. 如申請專利範圍第13項所述之封裝結構之製法，其中，該第二線路層之表面係高於或齊平該開口之底面。
  18. 如申請專利範圍第13項所述之封裝結構之製法，其中，該第二線路層之表面係低於該開口之底面。
  19. 如申請專利範圍第13項所述之封裝結構之製法，其 中，該第二線路層係包含複數電性接觸墊與複數導電跡線，且該些電性接觸墊係結合並電性連接該電子元件。
  20. 如申請專利範圍第19項所述之封裝結構之製法，其中，該電性接觸墊係連接該第一導電體。
  21. 如申請專利範圍第19項所述之封裝結構之製法，其中，該電性接觸墊係未連接該第一導電體，且該導電跡線係連接該第一導電體。
  22. 如申請專利範圍第13項所述之封裝結構之製法，其中，該開口係以研磨方式或雷射方式製作。
  23. 如申請專利範圍第13項所述之封裝結構之製法，其中，該開口內係為階梯狀。
  24. 如申請專利範圍第13項所述之封裝結構之製法，其中，該電子元件係為主動元件、被動元件或其二者組合。
  25. 如申請專利範圍第13項所述之封裝結構之製法，復包括形成複數導電元件於該第二絕緣層上，且該些導電元件電性連接該些第二導電體。
  26. 如申請專利範圍第13項所述之封裝結構之製法，復包括於形成該開口之後，移除該承載板。
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