TW201530729A - 層疊封裝元件及其製造方法 - Google Patents

層疊封裝元件及其製造方法 Download PDF

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Publication number
TW201530729A
TW201530729A TW103145039A TW103145039A TW201530729A TW 201530729 A TW201530729 A TW 201530729A TW 103145039 A TW103145039 A TW 103145039A TW 103145039 A TW103145039 A TW 103145039A TW 201530729 A TW201530729 A TW 201530729A
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Taiwan
Prior art keywords
package
logic
memory
wafer
package structure
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TW103145039A
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English (en)
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TWI588965B (zh
Inventor
Chen-Hua Yu
Kuo-Chung Yee
Mirng-Ji Lii
Chien-Hsun Lee
Jiun-Yi Wu
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201530729A publication Critical patent/TW201530729A/zh
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

一實施例之層疊封裝(package-on-package，PoP)元件包含封裝結構、封裝基板、以及複數個連接件將封裝結構接合至封裝基板。封裝結構包含邏輯晶片接合至記憶晶片、模封化合物包圍記憶晶片、以及複數個導電柱延伸穿過模封化合物。這些導電柱附著在邏輯晶片上之接觸墊。

Description

積體電路封裝及其製造方法 【優先權主張及交互參照】
本案主張2014年1月17日申請之美國臨時申請案第61/928,887號，名稱為「積體電路封裝及其製造方法」的權利，在此一併列入參考。
本發明是有關於一種積體電路製作技術，且特別是有關於一種積體電路封裝及其製造方法。
3D封裝應用，例如層疊封裝(package on package，PoP)，已變得愈來愈受歡迎且廣泛地應用在行動裝置中，因其可藉由例如增加帶寬(bandwidth)以及縮短邏輯晶片(例如應用處理器)與記憶晶片之間之繞線距離的方式來提升電性性能。然而，隨著寬輸入/輸出(wide IO)記憶晶片的出現，對於較高速與較低功率需求、封裝體尺寸與封裝層之數量需求逐漸增加。較大且較厚之元件及實際尺寸電性性能變得更受限。因在球狀接合處的良率損失，而導致利用傳統球狀接合封裝來符合微細通道與高密度繞線需 求之現存層疊封裝元件遭遇挑戰。故，需要改進之元件及其製造方法。
依照一實施例，一種層疊封裝元件包含封裝結構、封裝基板、以及複數個連接件將封裝結構接合至封裝基板。封裝結構包含邏輯晶片接合至記憶晶片、模封化合物包圍記憶晶片、以及複數個導電柱延伸穿過模封化合物。這些導電柱附著在邏輯晶片上之接觸墊。
依照另一實施例，一種層疊封裝元件包含邏輯晶片、模封化合物包圍邏輯晶片、以及一或多個第一重新分布層設於邏輯晶片與模封化合物之上方。此層疊封裝元件更包含複數個穿模介層窗，延伸穿過模封化合物且附著於一或複數個第二重新分布層。此一或複數個第二重新分布層設於模封化合物與邏輯晶片下。記憶晶片設於此一或複數個第一重新分布層之上方，且此一或複數個第一重新分布層將記憶晶片電性連接至邏輯晶片與穿模介層窗。
依照又一實施例，一種層疊封裝元件之製造方法，包含形成第一封裝結構以及接合第一封裝結構於封裝基板。形成第一封裝結構之方法包含接合邏輯晶片於記憶晶片(其中邏輯晶片包含複數個第一接觸墊)、將複數個第一預形成之導電柱附著於第一接觸墊、以及施加第一模封化合物於邏輯晶片上方且介於記憶晶片與每一預形成之導電柱之間。此方法更包含將複數個第二預形成之導電柱附著於封裝 基板上之複數個第二接觸墊、以及施加第二模封化合物於封裝基板之上方且介於第一封裝結構與每一第二導電柱之間。
100‧‧‧封裝結構
102‧‧‧邏輯晶片
103‧‧‧接觸墊
104‧‧‧記憶晶片
106‧‧‧連接件
106A‧‧‧連接件
106B‧‧‧連接件
108‧‧‧接觸墊
110‧‧‧底部填充材
112‧‧‧導電柱/穿模介層窗
114‧‧‧模封化合物
116‧‧‧重新分布層
118‧‧‧連接件
120‧‧‧底部填充材
122‧‧‧接觸墊
124‧‧‧封裝基板
126‧‧‧導電柱/穿模介層窗
128‧‧‧模封化合物
130‧‧‧連接件
200‧‧‧層疊封裝元件
300‧‧‧封裝結構
302‧‧‧封裝基板
304‧‧‧動態隨機存取記憶晶粒
306‧‧‧接合線
308‧‧‧模封化合物
310‧‧‧連接件
400‧‧‧層疊封裝元件
401‧‧‧載體
402‧‧‧重新分布層
404‧‧‧接觸墊
406‧‧‧導電柱/穿模介層窗
408‧‧‧導電樁
410‧‧‧模封化合物
412‧‧‧重新分布層
414‧‧‧連接件
416‧‧‧底部填充材
418‧‧‧連接件
450‧‧‧保護層
從以下結合所附圖式所做的詳細描述，可對本揭露之態樣有更佳的了解。需注意的是，根據業界的標準實務，各特徵並未依比例繪示。事實上，為了使討論更為清楚，各特徵的尺寸可任意地增加或減少。〔圖1〕至〔圖10〕係繪示依照本發明之一些實施方式製造一種層疊封裝元件之各個中間階段的剖面示意圖；〔圖11〕至〔圖19〕係繪示依照本發明之一些替代實施方式製造一種層疊封裝元件之各個中間階段的剖面示意圖；〔圖20〕至〔圖25〕係繪示依照本發明之一些其他替代實施方式製造一種層疊封裝元件之各個中間階段的剖面示意圖；以及〔圖26A〕與〔圖26B〕係繪示依照本發明之一些實施方式的導電柱的透視示意圖與剖面示意圖。
以下的揭露提供了許多不同的實施例或例子，以實施所提供之標的之不同特徵。以下所描述之構件與安排的特定例子係用以簡化本揭露。當然這些僅為例子，並非用 以作為限制。舉例而言，在描述中，第一特徵形成於第二特徵上方或上，可能包含第一特徵與第二特徵以直接接觸的方式形成的實施例，而也可能包含額外特徵可能形成在第一特徵與第二特徵之間的實施例，如此第一特徵與第二特徵可能不會直接接觸。此外，本揭露可能會在各例子中重複參考數字及/或文字。這樣的重複係基於簡單與清楚之目的，以其本身而言並非用以指定所討論之各實施例及/或配置之間的關係。
另外，在此說明中可能會使用空間相對用語，例如「向下(beneath)」、「下方(below)」、「較低(lower)」、「上方(above)」、「較高(upper)」等等，以方便說明如圖式所繪示之一元件或一特徵與另一(另一些)元件或特徵之關係。除了在圖中所繪示之方向外，這些空間相對用詞意欲含括元件在使用或操作中的不同方位。設備可能以不同方式定位(旋轉90度或在其他方位上)，因此可利用同樣的方式來解釋在此所使用之空間相對描述符號。
各實施例包含具有邏輯與記憶晶片的層疊封裝元件。可利用扇出(fan-out)、層疊晶片(chip-on-chip)與晶片基板鍵合(chip-on-substrate)結構來完成邏輯與記憶晶片之間的互連。這些結構可使每一晶片之輸入/輸出(IO)墊具有改善分布，並提供現存層疊封裝元件各式各樣的優點。舉例而言，各實施例可符合系統級封裝(SiP)之微球間距需求，來以寬輸入輸出記憶堆疊方式互連邏輯晶片[例如應用處理器(AP)]。其他有利特徵可包含速度與功率消耗的 改善、較低之製作成本、能力增加、良率提升、較薄之形狀因子(form factor)、層次2之可靠裕度的改善等等。
圖1至圖10係繪示依照本發明之一些實施方式製造一種層疊封裝元件200(請參照圖10)之各個中間階段的剖面示意圖。在圖1至圖5中，形成層疊晶片型的封裝結構100。圖1繪示二半導體晶片，例如邏輯晶片102與記憶晶片104，之剖面示意圖。邏輯晶片102可為應用處理器，然亦可使用其他種半導體晶片(例如記憶晶片)。記憶晶片104可為寬輸入/輸出晶片(例如具有一千或更多連接件106B/接觸墊)，然亦可使用其他種半導體晶片(例如其他型式之記憶晶片)。在一些示範實施例中，邏輯晶片102與記憶晶片104均具有約40μm至約300μm的厚度。
連接件106A與106B可分別設置在邏輯晶片102與記憶晶片104上。在一些實施例中，連接件106A與106B可為間距約30μm至約100μm的微凸塊(μbump)。接觸墊108亦可設置在邏輯晶片102之上表面上。如圖1所示，邏輯晶片102可具有較記憶晶片104大的橫向尺寸，而可使接觸墊108設置在邏輯晶片102之周邊區處，因而仍可提供足夠之連接件106A來接合記憶晶片104的連接件106。
接下來，如圖2所示，接合邏輯晶片102與記憶晶片104。舉例而言，可在連接件106A與106B(如圖2所示之接合連接件106)上進行回銲。接著，可施加底部填充材110於邏輯晶片102與記憶晶片104之間並環繞連接件106。底部填充材110可提供接合件106支撐。於接合後， 接觸墊108可在邏輯晶片102之上表面上維持暴露。在一些實施例中，接合之連接件106可具有約30μm至約100μm的均高(standoff height)。
圖3係繪示導電柱112附著在接觸墊108。導電柱112可由導電材料，例如銅、金、銀及其類似物所形成。導電柱112可為預形成之結構，而附著於接觸墊108。舉例而言，圖26A與圖26B繪示示範導電柱112之透視示意圖與剖面示意圖。可利用打線器(wire bonder)或其他適合設備將導電柱112裝設在接觸墊108。在一些實施例中，導電柱112可具有約100μm至約500μm的間距。
請參照圖4，施加模封化合物114於邏輯晶片102之上方，以填充導電柱112與記憶晶片104之間的間隙。模封化合物114可包含任何適合材料，例如環氧樹脂、模封底部填充材及其類似材料。形成模封化合物114之適合方法可包含壓縮成型(compressive molding)、轉注成型(transfer molding)、液態封膠成型(liquid encapsulent molding)及其類似方法。舉例而言，模封化合物114可以液體形式施加在導電柱112與記憶晶片104之間。隨後，進行硬化製程，以固化模封化合物114。模封化合物114之填充可超過導電柱112/記憶晶片104，如此模封化合物114覆蓋導電柱112/記憶晶片104之上表面。可進行化學機械研磨(CMP)(或其他研磨/回蝕技術)，以暴露出導電柱112/記憶晶片104之上表面。在所產生之結構中，模封化合物114、導電柱112與記憶晶片104之暴露表面可實質等高。此外， 導電柱112可延伸穿過模封化合物114，因此導電柱112亦可稱為穿模介層窗(through-molding via，TMV)112。在封裝結構100之由上而下的視圖(未繪示)中，模封化合物114可包圍記憶晶片104。在一些實施例中，於化學機械研磨進行後，模封化合物114可具有約70μm至約500μm的厚度。
可形成互連結構，例如一或多個重新分布層(redistribution layer，RDL)116，在記憶晶片104與模封化合物114上。亦可形成連接件118在重新分布層116之相對於記憶晶片104的表面上。所形成之層疊晶片型的封裝結構100繪示於圖5中。封裝結構100包含接合之半導體晶片(即邏輯晶片102與記憶晶片104)、導電柱112、模封化合物114、重新分布層116與連接件118。重新分布層116可橫向延伸經過記憶晶片104之邊而至模封化合物114與導電柱112之上方。重新分布層116可包含形成在一或多個聚合物層中的數個互連結構(例如導電線及/或介層窗)。可利用任何適合方法，例如旋轉塗布技術及其類似技術，以任何適合材料[例如聚亞醯胺(PI)、聚苯噁唑(polybenzoxazole，PBO)、苯環丁烯(benzocyclobuten，BCB)、環氧化物、矽氧樹脂(silicone)、丙烯酸酯(acrylates)、奈米複合酚醛樹脂(nano-filled pheno resin)、矽氧烷(siloxane)、氟化聚合物、聚降冰片烯(polynorbornene)及其類似物]，來形成聚合物層。當記憶晶片104之方位係位於邏輯晶片102 之上方的情況下(例如圖1至圖4所示之方位)，聚合物層可形成在記憶晶片104之上方。
重新分布層116中之互連結構可形成在聚合物層中，且電性連接至記憶晶片104及/或邏輯晶片102(例如利用導電柱112)。互連結構的製作可包含圖案化聚合物層(例如利用微影與蝕刻製程的組合)，以及在經圖案化之聚合物層中形成互連結構(例如沉積晶種層與利用罩幕層來定義互連結構的形狀)。於重新分布層116形成後，形成連接件118於重新分布層116上。連接件118可例如為具有約60μm至約200μm之間距的控制崩潰晶片接合(C4)凸塊。接著，可將封裝結構100之方位翻轉成如圖5所示。
在圖6中，利用連接件118，將封裝結構100接合至封裝基板124。舉例而言，可對連接件118進行回銲，且可施加底部填充材120於封裝結構100與封裝基板124之間並環繞連接件118。底部填充材120可提供連接件118支撐。封裝基板124可為印刷電路板、中介層或其類似物。此外，封裝基板124可包含互連結構(未繪示)，且可利用連接件118與其他在封裝結構100中的互連結構(例如重新分布層116與導電柱112)，而電性連接至封裝結構100中之構件(例如邏輯晶片102及/或記憶晶片104)。封裝基板124可橫向延伸經過封裝結構100之邊，且接觸墊122可在封裝基板124之上表面上被暴露出。
圖7繪示出導電柱126附著於封裝基板124上之接觸墊122。導電柱126可實質類似於封裝結構100中的導 電柱112。舉例而言，導電柱112可為包含導電材料(例如銅、銀、金及其類似物)之預形成之結構，且附著於接觸墊122。在一些實施例中，導電柱126可具有約100μm至約500μm的間距。
請參照圖8，模封化合物128施加在封裝基板124上方，以填充導電柱126與封裝結構100之間的間隙。模封化合物128可實質類似於封裝結構100中的模封化合物114。模封化合物128之填充可超過導電柱126/封裝結構100，如此模封化合物128覆蓋導電柱126/封裝結構100之上表面。可進行化學機械研磨(或其他研磨/回蝕技術)，以暴露出導電柱126/封裝結構100之上表面。在所產生之結構中，模封化合物128、導電柱126與封裝結構100之橫向表面可實質等高。此外，導電柱126可延伸穿過模封化合物128，因此導電柱126亦可稱為穿模介層窗126。在由上而下的視圖(未繪示)中，模封化合物128可包圍封裝結構100。在一些實施例中，於化學機械研磨進行後，模封化合物128可具有約140μm至約900μm的厚度。
圖9係繪示連接件130[例如球柵陣列(BGA)之球]形成在封裝基板124之相對於封裝結構100的表面上。因而形成層疊封裝元件200。在一些實施例中，連接件130具有約250μm至約500μm的間距。連接件130可用以將層疊封裝元件400電性連接至一電性系統之主機板(未繪示)或另一元件構件。
額外的封裝構件可選擇性地包含在層疊封裝元件200中。舉例而言，另一積體封裝(IC)封裝結構300可透過導電柱126而電性連接於封裝基板124。所形成之結構繪示於圖10中。封裝結構300可為記憶體封裝，例如低功率雙倍數據傳輸率2(LP-DDR2)封裝、低功率雙倍數據傳輸率3(LP-DDR3)封裝、低功率雙倍數據傳輸率x(LP-DDRx)封裝、寬出入輸出封裝及類似結構。封裝結構300可包含複數個堆疊之記憶晶粒[例如動態隨機存取記憶(DRAM)晶粒304]，這些動態隨機存取記憶晶粒304利用例如接合線306接合於封裝基板302。動態隨機存取記憶晶粒304與接合線306可為保護之模封化合物308所包覆。亦可使用其他類型之封裝結構。替代地，根據封裝設計，可省略封裝結構300。
封裝基板302可包含互連結構(例如導電線及/或介層窗)，而提供電性連接予各個動態隨機存取記憶晶粒304。連接件310可設置在封裝基板302之底面上。連接件310可將封裝結構300接合至導電柱126，導電柱126可將封裝結構300電性連接至封裝基板126。邏輯晶片102及/或記憶晶片104可透過重新分布層116、封裝基板124、導電柱126與封裝基板302，而電性連接至動態隨機存取記憶晶粒304。因此，藉由將導電柱126含括在層疊封裝元件200中，額外的封裝結構可接合至封裝結構100，而可電性連接至邏輯晶片102及/或記憶晶片104。
層疊封裝元件200包含封裝結構100，此封裝結構100具有接合之數個半導體晶片，例如邏輯晶片102(例如 應用處理器)與記憶晶片104(例如寬輸入輸出晶片)。封裝結構100中之各互連/扇出結構將這些半導體晶片電性連接至封裝基板。層疊封裝元件200中之其他互連/扇出結構可將這些半導體晶片電性連接至額外之封裝構件(例如封裝結構300及/或主機板)。因此，邏輯(例如應用處理器)與記憶(例如寬輸入輸出)晶片可利用扇出、層疊晶片與晶片基板鍵合結構(例如模封化合物、導電柱與重新分布層)來接合。層疊封裝元件200之可包含下列一或多個有利特徵：成本效益(例如因使用相對簡單之互連結構而無昂貴之穿基板介層窗)、能力的提升(例如因相較於其他記憶晶片，其具有包含寬輸入輸出晶片之能力)、提升之電性連接可靠度、提升之良率、較高之電性速度(例如因邏輯晶片102與記憶晶片212和304之間具有較短之繞線距離)、較薄之形狀因子、良好之層次2之可靠裕度(例如在溫度循環及/或落下測試中有改善的結果)及類似有利特徵。
圖11至圖19係繪示依照本發明之一些替代實施方式製造一種層疊封裝元件400(請參照圖19)之各個中間階段的剖面示意圖。圖11繪示載體401之剖面示意圖。載體401可為玻璃載體或類似物。一或多個重新分布層402可設置在載體101之上方。重新分布層402之數個導電部分(例如晶種層)可利用例如濺鍍製程、無電電鍍製程及類似製程來製作。重新分布層402之導電部分可由導電材料，例如銅、鈦、銀、金及類似材料所組成。可利用例如微影與蝕刻 之組合來圖案化重新分布層402，以使其包含數個接觸墊404。
圖12繪示出導電柱406附著於接觸墊404。導電柱406可實質類似於導電柱112與126。舉例而言，導電柱406可為預形成之結構(例如包含銅、銀、金及其類似物)，且附著於接觸墊108。在一些實施例中，導電柱406可具有約100μm至約500μm的間距。
圖13繪示出半導體晶片(例如邏輯晶片102)設置於載體401之上方。邏輯晶片102可為應用處理器，然亦可使用其他種半導體晶片(例如記憶晶片)。邏輯晶片102包含複數個導電樁408(例如銅樁)形成在邏輯晶片102之上表面的接觸墊上。導電樁408可提供邏輯晶片102中之主動元件/功能電路電性連接。邏輯晶片102可設置在載體401之上方，因此可利用例如適合之安置工具(pick and place tool)使導電樁408朝上。
接下來，如圖14所示，施加模封化合物410，以填充導電柱406與邏輯晶片102之間的間隙。模封化合物410可實質類似於模封化合物114。舉例而言，模封化合物410可以液體形式施加在導電柱406與邏輯晶片102之間。隨後，進行硬化製程，以固化模封化合物410。模封化合物410之填充可超過導電柱406/邏輯晶片102，如此模封化合物410覆蓋導電柱406/邏輯晶片102之上表面。
可進行化學機械研磨(或其他研磨/回蝕技術)，以暴露出導電柱406與邏輯晶片102上之導電樁408的 上表面。所形成之結構繪示於圖15中。於化學機械研磨後，模封化合物410、導電柱406與導電樁408之橫向表面可實質等高。此外，導電樁408可在化學機械研磨製程期間保護邏輯晶片102之其他特徵受損。導電柱406可延伸穿過模封化合物410，因此導電柱406亦可稱為穿模介層窗406。在由上而下的視圖(未繪示)中，模封化合物410可包圍邏輯晶片102。
圖16繪示出一或多個重新分布層412形成於邏輯晶片102之上方。重新分布層412可實質類似於重新分布層116，且重新分布層412可延伸經過邏輯晶片102之邊而至模封化合物410與導電柱406之上方。連接件414形成於重新分布層412之上方。連接件414可例如為間距約30μm至約100μm、且均高約30μm至約100μm的微凸塊。連接件414與重新分布層412提供邏輯晶片102與導電柱406電性連接。
接下來，如圖17所示，將另一半導體晶片，例如記憶晶片104，接合至連接件414。舉例而言，可在連接件414上進行回銲。隨後，可施加底部填充材416於邏輯晶片102與記憶晶片104之間並環繞連接件414。底部填充材416可提供接合件414支撐。記憶晶片104可透過重新分布層412而電性連接至邏輯晶片102。在一些實施例中，記憶晶片104可為寬輸入輸出晶片。
接著，將所形成之層疊封裝元件400自載體移開，並設置連接件418於重新分布層402之相對於邏輯晶片 102之底面上，如圖18所示。連接件418可例如具有約250μm至約500μm之間距的球柵陣列的球。連接件418可用以將層疊封裝結元件400電性連接至一電性系統之主機板(未繪示)或另一元件構件。導電柱406(以及層疊封裝元件400之其他戶連結構)提供連接件418與記憶晶片104之間的電性連接。
圖19繪示出額外的封裝構件選擇性接合於層疊封裝元件400中之邏輯晶片102/記憶晶片104。舉例而言，封裝結構300可接合於重新分布層412之相對於邏輯晶片102的表面。封裝結構300可為記憶體封裝，例如LP-DDR2封裝、LP-DDR3封裝及類似結構。封裝結構300可包含複數個堆疊之記憶晶粒(例如動態隨機存取記憶晶粒304)，這些動態隨機存取記憶晶粒304利用例如接合線306接合於封裝基板302。動態隨機存取記憶晶粒304與接合線306可為保護之模封化合物308所包覆。亦可使用其他類型之封裝結構。替代地，根據封裝設計，可省略封裝結構300。
連接件310可設置在封裝基板302之底面上。封裝結構300可利用連接件310而接合至重新分布層412。連接件310可具有較記憶晶片104大之垂直尺寸，且記憶晶片104可設置在封裝結構300與重新分布層412之間。邏輯晶片102及/或記憶晶片104可透過重新分布層412與層疊封裝元件400中之其他互連結構，而電性連接至動態隨機存取記憶晶粒304。
因此，完成了層疊封裝元件400。層疊封裝元件400包含扇出結構，此扇出結構具有邏輯晶片102、模封化合物410包圍邏輯晶片102、以及複數個導電柱406延伸穿過模封化合物410。重新分布層412設置在邏輯晶片102、模封化合物410與導電柱406之上方。將另一半導體晶片，例如記憶晶片104，接合至扇出結構，且透過重新分布層412電性連接邏輯晶片102。因此，邏輯(例如應用處理器)與記憶(例如寬輸入輸出)晶片可利用封裝結構(例如具有模封化合物、導電柱及/或重新分布層)而接合。層疊封裝元件400之可包含下列一或多個有利特徵：成本效益(例如因使用相對簡單之互連結構而無昂貴之穿基板介層窗)、能力的提升(例如因相較於其他記憶晶片，其具有包含寬輸入輸出晶片之能力)、提升之電性連接可靠度、提升之良率、較高之電性速度(例如因邏輯與記憶晶片之間具有較短之繞線距離)、較薄之形狀因子、良好之層次2之可靠裕度(例如在溫度循環及/或落下測試中有改善的結果)及類似有利特徵。
圖20至圖25係繪示依照本發明之一些其他替代實施方式製造一種層疊封裝元件400(請參照圖25)之各個中間階段的剖面示意圖。圖20繪示出載體401、重新分布層402、接觸墊404、導電柱406與半導體晶片102之剖面示意圖。圖20之各元件可實質類似於圖13之元件，其中相同之參考數字指定相同之元件。然而，保護層450可形成於邏輯晶片102之上方，而非導電柱408。保護層450覆蓋在形 成於邏輯晶片102之上表面的複數個接觸墊103上。在一些實施例中，保護層450可為保護之紫外線(UV)膠帶層，其可利用紫外光來分解。邏輯晶片102可設置在載體401之上方，因此可利用例如適合之安置工具使保護層450朝上。
接下來，如圖21所示，施加模封化合物410，以填充導電柱406與邏輯晶片102之間的間隙。模封化合物410之填充可超過導電柱406/邏輯晶片102，如此模封化合物410覆蓋導電柱406/邏輯晶片102之上表面。
可進行化學機械研磨(或其他研磨/回蝕技術)，以暴露出導電柱406與邏輯晶片102上之保護層450的上表面。所形成之結構繪示於圖22中。保護層450可在化學機械研磨製程期間保護邏輯晶片102之其他特徵受損。導電柱406可延伸穿過模封化合物410，因此導電柱406亦可稱為穿模介層窗406。在由上而下的視圖(未繪示)中，模封化合物410可包圍邏輯晶片102。
在圖23中，利用例如去膠製程(例如剝除)、暴露於紫外光、使用適合之化學溶液來溶解(例如鹼性溶液)及類似方法，移除保護層450。藉由移除保護層450，可暴露出邏輯晶片102之接觸墊103。於保護層450移除後，模封化合物410與導電柱406之橫向表面可較邏輯晶片102高。
圖24繪示出一或多個重新分布層412形成於邏輯晶片102之上方。由於邏輯晶片102可能低於模封化合物410之上表面，因此重新分布層410可延伸至模封化合物 410中，以直接電性連接邏輯晶片102之接觸墊103。重新分布層412可進一步延伸經過邏輯晶片102之邊而至模封化合物410與導電柱406之上方。連接件414接著形成於重新分布層412之上方。連接件414與重新分布層412提供邏輯晶片102與導電柱406電性連接。
製作層疊封裝元件之剩下的製程步驟可實質類似於圖17至圖19所述，為了簡潔之故而予以省略。圖25繪示出完成之層疊封裝元件400。因此，如圖21至圖25所示，可利用一替代製程來製作層疊封裝元件，其中重新分布層412直接連接邏輯晶片102中之接觸墊103，而無任何介於中間的導電樁408。在這樣的實施例中，因保護層450包含在製程流程中，所以重新分布層410可延伸經過模封化合物410之上表面。
因此，如上所述，具有邏輯與記憶晶片之各實施例的層疊封裝元件可利用各式扇出、層疊晶片與晶片基板鍵合結構來接合。各實施例之優點可包含速度與功率消耗的改善、較低之製作成本、能力增加、良率提升、較薄之形狀因子、層次2之可靠裕度的改善等等。
依照一實施例，一種層疊封裝元件包含封裝結構、封裝基板、以及複數個連接件將封裝結構接合至封裝基板。封裝結構包含邏輯晶片接合至記憶晶片、模封化合物包圍記憶晶片、以及複數個導電柱延伸穿過模封化合物。這些導電柱附著在邏輯晶片上之接觸墊。
依照另一實施例，一種層疊封裝元件包含邏輯晶片、模封化合物包圍邏輯晶片、以及一或多個第一重新分布層設於邏輯晶片與模封化合物之上方。此層疊封裝元件更包含複數個穿模介層窗，延伸穿過模封化合物且附著於一或複數個第二重新分布層。此一或複數個第二重新分布層設於第一模封化合物與邏輯晶片下。記憶晶片設於此一或複數個第一重新分布層之上方，且此一或複數個第一重新分布層將記憶晶片電性連接至邏輯晶片與穿模介層窗。
依照又一實施例，一種層疊封裝元件之製造方法，包含形成第一封裝結構以及接合第一封裝結構於封裝基板。形成第一封裝結構之方法包含接合邏輯晶片於記憶晶片(其中邏輯晶片包含複數個第一接觸墊)、將複數個第一預形成之導電柱附著於第一接觸墊、以及施加第一模封化合物於邏輯晶片上方且介於記憶晶片與每一預形成之導電柱之間。此方法更包含將複數個第二預形成之導電柱附著於封裝基板上之複數個第二接觸墊、以及施加第二模封化合物於封裝基板之上方且介於第一封裝結構與每一第二導電柱之間。
上述已概述數個實施例的特徵，因此熟習此技藝者可更了解本揭露之態樣。熟悉此技藝者應了解到，其可輕易地利用本揭露作為基礎，來設計或潤飾其他製程與結構，以實現與在此所介紹之實施例相同之目的及/或達到相同的優點。熟悉此技藝者也應了解到，這類對等架構並未脫離本揭露之精神和範圍，且熟悉此技藝者可在不脫離本揭露之精神和範圍下，在此進行各種之更動、取代與潤飾。
100‧‧‧封裝結構
102‧‧‧邏輯晶片
104‧‧‧記憶晶片
106‧‧‧連接件
112‧‧‧導電柱/穿模介層窗
114‧‧‧模封化合物
118‧‧‧連接件
120‧‧‧底部填充材
122‧‧‧接觸墊
124‧‧‧封裝基板
126‧‧‧導電柱/穿模介層窗
128‧‧‧模封化合物
200‧‧‧層疊封裝元件
300‧‧‧封裝結構
302‧‧‧封裝基板
304‧‧‧動態隨機存取記憶晶粒
306‧‧‧接合線
308‧‧‧模封化合物
310‧‧‧連接件

Claims (20)

  1. 一種層疊封裝元件，包含：一第一封裝結構，包含：一邏輯晶片，接合至一記憶晶片；一第一模封化合物，包圍該記憶晶片；以及複數個第一導電柱，延伸穿過該第一模封化合物，且附著該邏輯晶片上之複數個接觸墊；一第一封裝基板；以及複數個第一連接件，將該第一封裝結構接合至該第一封裝基板。
  2. 如申請專利範圍第1項之層疊封裝元件，更包含一或複數個重新分布層位於該記憶晶片之相對於該邏輯晶片的一表面上，其中該些第一連接件設於該或該些重新分布層之相對於該記憶晶片的一表面上。
  3. 如申請專利範圍第2項之層疊封裝元件，其中該些第一導電柱將該邏輯晶片電性連接至該或該些重新分布層。
  4. 如申請專利範圍第2項之層疊封裝元件，其中該或該些重新分布層延伸經過該記憶晶片之複數個邊而至該第一模封化合物與該些第一導電柱之上方。
  5. 如申請專利範圍第1項之層疊封裝元件，更包含：一第二模封化合物，包圍該第一封裝結構；以及複數個第二導電柱，延伸穿過該第二模封化合物且附著於該第一封裝基板上之複數個接觸墊。
  6. 如申請專利範圍第5項之層疊封裝元件，更包含：一第二封裝結構；以及複數個第二連接件，將該第二封裝結構電性連接至該第一封裝基板，其中該些第二連接件接合至該些第二導電柱。
  7. 如申請專利範圍第6項之層疊封裝元件，其中該第二封裝結構包含：複數個堆疊動態隨機存取記憶晶片；一第二封裝基板，接合至該些堆疊動態隨機存取記憶晶片；以及一第三模封化合物，包圍該些堆疊動態隨機存取記憶晶片。
  8. 如申請專利範圍第5項之層疊封裝元件，其中該第一封裝結構與該第二模封化合物之橫向面實質等高。
  9. 如申請專利範圍第1項之層疊封裝元件，其中該邏輯晶片為一應用處理器，且其中該記憶晶片為一寬輸入/輸出晶片。
  10. 一種層疊封裝元件，包含：一邏輯晶片；一第一模封化合物，包圍該邏輯晶片；複數個穿模介層窗，延伸穿過該第一模封化合物且附著於一或複數個第一重新分布層，其中該或該些第一重新分布層設於該第一模封化合物與該邏輯晶片下；一或複數個第二重新分布層，設於該邏輯晶片與該第一模封化合物之上方；以及一記憶晶片，設於該或該些第二重新分布層之上方，其中該或該些第二重新分布層將該記憶晶片電性連接至該邏輯晶片與該些穿模介層窗。
  11. 如申請專利範圍第10項之層疊封裝元件，其中該邏輯晶片包含複數個導電樁位於一上表面，且電性連接至該或該些第二重新分布層。
  12. 如申請專利範圍第11項之層疊封裝元件，其中該些導電樁、該第一模封化合物與該些穿模介層窗之上表面實質等高。
  13. 如申請專利範圍第10項之層疊封裝元件，其中該第一模封化合物之一上表面較該邏輯晶片之一上表面高，其中該或該些第二重新分布層部分延伸至該第一模封化合物中，且直接電性連接至位於該邏輯晶片之該上表面之複數個接觸墊。
  14. 如申請專利範圍第10項之層疊封裝元件，更包含一封裝結構電性連接至該或該些第二重新分布層。
  15. 如申請專利範圍第14項之層疊封裝元件，其中該封裝結構為一低功率雙倍數據傳輸率2封裝或一低功率雙倍數據傳輸率3封裝。
  16. 如申請專利範圍第15項之層疊封裝元件，更包含複數個連接件，將該封裝結構接合至該或該些第二重新分布層之一上表面，其中該記憶晶片設於該封裝結構與該或該些第二重新分布層之間。
  17. 如申請專利範圍第10項之層疊封裝元件，其中該邏輯晶片為一應用處理器，其中該記憶晶片為一寬輸入/輸出晶片。
  18. 一種方法，包含： 形成一第一封裝結構，其中形成該第一封裝結構之操作包含：接合一邏輯晶片於一記憶晶片，其中該邏輯晶片包含複數個第一接觸墊；將複數個第一預形成之導電柱附著於該些第一接觸墊；以及施加一第一模封化合物於該邏輯晶片上方且介於該記憶晶片與每一該些預形成之導電柱之間；接合該第一封裝結構於一封裝基板，其中該封裝基板包含複數個第二接觸墊；將複數個第二預形成之導電柱附著於該些第二接觸墊；以及施加一第二模封化合物於該封裝基板之上方且介於該第一封裝結構與每一該些第二導電柱之間。
  19. 如申請專利範圍第18項之方法，更包含接合一第二封裝結構於該些第二導電柱。
  20. 如申請專利範圍第18項之方法，其中形成該第一封裝結構之操作包含形成一或複數個重新分布層於該記憶晶片與該第一模封化合物上，其中該些第一導電柱將該邏輯晶片電性連接至該或該些重新分布層。
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US20170250170A1 (en) 2017-08-31
US11152344B2 (en) 2021-10-19
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